From nobody Wed Apr 29 00:37:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DECDC433EF for ; Thu, 26 May 2022 04:26:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237872AbiEZE0k (ORCPT ); Thu, 26 May 2022 00:26:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344644AbiEZE0e (ORCPT ); Thu, 26 May 2022 00:26:34 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5D7FEE05; Wed, 25 May 2022 21:26:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1653539189; x=1685075189; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=6dWY3+26t8TB/GSIL8PK4o7L40xIy3j+pMrLgaoYu7U=; b=W0Pl2okGc/jfLpNarbmSgu9/3DqqMbAOFKrCCfncZIEs6RCVa0XawcnL 31gLsmIre4+3bUBfmofWtn9BQUCgWqQcLkhlWyCBLUOh7BUzDuOtTxmHU 5Hn2dePRfwLIVY0b8/ou97ML7lNhVHdPolU4zJeNe5Ab6+dWN0HTiFWQ4 w=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-01.qualcomm.com with ESMTP; 25 May 2022 21:26:29 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2022 21:26:29 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 25 May 2022 21:26:28 -0700 Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 25 May 2022 21:26:24 -0700 From: Taniya Das To: Stephen Boyd , =?UTF-8?q?Michael=20Turquette=20=C2=A0?= , Bjorn Andersson CC: , , , , , , , Taniya Das Subject: [PATCH v3 1/3] dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280 Date: Thu, 26 May 2022 09:55:59 +0530 Message-ID: <20220526042601.32064-2-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220526042601.32064-1-quic_tdas@quicinc.com> References: <20220526042601.32064-1-quic_tdas@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks for SC7280. Update reg property min/max items in YAML schema. Fixes: 57405b795504 ("dt-bindings: clock: Add YAML schemas for LPASS clocks= on SC7280"). Signed-off-by: Taniya Das --- .../clock/qcom,sc7280-lpasscorecc.yaml | 19 ++++++++++++++++--- .../clock/qcom,lpassaudiocc-sc7280.h | 5 +++++ 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorec= c.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.ya= ml index bad9135489de..1d20cdcc69ff 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -22,6 +22,8 @@ properties: clock-names: true + reg: true + compatible: enum: - qcom,sc7280-lpassaoncc @@ -38,8 +40,8 @@ properties: '#power-domain-cells': const: 1 - reg: - maxItems: 1 + '#reset-cells': + const: 1 required: - compatible @@ -69,6 +71,11 @@ allOf: items: - const: bi_tcxo - const: lpass_aon_cc_main_rcg_clk_src + + reg: + items: + - description: lpass core cc register + - description: lpass audio csr register - if: properties: compatible: @@ -90,6 +97,8 @@ allOf: - const: bi_tcxo_ao - const: iface + reg: + maxItems: 1 - if: properties: compatible: @@ -108,6 +117,8 @@ allOf: items: - const: bi_tcxo + reg: + maxItems: 1 examples: - | #include @@ -116,13 +127,15 @@ examples: #include lpass_audiocc: clock-controller@3300000 { compatible =3D "qcom,sc7280-lpassaudiocc"; - reg =3D <0x3300000 0x30000>; + reg =3D <0x3300000 0x30000>, + <0x32a9000 0x1000>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; clock-names =3D "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; power-domains =3D <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; #clock-cells =3D <1>; #power-domain-cells =3D <1>; + #reset-cells =3D <1>; }; - | diff --git a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h b/include= /dt-bindings/clock/qcom,lpassaudiocc-sc7280.h index 20ef2ea673f3..22dcd47d4513 100644 --- a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h +++ b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h @@ -24,6 +24,11 @@ #define LPASS_AUDIO_CC_RX_MCLK_CLK 14 #define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15 +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_TX_CGCR 1 +#define LPASS_AUDIO_SWR_WSA_CGCR 2 + /* LPASS_AON_CC clocks */ #define LPASS_AON_CC_PLL 0 #define LPASS_AON_CC_PLL_OUT_EVEN 1 -- 2.17.1 From nobody Wed Apr 29 00:37:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 323EDC4332F for ; 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Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 25 May 2022 21:26:33 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2022 21:26:32 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 25 May 2022 21:26:31 -0700 Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 25 May 2022 21:26:28 -0700 From: Taniya Das To: Stephen Boyd , =?UTF-8?q?Michael=20Turquette=20=C2=A0?= , Bjorn Andersson CC: , , , , , , , Taniya Das Subject: [PATCH v3 2/3] dt-bindings: clock: Add support for external MCLKs for LPASS on SC7280 Date: Thu, 26 May 2022 09:56:00 +0530 Message-ID: <20220526042601.32064-3-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220526042601.32064-1-quic_tdas@quicinc.com> References: <20220526042601.32064-1-quic_tdas@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support external mclk to interface external MI2S clocks for SC7280. Fixes: 57405b795504 ("dt-bindings: clock: Add YAML schemas for LPASS clocks= on SC7280"). Signed-off-by: Taniya Das --- include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h b/include/= dt-bindings/clock/qcom,lpasscorecc-sc7280.h index 28ed2a07aacc..0324c69ce968 100644 --- a/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h +++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h @@ -19,6 +19,8 @@ #define LPASS_CORE_CC_LPM_CORE_CLK 9 #define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10 #define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11 +#define LPASS_CORE_CC_EXT_MCLK0_CLK 12 +#define LPASS_CORE_CC_EXT_MCLK0_CLK_SRC 13 /* LPASS_CORE_CC power domains */ #define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0 -- 2.17.1 From nobody Wed Apr 29 00:37:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9420BC433F5 for ; Thu, 26 May 2022 04:26:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345589AbiEZE0x (ORCPT ); Thu, 26 May 2022 00:26:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239088AbiEZE0m (ORCPT ); Thu, 26 May 2022 00:26:42 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8337EE1D; Wed, 25 May 2022 21:26:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1653539196; x=1685075196; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Pe6Wi8DVqmHt8ekxuGJOkmaUnohWx9M/ugvxsS8fsas=; b=sR2DjEuIp6Io9qFkeHs1zbedD0agkfxKFin1cZfaQJYYa45At8jW2MFb V+3Hes0YfpMaY0AYiJb7o0VxNO2VE8WFXoxV4dxV7ipfHwrQll3uJXpDH DIFwDJ3notLajymGwXiNB50fOmyjyeum/oSaAM26Mm/0WQCuTojXxMIuA 4=; Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 25 May 2022 21:26:36 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg05-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2022 21:26:35 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 25 May 2022 21:26:35 -0700 Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 25 May 2022 21:26:31 -0700 From: Taniya Das To: Stephen Boyd , =?UTF-8?q?Michael=20Turquette=20=C2=A0?= , Bjorn Andersson CC: , , , , , , , Taniya Das Subject: [PATCH v3 3/3] clk: qcom: lpass: Add support for resets & external mclk for SC7280 Date: Thu, 26 May 2022 09:56:01 +0530 Message-ID: <20220526042601.32064-4-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220526042601.32064-1-quic_tdas@quicinc.com> References: <20220526042601.32064-1-quic_tdas@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The clock gating control for TX/RX/WSA core bus clocks would be required to be reset(moved from hardware control) from audio core driver. Thus add the support for the reset clocks. Also add the external mclk to interface external MI2S. Fixes: 2b75e142523e ("clk: qcom: lpass: Add support for LPASS clock control= ler for SC7280"). Signed-off-by: Taniya Das --- drivers/clk/qcom/lpassaudiocc-sc7280.c | 17 ++++++++++++- drivers/clk/qcom/lpasscorecc-sc7280.c | 33 ++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpas= saudiocc-sc7280.c index 6ab6e5a34c72..536509b78341 100644 --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c @@ -22,6 +22,7 @@ #include "clk-regmap-mux.h" #include "common.h" #include "gdsc.h" +#include "reset.h" enum { P_BI_TCXO, @@ -221,7 +222,7 @@ static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = =3D { .parent_data =3D lpass_aon_cc_parent_data_0, .num_parents =3D ARRAY_SIZE(lpass_aon_cc_parent_data_0), .flags =3D CLK_OPS_PARENT_ENABLE, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; @@ -665,6 +666,18 @@ static const struct qcom_cc_desc lpass_audio_cc_sc7280= _desc =3D { .num_clks =3D ARRAY_SIZE(lpass_audio_cc_sc7280_clocks), }; +static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] =3D { + [LPASS_AUDIO_SWR_RX_CGCR] =3D { 0xa0, 1 }, + [LPASS_AUDIO_SWR_TX_CGCR] =3D { 0xa8, 1 }, + [LPASS_AUDIO_SWR_WSA_CGCR] =3D { 0xb0, 1 }, +}; + +static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc =3D { + .config =3D &lpass_audio_cc_sc7280_regmap_config, + .resets =3D lpass_audio_cc_sc7280_resets, + .num_resets =3D ARRAY_SIZE(lpass_audio_cc_sc7280_resets), +}; + static const struct of_device_id lpass_audio_cc_sc7280_match_table[] =3D { { .compatible =3D "qcom,sc7280-lpassaudiocc" }, { } @@ -741,6 +754,8 @@ static int lpass_audio_cc_sc7280_probe(struct platform_= device *pdev) return ret; } + ret =3D qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc= ); + pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); pm_runtime_put_sync(&pdev->dev); diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpass= corecc-sc7280.c index 1f1f1bd1b68e..6ad19b06b1ce 100644 --- a/drivers/clk/qcom/lpasscorecc-sc7280.c +++ b/drivers/clk/qcom/lpasscorecc-sc7280.c @@ -190,6 +190,19 @@ static struct clk_rcg2 lpass_core_cc_ext_if1_clk_src = =3D { }, }; +static struct clk_rcg2 lpass_core_cc_ext_mclk0_clk_src =3D { + .cmd_rcgr =3D 0x20000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D lpass_core_cc_parent_map_0, + .freq_tbl =3D ftbl_lpass_core_cc_ext_if0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "lpass_core_cc_ext_mclk0_clk_src", + .parent_data =3D lpass_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(lpass_core_cc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; static struct clk_branch lpass_core_cc_core_clk =3D { .halt_reg =3D 0x1f000, @@ -283,6 +296,24 @@ static struct clk_branch lpass_core_cc_lpm_mem0_core_c= lk =3D { }, }; +static struct clk_branch lpass_core_cc_ext_mclk0_clk =3D { + .halt_reg =3D 0x20014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "lpass_core_cc_ext_mclk0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &lpass_core_cc_ext_mclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch lpass_core_cc_sysnoc_mport_core_clk =3D { .halt_reg =3D 0x23000, .halt_check =3D BRANCH_HALT_VOTED, @@ -326,6 +357,8 @@ static struct clk_regmap *lpass_core_cc_sc7280_clocks[]= =3D { [LPASS_CORE_CC_LPM_CORE_CLK] =3D &lpass_core_cc_lpm_core_clk.clkr, [LPASS_CORE_CC_LPM_MEM0_CORE_CLK] =3D &lpass_core_cc_lpm_mem0_core_clk.cl= kr, [LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] =3D &lpass_core_cc_sysnoc_mport_cor= e_clk.clkr, + [LPASS_CORE_CC_EXT_MCLK0_CLK] =3D &lpass_core_cc_ext_mclk0_clk.clkr, + [LPASS_CORE_CC_EXT_MCLK0_CLK_SRC] =3D &lpass_core_cc_ext_mclk0_clk_src.cl= kr, }; static struct regmap_config lpass_core_cc_sc7280_regmap_config =3D { -- 2.17.1