From nobody Tue May 5 10:13:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE38CC433EF for ; Wed, 25 May 2022 15:41:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236560AbiEYPlz (ORCPT ); Wed, 25 May 2022 11:41:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245209AbiEYPlt (ORCPT ); Wed, 25 May 2022 11:41:49 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 567E32983F; Wed, 25 May 2022 08:41:48 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EBEE71474; Wed, 25 May 2022 08:41:47 -0700 (PDT) Received: from e121896.arm.com (unknown [10.57.8.252]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 61F953F73D; Wed, 25 May 2022 08:41:44 -0700 (PDT) From: James Clark To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: broonie@kernel.org, german.gomez@arm.com, leo.yan@linaro.org, mathieu.poirier@linaro.org, john.garry@huawei.com, James Clark , Will Deacon , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/5] perf tools: arm64: Use perf's copy of kernel headers Date: Wed, 25 May 2022 16:41:10 +0100 Message-Id: <20220525154114.718321-2-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220525154114.718321-1-james.clark@arm.com> References: <20220525154114.718321-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fix this include path to use perf's copy of the kernel header rather than the one from the root of the repo. This fixes build errors when only applying the perf tools part of a patchset rather than both sides. Reported-by: German Gomez Signed-off-by: James Clark Acked-by: Ian Rogers Tested-by: German Gomez --- tools/perf/util/libunwind/arm64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/libunwind/arm64.c b/tools/perf/util/libunwind/= arm64.c index 15f60fd09424..014d82159656 100644 --- a/tools/perf/util/libunwind/arm64.c +++ b/tools/perf/util/libunwind/arm64.c @@ -24,7 +24,7 @@ #include "unwind.h" #include "libunwind-aarch64.h" #define perf_event_arm_regs perf_event_arm64_regs -#include <../../../../arch/arm64/include/uapi/asm/perf_regs.h> +#include <../../../arch/arm64/include/uapi/asm/perf_regs.h> #undef perf_event_arm_regs #include "../../arch/arm64/util/unwind-libunwind.c" =20 --=20 2.28.0 From nobody Tue May 5 10:13:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EACCC433EF for ; Wed, 25 May 2022 15:42:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245238AbiEYPl7 (ORCPT ); Wed, 25 May 2022 11:41:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245229AbiEYPlz (ORCPT ); Wed, 25 May 2022 11:41:55 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BE0592BB24; Wed, 25 May 2022 08:41:52 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 792DF152B; Wed, 25 May 2022 08:41:52 -0700 (PDT) Received: from e121896.arm.com (unknown [10.57.8.252]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DEDDD3F73D; Wed, 25 May 2022 08:41:48 -0700 (PDT) From: James Clark To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: broonie@kernel.org, german.gomez@arm.com, leo.yan@linaro.org, mathieu.poirier@linaro.org, john.garry@huawei.com, James Clark , Will Deacon , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/5] perf tools: arm64: Copy perf_regs.h from the kernel Date: Wed, 25 May 2022 16:41:11 +0100 Message-Id: <20220525154114.718321-3-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220525154114.718321-1-james.clark@arm.com> References: <20220525154114.718321-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Get the updated header for the newly added VG register. Reviewed-by: Leo Yan Signed-off-by: James Clark --- tools/arch/arm64/include/uapi/asm/perf_regs.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/arch/arm64/include/uapi/asm/perf_regs.h b/tools/arch/arm= 64/include/uapi/asm/perf_regs.h index d54daafa89e3..fd157f46727e 100644 --- a/tools/arch/arm64/include/uapi/asm/perf_regs.h +++ b/tools/arch/arm64/include/uapi/asm/perf_regs.h @@ -36,6 +36,11 @@ enum perf_event_arm_regs { PERF_REG_ARM64_LR, PERF_REG_ARM64_SP, PERF_REG_ARM64_PC, - PERF_REG_ARM64_MAX, + + /* Extended/pseudo registers */ + PERF_REG_ARM64_VG =3D 46, // SVE Vector Granule + + PERF_REG_ARM64_MAX =3D PERF_REG_ARM64_PC + 1, + PERF_REG_ARM64_EXTENDED_MAX =3D PERF_REG_ARM64_VG + 1 }; #endif /* _ASM_ARM64_PERF_REGS_H */ --=20 2.28.0 From nobody Tue May 5 10:13:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D98FAC433FE for ; Wed, 25 May 2022 15:42:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245263AbiEYPmI (ORCPT ); Wed, 25 May 2022 11:42:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245225AbiEYPl7 (ORCPT ); Wed, 25 May 2022 11:41:59 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 075832DD45; Wed, 25 May 2022 08:41:57 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BBA351424; Wed, 25 May 2022 08:41:56 -0700 (PDT) Received: from e121896.arm.com (unknown [10.57.8.252]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 89DF53F73D; Wed, 25 May 2022 08:41:53 -0700 (PDT) From: James Clark To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: broonie@kernel.org, german.gomez@arm.com, leo.yan@linaro.org, mathieu.poirier@linaro.org, john.garry@huawei.com, James Clark , Will Deacon , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/5] perf tools: Use dynamic register set for Dwarf unwind Date: Wed, 25 May 2022 16:41:12 +0100 Message-Id: <20220525154114.718321-4-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220525154114.718321-1-james.clark@arm.com> References: <20220525154114.718321-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Architectures can detect availability of extra registers at runtime so use this more complete set for unwinding. This will include the VG register on arm64 in a later commit. If the function isn't implemented then PERF_REGS_MASK is returned and there is no change. Reviewed-by: Leo Yan Signed-off-by: James Clark --- tools/perf/util/evsel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index ef169ad15236..020836a4c4bc 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -896,7 +896,7 @@ static void __evsel__config_callchain(struct evsel *evs= el, struct record_opts *o "specifying a subset with --user-regs may render DWARF unwinding u= nreliable, " "so the minimal registers set (IP, SP) is explicitly forced.\n"); } else { - attr->sample_regs_user |=3D PERF_REGS_MASK; + attr->sample_regs_user |=3D arch__user_reg_mask(); } attr->sample_stack_user =3D param->dump_size; attr->exclude_callchain_user =3D 1; --=20 2.28.0 From nobody Tue May 5 10:13:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96CFAC433EF for ; Wed, 25 May 2022 15:42:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245246AbiEYPmM (ORCPT ); Wed, 25 May 2022 11:42:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245256AbiEYPmF (ORCPT ); Wed, 25 May 2022 11:42:05 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4CF2431378; Wed, 25 May 2022 08:42:01 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E696F1424; Wed, 25 May 2022 08:42:00 -0700 (PDT) Received: from e121896.arm.com (unknown [10.57.8.252]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A02F13F73D; Wed, 25 May 2022 08:41:57 -0700 (PDT) From: James Clark To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: broonie@kernel.org, german.gomez@arm.com, leo.yan@linaro.org, mathieu.poirier@linaro.org, john.garry@huawei.com, James Clark , Will Deacon , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 4/5] perf tools: arm64: Decouple Libunwind register names from Perf Date: Wed, 25 May 2022 16:41:13 +0100 Message-Id: <20220525154114.718321-5-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220525154114.718321-1-james.clark@arm.com> References: <20220525154114.718321-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Dwarf register numbers and real register numbers on aarch64 are equivalent. Remove the references to the register names from Libunwind so that new registers are supported without having to add build time feature checks for each new register. The unwinder won't ask for a register that it doesn't know about and Perf will already report an error for an unknown or unrecorded register in the perf_reg_value() function so extra validation isn't needed. After this change the new VG register can be read by libunwind. Reviewed-by: Leo Yan Signed-off-by: James Clark --- tools/perf/arch/arm64/util/unwind-libunwind.c | 73 +------------------ 1 file changed, 2 insertions(+), 71 deletions(-) diff --git a/tools/perf/arch/arm64/util/unwind-libunwind.c b/tools/perf/arc= h/arm64/util/unwind-libunwind.c index 5aecf88e3de6..871af5992298 100644 --- a/tools/perf/arch/arm64/util/unwind-libunwind.c +++ b/tools/perf/arch/arm64/util/unwind-libunwind.c @@ -10,77 +10,8 @@ =20 int LIBUNWIND__ARCH_REG_ID(int regnum) { - switch (regnum) { - case UNW_AARCH64_X0: - return PERF_REG_ARM64_X0; - case UNW_AARCH64_X1: - return PERF_REG_ARM64_X1; - case UNW_AARCH64_X2: - return PERF_REG_ARM64_X2; - case UNW_AARCH64_X3: - return PERF_REG_ARM64_X3; - case UNW_AARCH64_X4: - return PERF_REG_ARM64_X4; - case UNW_AARCH64_X5: - return PERF_REG_ARM64_X5; - case UNW_AARCH64_X6: - return PERF_REG_ARM64_X6; - case UNW_AARCH64_X7: - return PERF_REG_ARM64_X7; - case UNW_AARCH64_X8: - return PERF_REG_ARM64_X8; - case UNW_AARCH64_X9: - return PERF_REG_ARM64_X9; - case UNW_AARCH64_X10: - return PERF_REG_ARM64_X10; - case UNW_AARCH64_X11: - return PERF_REG_ARM64_X11; - case UNW_AARCH64_X12: - return PERF_REG_ARM64_X12; - case UNW_AARCH64_X13: - return PERF_REG_ARM64_X13; - case UNW_AARCH64_X14: - return PERF_REG_ARM64_X14; - case UNW_AARCH64_X15: - return PERF_REG_ARM64_X15; - case UNW_AARCH64_X16: - return PERF_REG_ARM64_X16; - case UNW_AARCH64_X17: - return PERF_REG_ARM64_X17; - case UNW_AARCH64_X18: - return PERF_REG_ARM64_X18; - case UNW_AARCH64_X19: - return PERF_REG_ARM64_X19; - case UNW_AARCH64_X20: - return PERF_REG_ARM64_X20; - case UNW_AARCH64_X21: - return PERF_REG_ARM64_X21; - case UNW_AARCH64_X22: - return PERF_REG_ARM64_X22; - case UNW_AARCH64_X23: - return PERF_REG_ARM64_X23; - case UNW_AARCH64_X24: - return PERF_REG_ARM64_X24; - case UNW_AARCH64_X25: - return PERF_REG_ARM64_X25; - case UNW_AARCH64_X26: - return PERF_REG_ARM64_X26; - case UNW_AARCH64_X27: - return PERF_REG_ARM64_X27; - case UNW_AARCH64_X28: - return PERF_REG_ARM64_X28; - case UNW_AARCH64_X29: - return PERF_REG_ARM64_X29; - case UNW_AARCH64_X30: - return PERF_REG_ARM64_LR; - case UNW_AARCH64_SP: - return PERF_REG_ARM64_SP; - case UNW_AARCH64_PC: - return PERF_REG_ARM64_PC; - default: - pr_err("unwind: invalid reg id %d\n", regnum); + if (regnum < 0 || regnum >=3D PERF_REG_ARM64_EXTENDED_MAX) return -EINVAL; - } =20 - return -EINVAL; + return regnum; } --=20 2.28.0 From nobody Tue May 5 10:13:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBF70C433EF for ; Wed, 25 May 2022 15:42:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232320AbiEYPmR (ORCPT ); Wed, 25 May 2022 11:42:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245230AbiEYPmH (ORCPT ); Wed, 25 May 2022 11:42:07 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 519D72FE74; Wed, 25 May 2022 08:42:05 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8894E1474; Wed, 25 May 2022 08:42:05 -0700 (PDT) Received: from e121896.arm.com (unknown [10.57.8.252]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D57BB3F73D; Wed, 25 May 2022 08:42:01 -0700 (PDT) From: James Clark To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: broonie@kernel.org, german.gomez@arm.com, leo.yan@linaro.org, mathieu.poirier@linaro.org, john.garry@huawei.com, James Clark , Will Deacon , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 5/5] perf tools: arm64: Add support for VG register Date: Wed, 25 May 2022 16:41:14 +0100 Message-Id: <20220525154114.718321-6-james.clark@arm.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20220525154114.718321-1-james.clark@arm.com> References: <20220525154114.718321-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the name of the VG register so it can be used in --user-regs The event will fail to open if the register is requested but not available so only add it to the mask if the kernel supports sve and also if it supports that specific register. Reviewed-by: Leo Yan Signed-off-by: James Clark --- tools/perf/arch/arm64/util/perf_regs.c | 34 ++++++++++++++++++++++++++ tools/perf/util/perf_regs.c | 2 ++ 2 files changed, 36 insertions(+) diff --git a/tools/perf/arch/arm64/util/perf_regs.c b/tools/perf/arch/arm64= /util/perf_regs.c index 476b037eea1c..c0a921512a90 100644 --- a/tools/perf/arch/arm64/util/perf_regs.c +++ b/tools/perf/arch/arm64/util/perf_regs.c @@ -2,9 +2,11 @@ #include #include #include +#include #include #include =20 +#include "../../../perf-sys.h" #include "../../../util/debug.h" #include "../../../util/event.h" #include "../../../util/perf_regs.h" @@ -43,6 +45,7 @@ const struct sample_reg sample_reg_masks[] =3D { SMPL_REG(lr, PERF_REG_ARM64_LR), SMPL_REG(sp, PERF_REG_ARM64_SP), SMPL_REG(pc, PERF_REG_ARM64_PC), + SMPL_REG(vg, PERF_REG_ARM64_VG), SMPL_REG_END }; =20 @@ -131,3 +134,34 @@ int arch_sdt_arg_parse_op(char *old_op, char **new_op) =20 return SDT_ARG_VALID; } + +uint64_t arch__user_reg_mask(void) +{ + struct perf_event_attr attr =3D { + .type =3D PERF_TYPE_HARDWARE, + .config =3D PERF_COUNT_HW_CPU_CYCLES, + .sample_type =3D PERF_SAMPLE_REGS_USER, + .disabled =3D 1, + .exclude_kernel =3D 1, + .sample_period =3D 1, + .sample_regs_user =3D PERF_REGS_MASK + }; + int fd; + + if (getauxval(AT_HWCAP) & HWCAP_SVE) + attr.sample_regs_user |=3D SMPL_REG_MASK(PERF_REG_ARM64_VG); + + /* + * Check if the pmu supports perf extended regs, before + * returning the register mask to sample. + */ + if (attr.sample_regs_user !=3D PERF_REGS_MASK) { + event_attr_init(&attr); + fd =3D sys_perf_event_open(&attr, 0, -1, -1, 0); + if (fd !=3D -1) { + close(fd); + return attr.sample_regs_user; + } + } + return PERF_REGS_MASK; +} diff --git a/tools/perf/util/perf_regs.c b/tools/perf/util/perf_regs.c index a982e40ee5a9..872dd3d38782 100644 --- a/tools/perf/util/perf_regs.c +++ b/tools/perf/util/perf_regs.c @@ -103,6 +103,8 @@ static const char *__perf_reg_name_arm64(int id) return "lr"; case PERF_REG_ARM64_PC: return "pc"; + case PERF_REG_ARM64_VG: + return "vg"; default: return NULL; } --=20 2.28.0