From nobody Tue May 5 10:12:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E0DEC433FE for ; Wed, 25 May 2022 15:11:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243251AbiEYPLf (ORCPT ); Wed, 25 May 2022 11:11:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242439AbiEYPL1 (ORCPT ); Wed, 25 May 2022 11:11:27 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 95175AFAE4 for ; Wed, 25 May 2022 08:11:24 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id u12-20020a17090a1d4c00b001df78c7c209so1933595pju.1 for ; Wed, 25 May 2022 08:11:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bRYOEpeP8mCOnNEZuD4+iCUOqYnaouRYbges9HW9UzU=; b=fB7U5PYG4dbc2mUatzOeTVyMCW80Xn1V5J4gnethuZNXdHnYuttFdcoU/AEphupbov zUGFLG9Mz+1uQtzY+8NGIAiNJ0D8OgrbJsMASU26h3tP45Rweo+eTPyfXXabYZpPqqt6 e1r7cajKXogHIIKNu1pM5zWSAUQt9oc1lFNfIYYghr5SdCvUNmGfxu5vuigKuuccNGaA uD9Ln7t1Y5xARYxWZaXXDJFKLCdnHi102CkaLnBAM9jb2TFz81aI735OVi0D3oC0HDDQ TtM3LRl9f+CGL1+gZSBvJ/SGRyaxfMxbfwIxwG19xqVPJkEzhEaMXn6E0y9BmGQS2x65 Iz6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bRYOEpeP8mCOnNEZuD4+iCUOqYnaouRYbges9HW9UzU=; b=WY6tN2lgDCfEqSykNRl/E+xETfGRrflmnZP5GcOEeEEO/+ER52iqevh3o9t5rE9Zdo QGqq5F6z95EHBbOLCjzcCQu9SkPeUMbmGm7TGwuda9WTqIBvAoNpGlI0yebVG62t2q/c v7pHKrYZaKHbkVK9WgDnIDyyMQWt4rP0ADIaXASuKXD5qLmUSSCpiT/1u69m/ERoomh0 bkFuMfxnIsYgqK53la1e6o4i171MSvB+bZW8QEn757TwJWbwbJ0AHfHfzYHosOHY+xy8 ld+fnvQRdQZTZox3ADbsjJ5nEln6/rSRUBydeFRyqKf94FopSEHBALObSQOJdAzPT9s5 rEEw== X-Gm-Message-State: AOAM530zIRC6emCij30GX+92OQSRkdfODr60nfrdJQK7Knyx8Bwh/6JG OY63XYDn8ExappPg7iEmQDG56A== X-Google-Smtp-Source: ABdhPJyvLJhZ25tdT27CnU0AAM2lFzx+JKOH7YUo/53c5dnjCKRLax1PKiPS3cY+JYL3ORleGvObXw== X-Received: by 2002:a17:902:d154:b0:163:5b66:564a with SMTP id t20-20020a170902d15400b001635b66564amr3395194plt.37.1653491483527; Wed, 25 May 2022 08:11:23 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id q16-20020a170902eb9000b00161b50c3db4sm9383129plg.94.2022.05.25.08.11.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 May 2022 08:11:23 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH 1/5] riscv: cpu_ops_sbi: Support for 64bit hartid Date: Wed, 25 May 2022 20:41:02 +0530 Message-Id: <20220525151106.2176147-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220525151106.2176147-1-sunilvl@ventanamicro.com> References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The hartid can be a 64bit value on RV64 platforms. This patch modifies the hartid variable type to unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L Reviewed-by: Heinrich Schuchardt --- arch/riscv/kernel/cpu_ops_sbi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sb= i.c index 4f5a6f84e2a4..efa0f0816634 100644 --- a/arch/riscv/kernel/cpu_ops_sbi.c +++ b/arch/riscv/kernel/cpu_ops_sbi.c @@ -65,7 +65,7 @@ static int sbi_hsm_hart_get_status(unsigned long hartid) static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle) { unsigned long boot_addr =3D __pa_symbol(secondary_start_sbi); - int hartid =3D cpuid_to_hartid_map(cpuid); + unsigned long hartid =3D cpuid_to_hartid_map(cpuid); unsigned long hsm_data; struct sbi_hart_boot_data *bdata =3D &per_cpu(boot_data, cpuid); =20 @@ -107,7 +107,7 @@ static void sbi_cpu_stop(void) static int sbi_cpu_is_stopped(unsigned int cpuid) { int rc; - int hartid =3D cpuid_to_hartid_map(cpuid); + unsigned long hartid =3D cpuid_to_hartid_map(cpuid); =20 rc =3D sbi_hsm_hart_get_status(hartid); =20 --=20 2.25.1 From nobody Tue May 5 10:12:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0BC1C433FE for ; Wed, 25 May 2022 15:11:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242647AbiEYPLm (ORCPT ); Wed, 25 May 2022 11:11:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243199AbiEYPLc (ORCPT ); Wed, 25 May 2022 11:11:32 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77A0AAFB09 for ; Wed, 25 May 2022 08:11:28 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id z11so10151913pjc.3 for ; Wed, 25 May 2022 08:11:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oVcwfs7LaLIcj8lD0NxblPY5TrT7/xc4rcWLu0GbH70=; b=coceHEo+uv0xofNyutF8KiY+u4PV6Q6q9xmbXvvXEGUoUIAew/qQzpeRkD/GbADPdv rMRlGpgN3VAC2YJjmyNiRZWOiFsXecrEerYxZmn+m/Y5NeGUWYcDxnh8umnlU/jvMjYd d8sc1IlKcPL6MFLm5Vv1tMCWqG+ZVsFgOFgt6bnci0h+K0TzBhy9UY8adMbssZYWIX/F ZSAMTANEQJtrQainm/5YfOp+Iq7f6c0ZsiCoAjkRJy+uDdeMt88mPVyUYJkDEf7OlZeD sgObM/VXLGHpbKfWbhP00sd+0gSX+i/RtUWiWU+Zfi7sBZMIOpI6/LCkdgF5Wh64Opvd qVsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oVcwfs7LaLIcj8lD0NxblPY5TrT7/xc4rcWLu0GbH70=; b=7Aw2HpwmA13+91hKOjP4XGvrrGFd7tfGScvVhPKfTkJENPxmL6YiY9TQEhARZYtvka Z7iCuShtp0+/vGvki90UmpTRrik2kMN3d/X8TbNHYzVUDAYIo1x09+H7FAX42ovqTZeA N7fBGJgPvYgY2FscnE2Q5Ltb3QAyZrAHQsbMQgjOFW19usG5LeS8vjQC6NEjoOvcuyuN HoRcoOX5AGRUHjEa8Bclrhaq3upIt95E0nMUHWduX9EERnwqwoDDxx0eMXnnbY85KIvz UCv/VxD+FUCwUp2ZFpvrH+BrIGOdw2DG80MFrVnhpydukv35z1o4+ekyB/+4ofEuBzJS Nacg== X-Gm-Message-State: AOAM531EVslb9CnacXZra+BMKINU0bhrHEWpvfJ/BDVvKH2Ov2ZqZhLc IB60Q9R5YLTPTi1+TVwNGJyUaw== X-Google-Smtp-Source: ABdhPJxNl6pWvjOH0gmcPXnjFKnF2aho/BIbIKdow5euUMkaXYfoVmFi2m9UhxAJyH5LYHt6hHL3Gg== X-Received: by 2002:a17:90b:4d12:b0:1e0:44a8:4a09 with SMTP id mw18-20020a17090b4d1200b001e044a84a09mr10865887pjb.189.1653491487665; Wed, 25 May 2022 08:11:27 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id q16-20020a170902eb9000b00161b50c3db4sm9383129plg.94.2022.05.25.08.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 May 2022 08:11:27 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH 2/5] riscv: cpu_ops_spinwait: Support for 64bit hartid Date: Wed, 25 May 2022 20:41:03 +0530 Message-Id: <20220525151106.2176147-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220525151106.2176147-1-sunilvl@ventanamicro.com> References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The hartid can be a 64bit value on RV64 platforms. This patch modifies the hartid variable type to unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L --- arch/riscv/kernel/cpu_ops_spinwait.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpu_ops_spinwait.c b/arch/riscv/kernel/cpu_o= ps_spinwait.c index 346847f6c41c..51ac07514a62 100644 --- a/arch/riscv/kernel/cpu_ops_spinwait.c +++ b/arch/riscv/kernel/cpu_ops_spinwait.c @@ -18,7 +18,7 @@ void *__cpu_spinwait_task_pointer[NR_CPUS] __section(".da= ta"); static void cpu_update_secondary_bootdata(unsigned int cpuid, struct task_struct *tidle) { - int hartid =3D cpuid_to_hartid_map(cpuid); + unsigned long hartid =3D cpuid_to_hartid_map(cpuid); =20 /* * The hartid must be less than NR_CPUS to avoid out-of-bound access --=20 2.25.1 From nobody Tue May 5 10:12:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F579C433F5 for ; Wed, 25 May 2022 15:12:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245041AbiEYPL7 (ORCPT ); Wed, 25 May 2022 11:11:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245047AbiEYPLp (ORCPT ); Wed, 25 May 2022 11:11:45 -0400 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52502B0A52 for ; Wed, 25 May 2022 08:11:33 -0700 (PDT) Received: by mail-pg1-x52d.google.com with SMTP id g184so19145620pgc.1 for ; Wed, 25 May 2022 08:11:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u3hj7ydFHDyTF3uUIDzuU/DKrZho4pwFZBNazS2zRYc=; b=KjBynz0SRbfVN3qpMXC7kjtpgmOMzEDF8I0kN4EzFYmcp/sm5REo7Nlfa21pZ5OLVe Hh0YxZ78ieeuqraEzEy22mseLwehS/ARrNVnyRZUhpey1Xk+YrVBk536tFwnYRfxE7kD FgbAxpiogw7wRP6IEajjgeX2s2podEV2yFbUJPQktj9kfTXJKsGWahWkRrjgvWRQetMy 8ydMLRvo69FdYjIR2/08s78ADO30emLwYV3bYUVNLnTSKVyrxgNwc60jhLBhvJCpg6OX 733n3UOS7X/9+la7j0WBxnMSILir1P4SgmEYn5BNzLWNm6Pv13eMyM1d/wMrAy0aa9Z+ h3YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u3hj7ydFHDyTF3uUIDzuU/DKrZho4pwFZBNazS2zRYc=; b=4m/icx+4x7477TSmfGly9VIUxXTeWQXb3GKYsExUnr9xM2LzCul/chWDYIrtxRA+z0 OhFyZ0/O1aTXFK8BNG4nmsd9gMby5dZXJS9vWGrSzfbhloRxZIbCI7CJ3WF5U8RZ1RLm gAPxrTNL5A9E5Qydeb2+S5ZItyj/dZcoUlvB8VMqnjJQEmT8wSsvS36pwOtRGHbA4NZR Gj8ZZ06rdM1EJhsihpqByWd0JHaYbiu6/BwBekRv9F7c0gcg6Z/7yAceTuIXAJHCdaWj rauuzqe5yxM70aPZg+qOJu/35124EIreZ8ONtTxyxGZVO+K7Zxgcf9bkPscEJcW5AfM0 s+AQ== X-Gm-Message-State: AOAM532KxBMqgoSyzGESd9sYVtmymzJAimArWPqPBIGzr8NzPT+lBDbv VBj1fegyUuWthvaAMmytB0nQwQ== X-Google-Smtp-Source: ABdhPJyR9tP9G0ssvONjCOVSdg70Xwqd7QhKiD+f4DqfrnhmEii7E7/6476AvAs2018HColuzqkvdQ== X-Received: by 2002:a63:a06:0:b0:3c2:3345:bf99 with SMTP id 6-20020a630a06000000b003c23345bf99mr29126038pgk.477.1653491491632; Wed, 25 May 2022 08:11:31 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id q16-20020a170902eb9000b00161b50c3db4sm9383129plg.94.2022.05.25.08.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 May 2022 08:11:31 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH 3/5] riscv: smp: Support for 64bit hartid Date: Wed, 25 May 2022 20:41:04 +0530 Message-Id: <20220525151106.2176147-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220525151106.2176147-1-sunilvl@ventanamicro.com> References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The hartid can be a 64bit value on RV64 platforms. This patch modifies the hartid parameter in riscv_hartid_to_cpuid() as unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L Reviewed-by: Heinrich Schuchardt --- arch/riscv/include/asm/smp.h | 4 ++-- arch/riscv/kernel/smp.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 23170c933d73..d3443be7eedc 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -42,7 +42,7 @@ void arch_send_call_function_ipi_mask(struct cpumask *mas= k); /* Hook for the generic smp_call_function_single() routine. */ void arch_send_call_function_single_ipi(int cpu); =20 -int riscv_hartid_to_cpuid(int hartid); +int riscv_hartid_to_cpuid(unsigned long hartid); =20 /* Set custom IPI operations */ void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops); @@ -70,7 +70,7 @@ static inline void show_ipi_stats(struct seq_file *p, int= prec) { } =20 -static inline int riscv_hartid_to_cpuid(int hartid) +static inline int riscv_hartid_to_cpuid(unsigned long hartid) { if (hartid =3D=3D boot_cpu_hartid) return 0; diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index b5d30ea92292..018e7dc45df6 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -47,7 +47,7 @@ static struct { unsigned long bits ____cacheline_aligned; } ipi_data[NR_CPUS] __cacheline_aligned; =20 -int riscv_hartid_to_cpuid(int hartid) +int riscv_hartid_to_cpuid(unsigned long hartid) { int i; =20 @@ -55,7 +55,7 @@ int riscv_hartid_to_cpuid(int hartid) if (cpuid_to_hartid_map(i) =3D=3D hartid) return i; =20 - pr_err("Couldn't find cpu id for hartid [%d]\n", hartid); + pr_err("Couldn't find cpu id for hartid [%lu]\n", hartid); return -ENOENT; } =20 --=20 2.25.1 From nobody Tue May 5 10:12:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01E85C433EF for ; Wed, 25 May 2022 15:12:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245121AbiEYPMI (ORCPT ); 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Wed, 25 May 2022 08:11:35 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH 4/5] riscv: cpu: Support for 64bit hartid Date: Wed, 25 May 2022 20:41:05 +0530 Message-Id: <20220525151106.2176147-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220525151106.2176147-1-sunilvl@ventanamicro.com> References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds support for 64bit hartid in riscv_of_processor_hartid() - Separate return value and status code. - Make hartid variable type as unsigned long. - Update the callers. Signed-off-by: Sunil V L --- arch/riscv/include/asm/processor.h | 4 ++-- arch/riscv/kernel/cpu.c | 26 +++++++++++++++----------- arch/riscv/kernel/cpufeature.c | 6 ++++-- arch/riscv/kernel/smpboot.c | 9 +++++---- drivers/clocksource/timer-riscv.c | 15 ++++++++------- drivers/irqchip/irq-riscv-intc.c | 7 ++++--- drivers/irqchip/irq-sifive-plic.c | 7 ++++--- 7 files changed, 42 insertions(+), 32 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 0749924d9e55..99fae9398506 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -75,8 +75,8 @@ static inline void wait_for_interrupt(void) } =20 struct device_node; -int riscv_of_processor_hartid(struct device_node *node); -int riscv_of_parent_hartid(struct device_node *node); +int riscv_of_processor_hartid(struct device_node *node, unsigned long *har= tid); +int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid= ); =20 extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struc= t *src); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ccb617791e56..c49ed1eac011 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -14,37 +14,36 @@ * Returns the hart ID of the given device tree node, or -ENODEV if the no= de * isn't an enabled and valid RISC-V hart node. */ -int riscv_of_processor_hartid(struct device_node *node) +int riscv_of_processor_hartid(struct device_node *node, unsigned long *har= t) { const char *isa; - u32 hart; =20 if (!of_device_is_compatible(node, "riscv")) { pr_warn("Found incompatible CPU\n"); return -ENODEV; } =20 - hart =3D of_get_cpu_hwid(node, 0); - if (hart =3D=3D ~0U) { + *hart =3D (unsigned long) of_get_cpu_hwid(node, 0); + if (*hart =3D=3D ~0U) { pr_warn("Found CPU without hart ID\n"); return -ENODEV; } =20 if (!of_device_is_available(node)) { - pr_info("CPU with hartid=3D%d is not available\n", hart); + pr_info("CPU with hartid=3D%lu is not available\n", *hart); return -ENODEV; } =20 if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=3D%d has no \"riscv,isa\" property\n", hart); + pr_warn("CPU with hartid=3D%lu has no \"riscv,isa\" property\n", *hart); return -ENODEV; } if (isa[0] !=3D 'r' || isa[1] !=3D 'v') { - pr_warn("CPU with hartid=3D%d has an invalid ISA of \"%s\"\n", hart, isa= ); + pr_warn("CPU with hartid=3D%lu has an invalid ISA of \"%s\"\n", *hart, i= sa); return -ENODEV; } =20 - return hart; + return 0; } =20 /* @@ -53,11 +52,16 @@ int riscv_of_processor_hartid(struct device_node *node) * To achieve this, we walk up the DT tree until we find an active * RISC-V core (HART) node and extract the cpuid from it. */ -int riscv_of_parent_hartid(struct device_node *node) +int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) { + int rc; + for (; node; node =3D node->parent) { - if (of_device_is_compatible(node, "riscv")) - return riscv_of_processor_hartid(node); + if (of_device_is_compatible(node, "riscv")) { + rc =3D riscv_of_processor_hartid(node, hartid); + if (!rc) + return 0; + } } =20 return -1; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b2d42d7f589..49c05bd9352d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -67,8 +67,9 @@ void __init riscv_fill_hwcap(void) struct device_node *node; const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - int i, j; + int i, j, rc; static unsigned long isa2hwcap[256] =3D {0}; + unsigned long hartid; =20 isa2hwcap['i'] =3D isa2hwcap['I'] =3D COMPAT_HWCAP_ISA_I; isa2hwcap['m'] =3D isa2hwcap['M'] =3D COMPAT_HWCAP_ISA_M; @@ -86,7 +87,8 @@ void __init riscv_fill_hwcap(void) DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; =20 - if (riscv_of_processor_hartid(node) < 0) + rc =3D riscv_of_processor_hartid(node, &hartid); + if (rc < 0) continue; =20 if (of_property_read_string(node, "riscv,isa", &isa)) { diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 622f226454d5..4336610a19ee 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -76,15 +76,16 @@ void __init smp_prepare_cpus(unsigned int max_cpus) void __init setup_smp(void) { struct device_node *dn; - int hart; + unsigned long hart; bool found_boot_cpu =3D false; int cpuid =3D 1; + int rc; =20 cpu_set_ops(0); =20 for_each_of_cpu_node(dn) { - hart =3D riscv_of_processor_hartid(dn); - if (hart < 0) + rc =3D riscv_of_processor_hartid(dn, &hart); + if (rc < 0) continue; =20 if (hart =3D=3D cpuid_to_hartid_map(0)) { @@ -94,7 +95,7 @@ void __init setup_smp(void) continue; } if (cpuid >=3D NR_CPUS) { - pr_warn("Invalid cpuid [%d] for hartid [%d]\n", + pr_warn("Invalid cpuid [%d] for hartid [%lu]\n", cpuid, hart); continue; } diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-= riscv.c index 1767f8bf2013..55142c27f0bc 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -101,20 +101,21 @@ static irqreturn_t riscv_timer_interrupt(int irq, voi= d *dev_id) =20 static int __init riscv_timer_init_dt(struct device_node *n) { - int cpuid, hartid, error; + int cpuid, error; + unsigned long hartid; struct device_node *child; struct irq_domain *domain; =20 - hartid =3D riscv_of_processor_hartid(n); - if (hartid < 0) { - pr_warn("Not valid hartid for node [%pOF] error =3D [%d]\n", + error =3D riscv_of_processor_hartid(n, &hartid); + if (error < 0) { + pr_warn("Not valid hartid for node [%pOF] error =3D [%lu]\n", n, hartid); - return hartid; + return error; } =20 cpuid =3D riscv_hartid_to_cpuid(hartid); if (cpuid < 0) { - pr_warn("Invalid cpuid for hartid [%d]\n", hartid); + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); return cpuid; } =20 @@ -140,7 +141,7 @@ static int __init riscv_timer_init_dt(struct device_nod= e *n) return -ENODEV; } =20 - pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", + pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", __func__, cpuid, hartid); error =3D clocksource_register_hz(&riscv_clocksource, riscv_timebase); if (error) { diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-i= ntc.c index b65bd8878d4f..499e5f81b3fe 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -95,10 +95,11 @@ static const struct irq_domain_ops riscv_intc_domain_op= s =3D { static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { - int rc, hartid; + int rc; + unsigned long hartid; =20 - hartid =3D riscv_of_parent_hartid(node); - if (hartid < 0) { + rc =3D riscv_of_parent_hartid(node, &hartid); + if (rc < 0) { pr_warn("unable to find hart id for %pOF\n", node); return 0; } diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index bb87e4c3b88e..4710d9741f36 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -317,7 +317,8 @@ static int __init plic_init(struct device_node *node, for (i =3D 0; i < nr_contexts; i++) { struct of_phandle_args parent; irq_hw_number_t hwirq; - int cpu, hartid; + int cpu; + unsigned long hartid; =20 if (of_irq_parse_one(node, i, &parent)) { pr_err("failed to parse parent for context %d.\n", i); @@ -341,8 +342,8 @@ static int __init plic_init(struct device_node *node, continue; } =20 - hartid =3D riscv_of_parent_hartid(parent.np); - if (hartid < 0) { + error =3D riscv_of_parent_hartid(parent.np, &hartid); + if (error < 0) { pr_warn("failed to parse hart ID for context %d.\n", i); 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Wed, 25 May 2022 08:11:40 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id q16-20020a170902eb9000b00161b50c3db4sm9383129plg.94.2022.05.25.08.11.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 May 2022 08:11:40 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH 5/5] riscv/efi_stub: Support for 64bit boot-hartid Date: Wed, 25 May 2022 20:41:06 +0530 Message-Id: <20220525151106.2176147-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220525151106.2176147-1-sunilvl@ventanamicro.com> References: <20220525151106.2176147-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The boot-hartid can be a 64bit value on RV64 platforms. Currently, the "boot-hartid" in DT is assumed to be 32bit only. This patch detects the size of the "boot-hartid" and uses 32bit or 64bit FDT reads appropriately. Signed-off-by: Sunil V L --- drivers/firmware/efi/libstub/riscv-stub.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/efi/libstub/riscv-stub.c b/drivers/firmware/e= fi/libstub/riscv-stub.c index 9e85e58d1f27..d748533f1329 100644 --- a/drivers/firmware/efi/libstub/riscv-stub.c +++ b/drivers/firmware/efi/libstub/riscv-stub.c @@ -29,7 +29,7 @@ static int get_boot_hartid_from_fdt(void) { const void *fdt; int chosen_node, len; - const fdt32_t *prop; + const void *prop; =20 fdt =3D get_efi_config_table(DEVICE_TREE_GUID); if (!fdt) @@ -40,10 +40,16 @@ static int get_boot_hartid_from_fdt(void) return -EINVAL; =20 prop =3D fdt_getprop((void *)fdt, chosen_node, "boot-hartid", &len); - if (!prop || len !=3D sizeof(u32)) + if (!prop) + return -EINVAL; + + if (len =3D=3D sizeof(u32)) + hartid =3D (unsigned long) fdt32_to_cpu(*(fdt32_t *)prop); + else if (len =3D=3D sizeof(u64)) + hartid =3D (unsigned long) fdt64_to_cpu(*(fdt64_t *)prop); + else return -EINVAL; =20 - hartid =3D fdt32_to_cpu(*prop); return 0; } =20 --=20 2.25.1