From nobody Thu May 7 16:17:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C0E5C433EF for ; Tue, 24 May 2022 21:20:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241893AbiEXVUC (ORCPT ); Tue, 24 May 2022 17:20:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235550AbiEXVT7 (ORCPT ); Tue, 24 May 2022 17:19:59 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E7EA56FB4 for ; Tue, 24 May 2022 14:19:58 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id y199so17507703pfb.9 for ; Tue, 24 May 2022 14:19:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=AOOnQwX8FlMZPsRjdPt59x3rx2ygNvknjVlpR0iASV4=; b=YrTSwufLEZ1P7/fW0b/k6bLAK/RaBs/rYT5zdNK+AgXQ3AfBxedshAwy/hCIaDeMum 63fAA5CXnCSlev0yz8w5zJhf+Gl71NBw+ln88+tJe9F2OdZrlckhk6isvq37z+mtIAoB GUUiprEZGCRYxZ3TKbhuCuaR+TCfnqGX+28hhCbYWCcA6wXWnx6tF0Ds0/yuAfu93c0U q9DKy/Dv2xD/oY1wOHTn8NdmF8uUp1br3r5riHE3BXs4JB+s8yMumemO0L0OoONBZGZk tiXTLgZUthwGvfGbljEKg/3YXIK/Tdn9WwXImLUgH03uoTJYhEk7NjuNRtYWoQCs8KrE rvgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=AOOnQwX8FlMZPsRjdPt59x3rx2ygNvknjVlpR0iASV4=; b=p4PADm7oXy4G7MkTFy9Gq/3HtommQgyg0C9RKUDevSLqEhquqejVd0WQfpxLdZ+lA0 hfcA0VLpw/ccJfZyg6wqONRN61t/426/rb1Vym8BOM8tQyZ5Qr8+xvMZSZ1YGB8Mba4+ Tpwha2s0Zbu+O9nzdL3IHFxRNZL7ntjGUfcjcwZAwZWrhHkuejRk4508xuVoFdedeYXN sEhEOhfUnpI/NRWyKVCq3NGRaYBWZkfCOJSM4xDi59XTuihFucliXeTi8md5qhuUgJ4p oPAtIE4BunQ4TjZR9aaFA716PaBTRE7oyhiLMHNnMJ+zR4lAQUBPP6epZ6lilHdJ6fC8 gqag== X-Gm-Message-State: AOAM5328gDwzhRmL8SzYvExNg3J5PtL6GCl6nKxk/tdIiKLRpTysHr3a ZCNDBEI7cSIbt8xNPn81Q8n47pX1ccdHsw== X-Google-Smtp-Source: ABdhPJxSAPU1ORTbLoGjyN5yxspHkTvKVWS0vgFiLp2ZZwtBNnGRSmXsVQw8Qg6e72inntA8VWn4fQ== X-Received: by 2002:a05:6a00:170c:b0:510:865f:bf34 with SMTP id h12-20020a056a00170c00b00510865fbf34mr30397811pfc.60.1653427197677; Tue, 24 May 2022 14:19:57 -0700 (PDT) Received: from daolu.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id a4-20020a62d404000000b0050dc7628181sm9833817pfh.91.2022.05.24.14.19.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 14:19:57 -0700 (PDT) From: Dao Lu To: linux-kernel@vger.kernel.org Cc: Dao Lu , Heiko Stuebner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Anup Patel , Randy Dunlap , Rob Herring , Alexandre Ghiti , Qinglin Pan , Tsukasa OI , Jisheng Zhang , linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE) Subject: [PATCH v2] arch/riscv: add Zihintpause support Date: Tue, 24 May 2022 14:19:50 -0700 Message-Id: <20220524211954.1936117-1-daolu@rivosinc.com> X-Mailer: git-send-email 2.36.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Implement support for the ZiHintPause extension. The PAUSE instruction is a HINT that indicates the current hart=E2=80=99s r= ate of instruction retirement should be temporarily reduced or paused. Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Dao Lu --- v1 -> v2: Remove the usage of static branch, use PAUSE if toolchain supports it arch/riscv/Makefile | 4 ++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/vdso/processor.h | 8 +++++++- arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 2 ++ 5 files changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 7d81102cffd4..900a8fda1a2d 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -56,6 +56,10 @@ riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-march-y)c toolchain-need-zicsr-zifencei :=3D $(call cc-option-yn, -march=3D$(riscv-m= arch-y)_zicsr_zifencei) riscv-march-$(toolchain-need-zicsr-zifencei) :=3D $(riscv-march-y)_zicsr_z= ifencei =20 +# Check if the toolchain supports Zihintpause extension +toolchain-supports-zihintpause :=3D $(call cc-option-yn, -march=3D$(riscv-= march-y)_zihintpause) +riscv-march-$(toolchain-supports-zihintpause) :=3D $(riscv-march-y)_zihint= pause + KBUILD_CFLAGS +=3D -march=3D$(subst fd,,$(riscv-march-y)) KBUILD_AFLAGS +=3D -march=3D$(riscv-march-y) =20 diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 0734e42f74f2..caa9ee5459b4 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -52,6 +52,7 @@ extern unsigned long elf_hwcap; */ enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF =3D RISCV_ISA_EXT_BASE, + RISCV_ISA_EXT_ZIHINTPAUSE, RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/a= sm/vdso/processor.h index 134388cbaaa1..4de911a25051 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -8,7 +8,13 @@ =20 static inline void cpu_relax(void) { -#ifdef __riscv_muldiv +#ifdef __riscv_zihintpause + /* + * Reduce instruction retirement. + * This assumes the PC changes. + */ + __asm__ __volatile__ ("pause"); +#elif __riscv_muldiv int dummy; /* In lieu of a halt instruction, induce a long-latency stall. */ __asm__ __volatile__ ("div %0, %0, zero" : "=3Dr" (dummy)); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ccb617791e56..89e563e9c4cc 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -88,6 +88,7 @@ int riscv_of_parent_hartid(struct device_node *node) */ static struct riscv_isa_ext_data isa_ext_arr[] =3D { __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b2d42d7f589..37ff06682ae6 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -25,6 +25,7 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __rea= d_mostly; __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); #endif =20 + /** * riscv_isa_extension_base() - Get base extension word * @@ -192,6 +193,7 @@ void __init riscv_fill_hwcap(void) set_bit(*ext - 'a', this_isa); } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); + SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); } #undef SET_ISA_EXT_MAP } --=20 2.36.0