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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id k24-20020a05600c1c9800b003974027722csm2703693wms.47.2022.05.24.08.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 08:28:08 -0700 (PDT) From: Alexandre Bailon To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, Michael Kao , Ben Tseng , Alexandre Bailon Subject: [PATCH v7 4/6] thermal: mediatek: Add thermal zone settings for mt8195 Date: Tue, 24 May 2022 17:25:51 +0200 Message-Id: <20220524152552.246193-5-abailon@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220524152552.246193-1-abailon@baylibre.com> References: <20220524152552.246193-1-abailon@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Michael Kao Add thermal zone settings for mt8195 Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon --- drivers/thermal/mediatek/soc_temp_lvts.c | 201 +++++++++++++++++++++-- 1 file changed, 187 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/mediatek/soc_temp_lvts.c b/drivers/thermal/med= iatek/soc_temp_lvts.c index 4b8c4c419f8e..c77c045d2599 100644 --- a/drivers/thermal/mediatek/soc_temp_lvts.c +++ b/drivers/thermal/mediatek/soc_temp_lvts.c @@ -49,6 +49,7 @@ =20 #define CLOCK_26MHZ_CYCLE_NS (38) #define BUS_ACCESS_US (2) +#define GOLDEN_TEMP_MAX (62) =20 #define FEATURE_DEVICE_AUTO_RCK (BIT(0)) #define FEATURE_CK26M_ACTIVE (BIT(1)) @@ -544,21 +545,10 @@ static int prepare_calibration_data(struct lvts_data = *lvts_data) if (!cal_data->count_rc) return -ENOMEM; =20 - if (ops->efuse_to_cal_data) + if (ops->efuse_to_cal_data && !cal_data->use_fake_efuse) ops->efuse_to_cal_data(lvts_data); - - cal_data->use_fake_efuse =3D 1; - if (cal_data->golden_temp !=3D 0) { - cal_data->use_fake_efuse =3D 0; - } else { - for (i =3D 0; i < lvts_data->num_sensor; i++) { - if (cal_data->count_r[i] !=3D 0 || - cal_data->count_rc[i] !=3D 0) { - cal_data->use_fake_efuse =3D 0; - break; - } - } - } + if (cal_data->golden_temp =3D=3D 0 || cal_data->golden_temp > GOLDEN_TEMP= _MAX) + cal_data->use_fake_efuse =3D 1; =20 if (cal_data->use_fake_efuse) { /* It means all efuse data are equal to 0 */ @@ -1233,11 +1223,194 @@ static const struct lvts_data mt8192_lvts_data =3D= { }, }; =20 +#define MT8195_NUM_LVTS (ARRAY_SIZE(mt8195_tc_settings)) + +enum mt8195_lvts_domain { + MT8195_AP_DOMAIN, + MT8195_MCU_DOMAIN, + MT8195_NUM_DOMAIN +}; + +enum mt8195_lvts_sensor_enum { + MT8195_TS1_0, + MT8195_TS1_1, + MT8195_TS2_0, + MT8195_TS2_1, + MT8195_TS3_0, + MT8195_TS3_1, + MT8195_TS3_2, + MT8195_TS3_3, + MT8195_TS4_0, + MT8195_TS4_1, + MT8195_TS5_0, + MT8195_TS5_1, + MT8195_TS6_0, + MT8195_TS6_1, + MT8195_TS6_2, + MT8195_TS7_0, + MT8195_TS7_1, + MT8195_NUM_TS +}; + +static void mt8195_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct sensor_cal_data *cal_data =3D &lvts_data->cal_data; + + cal_data->golden_temp =3D GET_CAL_DATA_BITMASK(0, 31, 24); + cal_data->count_r[MT8195_TS1_0] =3D GET_CAL_DATA_BITMASK(1, 23, 0); + cal_data->count_r[MT8195_TS1_1] =3D (GET_CAL_DATA_BITMASK(2, 15, 0) << 8)= + + GET_CAL_DATA_BITMASK(1, 31, 24); + cal_data->count_r[MT8195_TS2_0] =3D GET_CAL_DATA_BITMASK(3, 31, 8); + cal_data->count_r[MT8195_TS2_1] =3D GET_CAL_DATA_BITMASK(4, 23, 0); + cal_data->count_r[MT8195_TS3_0] =3D (GET_CAL_DATA_BITMASK(6, 7, 0) << 16)= + + GET_CAL_DATA_BITMASK(5, 31, 16); + cal_data->count_r[MT8195_TS3_1] =3D GET_CAL_DATA_BITMASK(6, 31, 8); + cal_data->count_r[MT8195_TS3_2] =3D GET_CAL_DATA_BITMASK(7, 23, 0); + cal_data->count_r[MT8195_TS3_3] =3D (GET_CAL_DATA_BITMASK(8, 15, 0) << 8)= + + GET_CAL_DATA_BITMASK(7, 31, 24); + cal_data->count_r[MT8195_TS4_0] =3D GET_CAL_DATA_BITMASK(9, 31, 8); + cal_data->count_r[MT8195_TS4_1] =3D GET_CAL_DATA_BITMASK(10, 23, 0); + cal_data->count_r[MT8195_TS5_0] =3D (GET_CAL_DATA_BITMASK(12, 7, 0) << 16= ) + + GET_CAL_DATA_BITMASK(11, 31, 16); + cal_data->count_r[MT8195_TS5_1] =3D GET_CAL_DATA_BITMASK(12, 31, 8); + cal_data->count_r[MT8195_TS6_0] =3D (GET_CAL_DATA_BITMASK(14, 15, 0) << 8= ) + + GET_CAL_DATA_BITMASK(13, 31, 24); + cal_data->count_r[MT8195_TS6_1] =3D (GET_CAL_DATA_BITMASK(15, 7, 0) << 16= ) + + GET_CAL_DATA_BITMASK(14, 31, 16); + cal_data->count_r[MT8195_TS6_2] =3D GET_CAL_DATA_BITMASK(15, 31, 8); + cal_data->count_r[MT8195_TS7_0] =3D (GET_CAL_DATA_BITMASK(17, 15, 0) << 8= ) + + GET_CAL_DATA_BITMASK(16, 31, 24); + cal_data->count_r[MT8195_TS7_1] =3D (GET_CAL_DATA_BITMASK(18, 7, 0) << 16= ) + + GET_CAL_DATA_BITMASK(17, 31, 16); + cal_data->count_rc[MT8195_TS1_0] =3D (GET_CAL_DATA_BITMASK(3, 7, 0) << 16= ) + + GET_CAL_DATA_BITMASK(2, 31, 16); + cal_data->count_rc[MT8195_TS2_0] =3D (GET_CAL_DATA_BITMASK(5, 15, 0) << 8= ) + + GET_CAL_DATA_BITMASK(4, 31, 24); + cal_data->count_rc[MT8195_TS3_0] =3D (GET_CAL_DATA_BITMASK(9, 7, 0) << 16= ) + + GET_CAL_DATA_BITMASK(8, 31, 16); + cal_data->count_rc[MT8195_TS4_0] =3D (GET_CAL_DATA_BITMASK(11, 15, 0) << = 8) + + GET_CAL_DATA_BITMASK(10, 31, 24); + cal_data->count_rc[MT8195_TS5_0] =3D GET_CAL_DATA_BITMASK(13, 23, 0); + cal_data->count_rc[MT8195_TS6_0] =3D GET_CAL_DATA_BITMASK(16, 23, 0); + cal_data->count_rc[MT8195_TS7_0] =3D GET_CAL_DATA_BITMASK(18, 31, 8); +} + +static const struct tc_settings mt8195_tc_settings[] =3D { + [0] =3D { + .domain_index =3D MT8195_MCU_DOMAIN, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS1_0, MT8195_TS1_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(3), + }, + [1] =3D { + .domain_index =3D MT8195_MCU_DOMAIN, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS2_0, MT8195_TS2_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(4), + }, + [2] =3D { + .domain_index =3D MT8195_MCU_DOMAIN, + .addr_offset =3D 0x200, + .num_sensor =3D 4, + .sensor_map =3D {MT8195_TS3_0, MT8195_TS3_1, MT8195_TS3_2, MT8195_TS3_3}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(5), + }, + [3] =3D { + .domain_index =3D MT8195_AP_DOMAIN, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS4_0, MT8195_TS4_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(3), + }, + [4] =3D { + .domain_index =3D MT8195_AP_DOMAIN, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS5_0, MT8195_TS5_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(4), + }, + [5] =3D { + .domain_index =3D MT8195_AP_DOMAIN, + .addr_offset =3D 0x200, + .num_sensor =3D 3, + .sensor_map =3D {MT8195_TS6_0, MT8195_TS6_1, MT8195_TS6_2}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(5), + }, + [6] =3D { + .domain_index =3D MT8195_AP_DOMAIN, + .addr_offset =3D 0x300, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS7_0, MT8195_TS7_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(6), + } +}; + +static const struct lvts_data mt8195_lvts_data =3D { + .num_domain =3D MT8195_NUM_DOMAIN, + .num_tc =3D MT8195_NUM_LVTS, + .tc =3D mt8195_tc_settings, + .num_sensor =3D MT8195_NUM_TS, + .ops =3D { + .efuse_to_cal_data =3D mt8195_efuse_to_cal_data, + .device_enable_and_init =3D device_enable_and_init_v4, + .device_enable_auto_rck =3D device_enable_auto_rck_v4, + .device_read_count_rc_n =3D device_read_count_rc_n_v4, + .set_cal_data =3D set_calibration_data_v4, + .init_controller =3D init_controller_v4, + }, + .feature_bitmap =3D FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr =3D 22, + .num_efuse_block =3D 2, + .cal_data =3D { + .default_golden_temp =3D 50, + .default_count_r =3D 35000, + .default_count_rc =3D 2750, + }, + .coeff =3D { + .a =3D -250460, + .b =3D 250460, + }, +}; + static const struct of_device_id lvts_of_match[] =3D { { .compatible =3D "mediatek,mt8192-lvts", .data =3D (void *)&mt8192_lvts_data, }, + { + .compatible =3D "mediatek,mt8195-lvts", + .data =3D (void *)&mt8195_lvts_data, + }, { }, }; --=20 2.35.1