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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id k24-20020a05600c1c9800b003974027722csm2703693wms.47.2022.05.24.08.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 08:28:03 -0700 (PDT) From: Alexandre Bailon To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, Michael Kao , Ben Tseng Subject: [PATCH v7 1/6] thermal: mediatek: Relocate driver to mediatek folder Date: Tue, 24 May 2022 17:25:48 +0200 Message-Id: <20220524152552.246193-2-abailon@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220524152552.246193-1-abailon@baylibre.com> References: <20220524152552.246193-1-abailon@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Michael Kao Add Mediatek proprietary folder to upstream more thermal zone and cooler drivers. Relocate the original thermal controller driver to it and rename as soc_temp.c to show its purpose more clearly. Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Reviewed-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno --- drivers/thermal/Kconfig | 14 ++++------- drivers/thermal/Makefile | 2 +- drivers/thermal/mediatek/Kconfig | 23 +++++++++++++++++++ drivers/thermal/mediatek/Makefile | 1 + .../{mtk_thermal.c =3D> mediatek/soc_temp.c} | 0 5 files changed, 29 insertions(+), 11 deletions(-) create mode 100644 drivers/thermal/mediatek/Kconfig create mode 100644 drivers/thermal/mediatek/Makefile rename drivers/thermal/{mtk_thermal.c =3D> mediatek/soc_temp.c} (100%) diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index e37691e0bf20..8669d7278055 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -410,16 +410,10 @@ config DA9062_THERMAL zone. Compatible with the DA9062 and DA9061 PMICs. =20 -config MTK_THERMAL - tristate "Temperature sensor driver for mediatek SoCs" - depends on ARCH_MEDIATEK || COMPILE_TEST - depends on HAS_IOMEM - depends on NVMEM || NVMEM=3Dn - depends on RESET_CONTROLLER - default y - help - Enable this option if you want to have support for thermal management - controller present in Mediatek SoCs +menu "Mediatek thermal drivers" +depends on ARCH_MEDIATEK || COMPILE_TEST +source "drivers/thermal/mediatek/Kconfig" +endmenu =20 config AMLOGIC_THERMAL tristate "Amlogic Thermal Support" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index f0c36a1530d5..9ade39bdb525 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -55,7 +55,7 @@ obj-y +=3D st/ obj-$(CONFIG_QCOM_TSENS) +=3D qcom/ obj-y +=3D tegra/ obj-$(CONFIG_HISI_THERMAL) +=3D hisi_thermal.o -obj-$(CONFIG_MTK_THERMAL) +=3D mtk_thermal.o +obj-$(CONFIG_MTK_THERMAL) +=3D mediatek/ obj-$(CONFIG_GENERIC_ADC_THERMAL) +=3D thermal-generic-adc.o obj-$(CONFIG_UNIPHIER_THERMAL) +=3D uniphier_thermal.o obj-$(CONFIG_AMLOGIC_THERMAL) +=3D amlogic_thermal.o diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kc= onfig new file mode 100644 index 000000000000..592c849b9fed --- /dev/null +++ b/drivers/thermal/mediatek/Kconfig @@ -0,0 +1,23 @@ +config MTK_THERMAL + tristate "MediaTek thermal drivers" + depends on THERMAL_OF + help + This is the option for MediaTek thermal software + solutions. Please enable corresponding options to + get temperature information from thermal sensors or + turn on throttle mechaisms for thermal mitigation. + +if MTK_THERMAL + +config MTK_SOC_THERMAL + tristate "Temperature sensor driver for MediaTek SoCs" + depends on HAS_IOMEM + depends on NVMEM + depends on RESET_CONTROLLER + help + Enable this option if you want to get SoC temperature + information for MediaTek platforms. This driver + configures thermal controllers to collect temperature + via AUXADC interface. + +endif diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/M= akefile new file mode 100644 index 000000000000..f75313ddce5e --- /dev/null +++ b/drivers/thermal/mediatek/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MTK_SOC_THERMAL) +=3D soc_temp.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mediatek/soc_t= emp.c similarity index 100% rename from drivers/thermal/mtk_thermal.c rename to drivers/thermal/mediatek/soc_temp.c --=20 2.35.1 From nobody Sat Sep 21 23:31:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C2B3C433F5 for ; Tue, 24 May 2022 15:28:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239038AbiEXP2s (ORCPT ); Tue, 24 May 2022 11:28:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238935AbiEXP2T (ORCPT ); Tue, 24 May 2022 11:28:19 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D206F62211 for ; Tue, 24 May 2022 08:28:06 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id t13so7044212wrg.9 for ; Tue, 24 May 2022 08:28:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K2Kq4AjX60Auvs3EuDkJuXpELchmlwLWXQGbXPVKMFg=; b=MaqBpO0pzw2Nv86cZdqlL2ALSDFOV1BK9LgFUwh35kTr5l0ZencTSTkfJUfpzHwq4A LZNnnNo4Zc7/yvDJ1AA+qsJqoF8vsxLvFmggzUmZ3J5jYs56Z/bj1NfI0oMUTFC/IcMw A9a6feB5qVngeQMPrdhkk5bM3jqtrnhSwpr+EGbm2w0cPK8Crl381CE7ZLc6ma6SjgqY Vh5VpS57UfOIivGNOEOPheHHd29CzvCa6rUM/gr/Cw8fXNJq1J/qr4O9AXlq0bnRlruP mADsDpqLi9PDK5UBvn8ADQNFzFPEWEEP+h70O9ijS0SmGSyYgB8cwcUf4KPSnYs9rKFv ge3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K2Kq4AjX60Auvs3EuDkJuXpELchmlwLWXQGbXPVKMFg=; b=QAs8IvcbNaSesPJ//qahIuLBjcUfdljNanSYB6qKodeO94QrwmQvSvd7UFgMY1RWDf zLRXIFMIclkrZdwyjYqG8vE14YX3UGnuzoWF57RdwZ6EmEERIMWYuqQ34D810rWirjL5 +wt9gRHf+Rr/uz/jYcyzwLgXIJE3I17hoa3JyOanOJgwMKmbyL0zlKnnnqyUBtBdBNN9 31DwHxxbNrqCnpgNpNXtW3Jz+Ab7pz8VO9jPTJmbGP3X2r/ZDX0q0xHGaDXGwCPwpiPy xpyeA6mHf+c3JkUiJY85J/ylntCzmEyqvFnjrRM0Bj9f1MPvL/2VRxwVlkQcXScVCE1u pzdw== X-Gm-Message-State: AOAM533YtS9l1VNhhQkjaZfNcw0G6MrwzpWGZxyyZgGtfCBvdmrq8P+H umIkZ0diHu/pUH4DubEQ3VHrRQ== X-Google-Smtp-Source: ABdhPJzhL25As+aiDUdp92860cR8SXhTp4IGDzPkkcaizWyOIZvd4NfNBonbrx5zCl7T9cfzyR+7Mw== X-Received: by 2002:a05:6000:1541:b0:20f:e8f0:be4e with SMTP id 1-20020a056000154100b0020fe8f0be4emr6471819wry.658.1653406085387; Tue, 24 May 2022 08:28:05 -0700 (PDT) Received: from xps-9300.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id k24-20020a05600c1c9800b003974027722csm2703693wms.47.2022.05.24.08.28.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 08:28:05 -0700 (PDT) From: Alexandre Bailon To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, Alexandre Bailon Subject: [PATCH v7 2/6] dt-bindings: thermal: Add binding document for LVTS thermal controllers Date: Tue, 24 May 2022 17:25:49 +0200 Message-Id: <20220524152552.246193-3-abailon@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220524152552.246193-1-abailon@baylibre.com> References: <20220524152552.246193-1-abailon@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds binding document for mt8192 and mt8195 thermal controllers. Signed-off-by: Alexandre Bailon --- .../thermal/mediatek,mt8192-lvts.yaml | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,mt81= 92-lvts.yaml diff --git a/Documentation/devicetree/bindings/thermal/mediatek,mt8192-lvts= .yaml b/Documentation/devicetree/bindings/thermal/mediatek,mt8192-lvts.yaml new file mode 100644 index 000000000000..914c877d1f2f --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek,mt8192-lvts.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/mediatek,mt8192-lvts.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC LVTS thermal controller + +maintainers: + - Yu-Chia Chang + - Ben Tseng + +allOf: + - $ref: thermal-sensor.yaml# + - $ref: /nvmem/nvmem-consumer.yaml# + +properties: + compatible: + enum: + - mediatek,mt8192-lvts + - mediatek,mt8195-lvts + + reg: + minItems: 2 + maxItems: 4 + + interrupts: + maxItems: 2 + + clocks: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + + nvmem-cells: + maxItems: 2 + description: Calibration data for thermal sensors + + nvmem-cell-names: + items: + - const: e_data1 + - const: e_data2 + + resets: + $ref: /schemas/types.yaml#/definitions/phandle-array + + +required: + - '#thermal-sensor-cells' + - compatible + - reg + - interrupts + - clocks + - nvmem-cells + - nvmem-cell-names + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + lvts: lvts@1100b000 { + compatible =3D "mediatek,mt8195-lvts"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x1100b000 0 0x1000>, + <0 0x11278000 0 0x1000>; + interrupts =3D , + ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>, + <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells =3D <&lvts_e_data1 &lvts_e_data2>; + nvmem-cell-names =3D "e_data1","e_data2"; + }; +... --=20 2.35.1 From nobody Sat Sep 21 23:31:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E864DC433F5 for ; Tue, 24 May 2022 15:28:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238911AbiEXP23 (ORCPT ); Tue, 24 May 2022 11:28:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238947AbiEXP2U (ORCPT ); Tue, 24 May 2022 11:28:20 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42E61663FB for ; Tue, 24 May 2022 08:28:09 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id x12so1975272wrg.2 for ; Tue, 24 May 2022 08:28:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d2Ckj9H7tmTr8N1cGDHMTwsQbrYT+Ulqt7AMgC9pLHg=; b=5PFwfEFvkK8NshoD7enCcGJ6ksvref83KgfOBcnYx4pLndsznSjsi1pQlcDoFGdy+Y C2DNjj4ghazbbDaG4KEJyu2uie8v7pRkRQkmcZvwH/UBOO+WgbLyY4CacrsPqmPy00n/ PmC/cmSja++CuAvgg8eUC7AC3iZTMKbqYeov9mk9R3Nd2igi231E38P8BFlHz5sNSOKY qKfaDlzPVc+ONMkcWe7Ds7Wto7pICHzJZSwefn2tRvuPcTJU1b11BUFoGWSTEesyGms8 VFj6wjnylSH2CugMdBX1IxYdeCyBdp+dWpL1Au5cRKRXhdTOx/Q16G3E1y3mhNjJ9Yeq lUXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d2Ckj9H7tmTr8N1cGDHMTwsQbrYT+Ulqt7AMgC9pLHg=; b=k8HFH0o8YTtFOTtpriSzfTe8W2YFSQjql37Nr5PSx+l1HU6t2mZ/9DRU95g4rJASeQ bIaJNY7ovsZlcE+3rDsIHKHNzV1NkfX4ZEAqHHq3PT79mVyhmP8Bh+SstUrz5pxYv0Y4 66dw4cg07e+Qx3RcgloNBEIJWjzRvS3HLhFfoiRs4YFJb+O785TuXYhpwrpTWK49/+JZ txiUgJPnCHCZe2wCEO1AWpiNFEmPHAyL4rb+gHUMq8xuTidFZbs87IILCogkpkTem0UQ IxfEDId22uvd7ZKZeRUrFZYJYp/CeN9eyOhf+hnvv8nKG7T4thfj79rDvxvOnLi76S6g w+8A== X-Gm-Message-State: AOAM533q/jjFdpxNToej+YOl2GAPUPTu9M4a6Zmbj1ftDoTBffgGY1NT U0JSupj7kk2ldn0cnOqY3U7VgTA+PzSSmpm3ZDA= X-Google-Smtp-Source: ABdhPJxDDCCTLeb7hhxNQP7dQpt0ksQi9Tw8+rvdWyLPrrpp0uFnhRyEbiEMUUcHlPlR+dpLUWXDQQ== X-Received: by 2002:adf:fc07:0:b0:20d:7cb:b856 with SMTP id i7-20020adffc07000000b0020d07cbb856mr24431532wrr.551.1653406087402; Tue, 24 May 2022 08:28:07 -0700 (PDT) Received: from xps-9300.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id k24-20020a05600c1c9800b003974027722csm2703693wms.47.2022.05.24.08.28.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 08:28:06 -0700 (PDT) From: Alexandre Bailon To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, Michael Kao , Yu-Chia Chang , Ben Tseng , Alexandre Bailon Subject: [PATCH v7 3/6] thermal: mediatek: Add LVTS drivers for SoC theraml zones Date: Tue, 24 May 2022 17:25:50 +0200 Message-Id: <20220524152552.246193-4-abailon@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220524152552.246193-1-abailon@baylibre.com> References: <20220524152552.246193-1-abailon@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Michael Kao Add a LVTS (Low voltage thermal sensor) driver to report junction temperatures in Mediatek SoC and register the maximum temperature of sensors and each sensor as a thermal zone. Signed-off-by: Yu-Chia Chang Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon --- drivers/thermal/mediatek/Kconfig | 10 + drivers/thermal/mediatek/Makefile | 1 + drivers/thermal/mediatek/soc_temp.c | 2 +- drivers/thermal/mediatek/soc_temp_lvts.c | 1261 ++++++++++++++++++++++ drivers/thermal/mediatek/soc_temp_lvts.h | 304 ++++++ 5 files changed, 1577 insertions(+), 1 deletion(-) create mode 100644 drivers/thermal/mediatek/soc_temp_lvts.c create mode 100644 drivers/thermal/mediatek/soc_temp_lvts.h diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kc= onfig index 592c849b9fed..4839aefeacb3 100644 --- a/drivers/thermal/mediatek/Kconfig +++ b/drivers/thermal/mediatek/Kconfig @@ -20,4 +20,14 @@ config MTK_SOC_THERMAL configures thermal controllers to collect temperature via AUXADC interface. =20 +config MTK_SOC_THERMAL_LVTS + tristate "LVTS (Low voltage thermal sensor) driver for Mediatek So= Cs" + depends on HAS_IOMEM + depends on NVMEM + depends on RESET_TI_SYSCON + help + Enable this option if you want to get SoC temperature + information for MediaTek platforms. This driver + configures LVTS thermal controllers to collect temperatures + via Analog Serial Interface(ASIF). endif diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/M= akefile index f75313ddce5e..16ce166e5916 100644 --- a/drivers/thermal/mediatek/Makefile +++ b/drivers/thermal/mediatek/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_MTK_SOC_THERMAL) +=3D soc_temp.o +obj-$(CONFIG_MTK_SOC_THERMAL_LVTS) +=3D soc_temp_lvts.o diff --git a/drivers/thermal/mediatek/soc_temp.c b/drivers/thermal/mediatek= /soc_temp.c index 79d592f3f60d..4ed78bbadd62 100644 --- a/drivers/thermal/mediatek/soc_temp.c +++ b/drivers/thermal/mediatek/soc_temp.c @@ -23,7 +23,7 @@ #include #include =20 -#include "thermal_hwmon.h" +#include "../thermal_hwmon.h" =20 /* AUXADC Registers */ #define AUXADC_CON1_SET_V 0x008 diff --git a/drivers/thermal/mediatek/soc_temp_lvts.c b/drivers/thermal/med= iatek/soc_temp_lvts.c new file mode 100644 index 000000000000..4b8c4c419f8e --- /dev/null +++ b/drivers/thermal/mediatek/soc_temp_lvts.c @@ -0,0 +1,1261 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "soc_temp_lvts.h" + +#define STOP_COUNTING_V4 (DEVICE_WRITE | RG_TSFM_CTRL_0 << 8 | 0x00) +#define SET_RG_TSFM_LPDLY_V4 (DEVICE_WRITE | RG_TSFM_CTRL_4 << 8 | 0xA6) +#define SET_COUNTING_WINDOW_20US1_V4 (DEVICE_WRITE | RG_TSFM_CTRL_2 << 8 |= 0x00) +#define SET_COUNTING_WINDOW_20US2_V4 (DEVICE_WRITE | RG_TSFM_CTRL_1 << 8 |= 0x20) +#define TSV2F_CHOP_CKSEL_AND_TSV2F_EN_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_2 <= < 8 | 0x84) +#define TSBG_DEM_CKSEL_X_TSBG_CHOP_EN_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_4 <= < 8 | 0x7C) +#define SET_TS_RSV_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_1 << 8 | 0x8D) +#define SET_TS_EN_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 | 0xF4) +#define TOGGLE_RG_TSV2F_VCO_RST1_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 |= 0xFC) +#define TOGGLE_RG_TSV2F_VCO_RST2_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 |= 0xF4) + +#define SET_LVTS_AUTO_RCK_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_6 << 8 | 0x01) +#define SELECT_SENSOR_RCK_V4(id) (DEVICE_WRITE | RG_TSV2F_CTRL_5 << 8 | (i= d)) +#define SET_DEVICE_SINGLE_MODE_V4 (DEVICE_WRITE | RG_TSFM_CTRL_3 << 8 | 0x= 78) +#define KICK_OFF_RCK_COUNTING_V4 (DEVICE_WRITE | RG_TSFM_CTRL_0 << 8 | 0x0= 2) +#define SET_SENSOR_NO_RCK_V4 (DEVICE_WRITE | RG_TSV2F_CTRL_5 << 8 | 0x10) +#define SET_DEVICE_LOW_POWER_SINGLE_MODE_V4 (DEVICE_WRITE | RG_TSFM_CTRL_3= << 8 | 0xB8) + +#define ENABLE_FEATURE(feature) (lvts_data->feature_bitmap |=3D (feature)) +#define DISABLE_FEATURE(feature) (lvts_data->feature_bitmap &=3D (~(featur= e))) +#define IS_ENABLE(feature) (lvts_data->feature_bitmap & (feature)) + +#define DISABLE_THERMAL_HW_REBOOT (-274000) + +#define CLOCK_26MHZ_CYCLE_NS (38) +#define BUS_ACCESS_US (2) + +#define FEATURE_DEVICE_AUTO_RCK (BIT(0)) +#define FEATURE_CK26M_ACTIVE (BIT(1)) +#define CK26M_ACTIVE (((lvts_data->feature_bitmap & FEATURE_CK26M_ACTIVE= ) \ + ? 1 : 0) << 30) +#define GET_BASE_ADDR(tc_id) \ + (lvts_data->domain[lvts_data->tc[tc_id].domain_index].base \ + + lvts_data->tc[tc_id].addr_offset) + +#define SET_TC_SPEED_IN_US(pu, gd, fd, sd) \ + { \ + .period_unit =3D (((pu) * 1000) / (256 * CLOCK_26MHZ_CYCLE_NS)), \ + .group_interval_delay =3D ((gd) / (pu)), \ + .filter_interval_delay =3D ((fd) / (pu)), \ + .sensor_interval_delay =3D ((sd) / (pu)), \ + } + +#define GET_CAL_DATA_BITMASK(index, h, l) \ + (((index) < lvts_data->num_efuse_addr) \ + ? ((lvts_data->efuse[(index)] & GENMASK(h, l)) >> l) \ + : 0) + +#define GET_CAL_DATA_BIT(index, bit) \ + (((index) < lvts_data->num_efuse_addr) \ + ? ((lvts_data->efuse[index] & BIT(bit)) >> (bit)) \ + : 0) + +#define GET_TC_SENSOR_NUM(tc_id) \ + (lvts_data->tc[tc_id].num_sensor) + +#define ONE_SAMPLE (lvts_data->counting_window_us + 2 * BUS_ACCESS_US) + +#define NUM_OF_SAMPLE(tc_id) \ + ((lvts_data->tc[tc_id].hw_filter < LVTS_FILTER_2) ? 1 : \ + ((lvts_data->tc[tc_id].hw_filter > LVTS_FILTER_16_OF_18) ? 1 : \ + ((lvts_data->tc[tc_id].hw_filter =3D=3D LVTS_FILTER_16_OF_18) ? 18 :\ + ((lvts_data->tc[tc_id].hw_filter =3D=3D LVTS_FILTER_8_OF_10) ? 10 : \ + (lvts_data->tc[tc_id].hw_filter * 2))))) + +#define PERIOD_UNIT_US(tc_id) \ + ((lvts_data->tc[tc_id].tc_speed.period_unit * 256 * \ + CLOCK_26MHZ_CYCLE_NS) / 1000) +#define FILTER_INT_US(tc_id) \ + (lvts_data->tc[tc_id].tc_speed.filter_interval_delay \ + * PERIOD_UNIT_US(tc_id)) +#define SENSOR_INT_US(tc_id) \ + (lvts_data->tc[tc_id].tc_speed.sensor_interval_delay \ + * PERIOD_UNIT_US(tc_id)) +#define GROUP_INT_US(tc_id) \ + (lvts_data->tc[tc_id].tc_speed.group_interval_delay \ + * PERIOD_UNIT_US(tc_id)) + +#define SENSOR_LATENCY_US(tc_id) \ + ((NUM_OF_SAMPLE(tc_id) - 1) * FILTER_INT_US(tc_id) \ + + NUM_OF_SAMPLE(tc_id) * ONE_SAMPLE) + +#define GROUP_LATENCY_US(tc_id) \ + (GET_TC_SENSOR_NUM(tc_id) * SENSOR_LATENCY_US(tc_id) \ + + (GET_TC_SENSOR_NUM(tc_id) - 1) * SENSOR_INT_US(tc_id) \ + + GROUP_INT_US(tc_id)) + +static int lvts_raw_to_temp(struct formula_coeff *co, unsigned int msr_raw) +{ + /* This function returns degree mC */ + + int temp; + + temp =3D (co->a * ((unsigned long long)msr_raw)) >> 14; + temp =3D temp + co->golden_temp * 500 + co->b; + + return temp; +} + +static unsigned int lvts_temp_to_raw(struct formula_coeff *co, int temp) +{ + unsigned int msr_raw; + + msr_raw =3D div_s64((s64)((co->golden_temp * 500 + co->b - temp)) << 14, + (-1 * co->a)); + + return msr_raw; +} + +static int soc_temp_lvts_read_temp(void *data, int *temperature) +{ + struct soc_temp_tz *lvts_tz =3D (struct soc_temp_tz *)data; + struct lvts_data *lvts_data =3D lvts_tz->lvts_data; + unsigned int msr_raw; + + msr_raw =3D readl(lvts_data->reg[lvts_tz->id]) & MRS_RAW_MASK; + if (msr_raw =3D=3D 0) + return -EINVAL; + + *temperature =3D lvts_raw_to_temp(&lvts_data->coeff, msr_raw); + + return 0; +} + +static const struct thermal_zone_of_device_ops soc_temp_lvts_ops =3D { + .get_temp =3D soc_temp_lvts_read_temp, +}; + +static void lvts_write_device(struct lvts_data *lvts_data, unsigned int da= ta, + int tc_id) +{ + void __iomem *base; + + base =3D GET_BASE_ADDR(tc_id); + + writel(data, LVTS_CONFIG_0 + base); + + usleep_range(5, 15); +} + +static unsigned int lvts_read_device(struct lvts_data *lvts_data, + unsigned int reg_idx, int tc_id) +{ + struct device *dev =3D lvts_data->dev; + void __iomem *base; + unsigned int data; + int ret; + + base =3D GET_BASE_ADDR(tc_id); + writel(READ_DEVICE_REG(reg_idx), LVTS_CONFIG_0 + base); + + ret =3D readl_poll_timeout(LVTS_CONFIG_0 + base, data, + !(data & DEVICE_ACCESS_STARTUS), + 2, 200); + if (ret) + dev_err(dev, + "Error: LVTS %d DEVICE_ACCESS_START didn't ready\n", tc_id); + + data =3D readl(LVTSRDATA0_0 + base); + + return data; +} + +static void wait_all_tc_sensing_point_idle(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + unsigned int mask, error_code, is_error; + void __iomem *base; + int i, cnt, ret; + + mask =3D BIT(10) | BIT(7) | BIT(0); + + for (cnt =3D 0; cnt < 2; cnt++) { + is_error =3D 0; + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(i); + ret =3D readl_poll_timeout(LVTSMSRCTL1_0 + base, error_code, + !(error_code & mask), 2, 200); + /* + * Error code + * 000: IDLE + * 001: Write transaction + * 010: Waiting for read after Write + * 011: Disable Continue fetching on Device + * 100: Read transaction + * 101: Set Device special Register for Voltage threshold + * 111: Set TSMCU number for Fetch + */ + error_code =3D ((error_code & BIT(10)) >> 8) + + ((error_code & BIT(7)) >> 6) + + (error_code & BIT(0)); + + if (ret) + dev_err(dev, + "Error LVTS %d sensing points aren't idle, error_code %d\n", + i, error_code); + + if (error_code !=3D 0) + is_error =3D 1; + } + + if (is_error =3D=3D 0) + break; + } +} + +static void lvts_reset(struct lvts_data *lvts_data) +{ + int i; + + for (i =3D 0; i < lvts_data->num_domain; i++) { + if (lvts_data->domain[i].reset) + reset_control_assert(lvts_data->domain[i].reset); + + if (lvts_data->domain[i].reset) + reset_control_deassert(lvts_data->domain[i].reset); + } +} + +static void device_identification(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + unsigned int i, data; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(i); + + writel(ENABLE_LVTS_CTRL_CLK, LVTSCLKEN_0 + base); + + lvts_write_device(lvts_data, RESET_ALL_DEVICES, i); + + lvts_write_device(lvts_data, READ_BACK_DEVICE_ID, i); + + /* Check LVTS device ID */ + data =3D (readl(LVTS_ID_0 + base) & GENMASK(7, 0)); + if (data !=3D (0x81 + i)) + dev_err(dev, "LVTS_TC_%d, Device ID should be 0x%x, but 0x%x\n", + i, (0x81 + i), data); + } +} + +static void disable_all_sensing_points(struct lvts_data *lvts_data) +{ + unsigned int i; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(i); + writel(DISABLE_SENSING_POINT, LVTSMONCTL0_0 + base); + } +} + +static void enable_all_sensing_points(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + const struct tc_settings *tc =3D lvts_data->tc; + unsigned int i, num; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(i); + num =3D tc[i].num_sensor; + + if (num > ALL_SENSING_POINTS) { + dev_err(dev, + "%s, LVTS%d, illegal number of sensors: %d\n", + __func__, i, tc[i].num_sensor); + continue; + } + + writel(ENABLE_SENSING_POINT(num), LVTSMONCTL0_0 + base); + } +} + +static void set_polling_speed(struct lvts_data *lvts_data, int tc_id) +{ + struct device *dev =3D lvts_data->dev; + const struct tc_settings *tc =3D lvts_data->tc; + unsigned int lvts_mon_ctl_1, lvts_mon_ctl_2; + void __iomem *base; + + base =3D GET_BASE_ADDR(tc_id); + + lvts_mon_ctl_1 =3D ((tc[tc_id].tc_speed.group_interval_delay << 20) & GEN= MASK(29, 20)) | + (tc[tc_id].tc_speed.period_unit & GENMASK(9, 0)); + lvts_mon_ctl_2 =3D ((tc[tc_id].tc_speed.filter_interval_delay << 16) & GE= NMASK(25, 16)) | + (tc[tc_id].tc_speed.sensor_interval_delay & GENMASK(9, 0)); + /* + * Clock source of LVTS thermal controller is 26MHz. + * Period unit is a base for all interval delays + * All interval delays must multiply it to convert a setting to time. + * Filter interval delay is a delay between two samples of the same sensor + * Sensor interval delay is a delay between two samples of differnet sens= ors + * Group interval delay is a delay between different rounds. + * For example: + * If Period unit =3D C, filter delay =3D 1, sensor delay =3D 2, grou= p delay =3D 1, + * and two sensors, TS1 and TS2, are in a LVTS thermal controller + * and then + * Period unit =3D C * 1/26M * 256 =3D 12 * 38.46ns * 256 =3D 118.149= us + * Filter interval delay =3D 1 * Period unit =3D 118.149us + * Sensor interval delay =3D 2 * Period unit =3D 236.298us + * Group interval delay =3D 1 * Period unit =3D 118.149us + * + * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... + * <--> Filter interval delay + * <--> Sensor interval delay + * <--> Group interval delay + */ + writel(lvts_mon_ctl_1, LVTSMONCTL1_0 + base); + writel(lvts_mon_ctl_2, LVTSMONCTL2_0 + base); + + dev_info(dev, "%s %d, LVTSMONCTL1_0=3D 0x%x,LVTSMONCTL2_0=3D 0x%x\n", + __func__, tc_id, readl(LVTSMONCTL1_0 + base), + readl(LVTSMONCTL2_0 + base)); +} + +static void set_hw_filter(struct lvts_data *lvts_data, int tc_id) +{ + struct device *dev =3D lvts_data->dev; + const struct tc_settings *tc =3D lvts_data->tc; + unsigned int option; + void __iomem *base; + + base =3D GET_BASE_ADDR(tc_id); + option =3D tc[tc_id].hw_filter & 0x7; + /* + * hw filter + * 000: Get one sample + * 001: Get 2 samples and average them + * 010: Get 4 samples, drop max and min, then average the rest of 2 sampl= es + * 011: Get 6 samples, drop max and min, then average the rest of 4 sampl= es + * 100: Get 10 samples, drop max and min, then average the rest of 8 samp= les + * 101: Get 18 samples, drop max and min, then average the rest of 16 sam= ples + */ + option =3D (option << 9) | (option << 6) | (option << 3) | option; + + writel(option, LVTSMSRCTL0_0 + base); + dev_info(dev, "%s %d, LVTSMSRCTL0_0=3D 0x%x\n", + __func__, tc_id, readl(LVTSMSRCTL0_0 + base)); +} + +static int get_dominator_index(struct lvts_data *lvts_data, int tc_id) +{ + struct device *dev =3D lvts_data->dev; + const struct tc_settings *tc =3D lvts_data->tc; + int d_index; + + if (tc[tc_id].dominator_sensing_point =3D=3D ALL_SENSING_POINTS) { + d_index =3D ALL_SENSING_POINTS; + } else if (tc[tc_id].dominator_sensing_point < + tc[tc_id].num_sensor){ + d_index =3D tc[tc_id].dominator_sensing_point; + } else { + dev_err(dev, + "Error: LVTS%d, dominator_sensing_point=3D %d should smaller than num_s= ensor=3D %d\n", + tc_id, tc[tc_id].dominator_sensing_point, + tc[tc_id].num_sensor); + + dev_err(dev, "Use the sensing point 0 as the dominated sensor\n"); + d_index =3D SENSING_POINT0; + } + + return d_index; +} + +static void disable_hw_reboot_interrupt(struct lvts_data *lvts_data, int t= c_id) +{ + unsigned int temp; + void __iomem *base; + + base =3D GET_BASE_ADDR(tc_id); + + /* + * LVTS thermal controller has two interrupts for thermal HW reboot + * One is for AP SW and the other is for RGU + * The interrupt of AP SW can turn off by a bit of a register, but + * the other for RGU cannot. + * To prevent rebooting device accidentally, we are going to add + * a huge offset to LVTS and make LVTS always report extremely low + * temperature. + */ + + /* + * After adding the huge offset 0x3FFF, LVTS alawys adds the + * offset to MSR_RAW. + * When MSR_RAW is larger, SW will convert lower temperature/ + */ + temp =3D readl(LVTSPROTCTL_0 + base); + writel(temp | 0x3FFF, LVTSPROTCTL_0 + base); + + /* Disable the interrupt of AP SW */ + temp =3D readl(LVTSMONINT_0 + base); + writel(temp & ~(STAGE3_INT_EN), LVTSMONINT_0 + base); +} + +static void enable_hw_reboot_interrupt(struct lvts_data *lvts_data, int tc= _id) +{ + unsigned int temp; + void __iomem *base; + + base =3D GET_BASE_ADDR(tc_id); + + /* Enable the interrupt of AP SW */ + temp =3D readl(LVTSMONINT_0 + base); + writel(temp | STAGE3_INT_EN, LVTSMONINT_0 + base); + /* Clear the offset */ + temp =3D readl(LVTSPROTCTL_0 + base); + writel(temp & ~PROTOFFSET, LVTSPROTCTL_0 + base); +} + +static void set_tc_hw_reboot_threshold(struct lvts_data *lvts_data, + int trip_point, int tc_id) +{ + struct device *dev =3D lvts_data->dev; + unsigned int msr_raw, temp, config, d_index; + void __iomem *base; + + base =3D GET_BASE_ADDR(tc_id); + d_index =3D get_dominator_index(lvts_data, tc_id); + + dev_info(dev, "%s: LVTS%d, the dominator sensing point=3D %d\n", + __func__, tc_id, d_index); + + disable_hw_reboot_interrupt(lvts_data, tc_id); + + temp =3D readl(LVTSPROTCTL_0 + base); + if (d_index =3D=3D ALL_SENSING_POINTS) { + /* Maximum of 4 sensing points */ + config =3D (0x1 << 16); + writel(config | temp, LVTSPROTCTL_0 + base); + } else { + /* Select protection sensor */ + config =3D ((d_index << 2) + 0x2) << 16; + writel(config | temp, LVTSPROTCTL_0 + base); + } + + msr_raw =3D lvts_temp_to_raw(&lvts_data->coeff, trip_point); + writel(msr_raw, LVTSPROTTC_0 + base); + + enable_hw_reboot_interrupt(lvts_data, tc_id); +} + +static void set_all_tc_hw_reboot(struct lvts_data *lvts_data) +{ + const struct tc_settings *tc =3D lvts_data->tc; + int i, trip_point; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + trip_point =3D tc[i].hw_reboot_trip_point; + + if (tc[i].num_sensor =3D=3D 0) + continue; + + if (trip_point =3D=3D DISABLE_THERMAL_HW_REBOOT) + continue; + + set_tc_hw_reboot_threshold(lvts_data, trip_point, i); + } +} + +static int lvts_init(struct lvts_data *lvts_data) +{ + struct platform_ops *ops =3D &lvts_data->ops; + struct device *dev =3D lvts_data->dev; + int ret; + + ret =3D clk_prepare_enable(lvts_data->clk); + if (ret) { + dev_err(dev, + "Error: Failed to enable lvts controller clock: %d\n", + ret); + return ret; + } + + lvts_reset(lvts_data); + + device_identification(lvts_data); + if (ops->device_enable_and_init) + ops->device_enable_and_init(lvts_data); + + if (IS_ENABLE(FEATURE_DEVICE_AUTO_RCK)) { + if (ops->device_enable_auto_rck) + ops->device_enable_auto_rck(lvts_data); + } else { + if (ops->device_read_count_rc_n) + ops->device_read_count_rc_n(lvts_data); + } + + if (ops->set_cal_data) + ops->set_cal_data(lvts_data); + + disable_all_sensing_points(lvts_data); + wait_all_tc_sensing_point_idle(lvts_data); + if (ops->init_controller) + ops->init_controller(lvts_data); + enable_all_sensing_points(lvts_data); + + set_all_tc_hw_reboot(lvts_data); + + return 0; +} + +static int prepare_calibration_data(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + struct sensor_cal_data *cal_data =3D &lvts_data->cal_data; + struct platform_ops *ops =3D &lvts_data->ops; + int i, offset, size; + char buffer[512]; + + cal_data->count_r =3D devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*cal_data->count_r), GFP_KERNEL); + if (!cal_data->count_r) + return -ENOMEM; + + cal_data->count_rc =3D devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*cal_data->count_rc), GFP_KERNEL); + if (!cal_data->count_rc) + return -ENOMEM; + + if (ops->efuse_to_cal_data) + ops->efuse_to_cal_data(lvts_data); + + cal_data->use_fake_efuse =3D 1; + if (cal_data->golden_temp !=3D 0) { + cal_data->use_fake_efuse =3D 0; + } else { + for (i =3D 0; i < lvts_data->num_sensor; i++) { + if (cal_data->count_r[i] !=3D 0 || + cal_data->count_rc[i] !=3D 0) { + cal_data->use_fake_efuse =3D 0; + break; + } + } + } + + if (cal_data->use_fake_efuse) { + /* It means all efuse data are equal to 0 */ + dev_err(dev, + "[lvts_cal] This sample is not calibrated, fake !!\n"); + + cal_data->golden_temp =3D cal_data->default_golden_temp; + for (i =3D 0; i < lvts_data->num_sensor; i++) { + cal_data->count_r[i] =3D cal_data->default_count_r; + cal_data->count_rc[i] =3D cal_data->default_count_rc; + } + } + + lvts_data->coeff.golden_temp =3D cal_data->golden_temp; + + dev_info(dev, "[lvts_cal] golden_temp =3D %d\n", cal_data->golden_temp); + + size =3D sizeof(buffer); + offset =3D snprintf(buffer, size, "[lvts_cal] num:g_count:g_count_rc "); + for (i =3D 0; i < lvts_data->num_sensor; i++) + offset +=3D snprintf(buffer + offset, size - offset, "%d:%d:%d ", + i, cal_data->count_r[i], cal_data->count_rc[i]); + + buffer[offset] =3D '\0'; + dev_info(dev, "%s\n", buffer); + + return 0; +} + +static int get_calibration_data(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + char cell_name[8]; + struct nvmem_cell *cell; + u32 *buf; + size_t len; + int i, j, index =3D 0, ret; + + lvts_data->efuse =3D devm_kcalloc(dev, lvts_data->num_efuse_addr, + sizeof(*lvts_data->efuse), GFP_KERNEL); + if (!lvts_data->efuse) + return -ENOMEM; + + for (i =3D 0; i < lvts_data->num_efuse_block; i++) { + snprintf(cell_name, sizeof(cell_name), "e_data%d", i + 1); + cell =3D nvmem_cell_get(dev, cell_name); + if (IS_ERR(cell)) { + dev_err(dev, "Error: Failed to get nvmem cell %s\n", cell_name); + return PTR_ERR(cell); + } + + buf =3D (u32 *)nvmem_cell_read(cell, &len); + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + for (j =3D 0; j < (len / sizeof(u32)); j++) { + if (index >=3D lvts_data->num_efuse_addr) { + dev_err(dev, "Array efuse is going to overflow"); + kfree(buf); + return -EINVAL; + } + + lvts_data->efuse[index] =3D buf[j]; + index++; + } + + kfree(buf); + } + + ret =3D prepare_calibration_data(lvts_data); + + return ret; +} + +static int lvts_init_tc_regs(struct device *dev, struct lvts_data *lvts_da= ta) +{ + const struct tc_settings *tc =3D lvts_data->tc; + unsigned int i, j, s_index; + void __iomem *base; + + lvts_data->reg =3D devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*lvts_data->reg), GFP_KERNEL); + if (!lvts_data->reg) + return -ENOMEM; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(i); + for (j =3D 0; j < tc[i].num_sensor; j++) { + s_index =3D tc[i].sensor_map[j]; + lvts_data->reg[s_index] =3D LVTSMSR0_0 + base + 0x4 * j; + } + } + + return 0; +} + +static int of_update_lvts_data(struct lvts_data *lvts_data, + struct platform_device *pdev) +{ + struct device *dev =3D lvts_data->dev; + struct power_domain *domain; + struct resource *res; + unsigned int i; + int ret; + + lvts_data->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(lvts_data->clk)) + return PTR_ERR(lvts_data->clk); + + domain =3D devm_kcalloc(dev, lvts_data->num_domain, sizeof(*domain), GFP_= KERNEL); + if (!domain) + return -ENOMEM; + + for (i =3D 0; i < lvts_data->num_domain; i++) { + /* Get base address */ + res =3D platform_get_resource(pdev, IORESOURCE_MEM, i); + if (!res) { + dev_err(dev, "No IO resource, index %d\n", i); + return -ENXIO; + } + + domain[i].base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(domain[i].base)) { + dev_err(dev, "Failed to remap io, index %d\n", i); + return PTR_ERR(domain[i].base); + } + + /* Get interrupt number */ + res =3D platform_get_resource(pdev, IORESOURCE_IRQ, i); + if (!res) { + dev_err(dev, "No irq resource, index %d\n", i); + return -EINVAL; + } + domain[i].irq_num =3D res->start; + + /* Get reset control */ + domain[i].reset =3D devm_reset_control_get_by_index(dev, i); + if (IS_ERR(domain[i].reset)) { + dev_err(dev, "Failed to get, index %d\n", i); + return PTR_ERR(domain[i].reset); + } + } + + lvts_data->domain =3D domain; + + ret =3D lvts_init_tc_regs(dev, lvts_data); + if (ret) + return ret; + + ret =3D get_calibration_data(lvts_data); + if (ret) + return ret; + + return 0; +} + +static void lvts_device_close(struct lvts_data *lvts_data) +{ + unsigned int i; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(i); + lvts_write_device(lvts_data, RESET_ALL_DEVICES, i); + writel(DISABLE_LVTS_CTRL_CLK, LVTSCLKEN_0 + base); + } +} + +static void lvts_close(struct lvts_data *lvts_data) +{ + disable_all_sensing_points(lvts_data); + wait_all_tc_sensing_point_idle(lvts_data); + lvts_device_close(lvts_data); + clk_disable_unprepare(lvts_data->clk); +} + +static void tc_irq_handler(struct lvts_data *lvts_data, int tc_id) +{ + const struct device *dev =3D lvts_data->dev; + unsigned int ret =3D 0; + void __iomem *base; + + base =3D GET_BASE_ADDR(tc_id); + + ret =3D readl(LVTSMONINTSTS_0 + base); + /* Write back to clear interrupt status */ + writel(ret, LVTSMONINTSTS_0 + base); + + dev_info(dev, "[Thermal IRQ] LVTS thermal controller %d, LVTSMONINTSTS=3D= 0x%08x\n", + tc_id, ret); + + if (ret & THERMAL_PROTECTION_STAGE_3) + dev_info(dev, + "[Thermal IRQ]: Thermal protection stage 3 interrupt triggered\n"); +} + +static irqreturn_t irq_handler(int irq, void *dev_id) +{ + struct lvts_data *lvts_data =3D (struct lvts_data *)dev_id; + struct device *dev =3D lvts_data->dev; + const struct tc_settings *tc =3D lvts_data->tc; + unsigned int i, *irq_bitmap; + void __iomem *base; + + irq_bitmap =3D kcalloc(lvts_data->num_domain, sizeof(*irq_bitmap), GFP_AT= OMIC); + + if (!irq_bitmap) + return IRQ_NONE; + + for (i =3D 0; i < lvts_data->num_domain; i++) { + base =3D lvts_data->domain[i].base; + irq_bitmap[i] =3D readl(THERMINTST + base); + dev_info(dev, "%s : THERMINTST =3D 0x%x\n", __func__, irq_bitmap[i]); + } + + for (i =3D 0; i < lvts_data->num_tc; i++) { + if ((irq_bitmap[tc[i].domain_index] & tc[i].irq_bit) =3D=3D 0) + tc_irq_handler(lvts_data, i); + } + + kfree(irq_bitmap); + + return IRQ_HANDLED; +} + +static int lvts_register_irq_handler(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + unsigned int i; + int ret; + + for (i =3D 0; i < lvts_data->num_domain; i++) { + ret =3D devm_request_irq(dev, lvts_data->domain[i].irq_num, irq_handler, + IRQF_TRIGGER_HIGH, "mtk_lvts", lvts_data); + + if (ret) { + dev_err(dev, "Failed to register LVTS IRQ, ret %d, domain %d irq_num %d= \n", + ret, i, lvts_data->domain[i].irq_num); + lvts_close(lvts_data); + return ret; + } + } + + return 0; +} + +static int lvts_register_thermal_zones(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + struct thermal_zone *tzdev; + struct soc_temp_tz *lvts_tz; + int i, ret; + + for (i =3D 0; i < lvts_data->num_sensor; i++) { + lvts_tz =3D devm_kzalloc(dev, sizeof(*lvts_tz), GFP_KERNEL); + if (!lvts_tz) { + lvts_close(lvts_data); + return -ENOMEM; + } + + lvts_tz->id =3D i; + lvts_tz->lvts_data =3D lvts_data; + + tzdev =3D devm_thermal_zone_of_sensor_register(dev, lvts_tz->id, + lvts_tz, &soc_temp_lvts_ops); + + if (IS_ERR(tzdev)) { + if (lvts_tz->id !=3D 0) + return 0; + + ret =3D PTR_ERR(tzdev); + dev_err(dev, "Error: Failed to register lvts tz %d, ret =3D %d\n", + lvts_tz->id, ret); + lvts_close(lvts_data); + return ret; + } + } + + return 0; +} + +static int lvts_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct lvts_data *lvts_data; + int ret; + + lvts_data =3D (struct lvts_data *)of_device_get_match_data(dev); + + if (!lvts_data) { + dev_err(dev, "Error: Failed to get lvts platform data\n"); + return -ENODATA; + } + + lvts_data->dev =3D &pdev->dev; + + ret =3D of_update_lvts_data(lvts_data, pdev); + if (ret) + return ret; + + platform_set_drvdata(pdev, lvts_data); + + ret =3D lvts_init(lvts_data); + if (ret) + return ret; + + ret =3D lvts_register_irq_handler(lvts_data); + if (ret) + return ret; + + ret =3D lvts_register_thermal_zones(lvts_data); + if (ret) + return ret; + + return 0; +} + +static int lvts_remove(struct platform_device *pdev) +{ + struct lvts_data *lvts_data; + + lvts_data =3D (struct lvts_data *)platform_get_drvdata(pdev); + + lvts_close(lvts_data); + + return 0; +} + +static int lvts_suspend(struct platform_device *pdev, pm_message_t state) +{ + struct lvts_data *lvts_data; + + lvts_data =3D (struct lvts_data *)platform_get_drvdata(pdev); + + lvts_close(lvts_data); + + return 0; +} + +static int lvts_resume(struct platform_device *pdev) +{ + int ret; + struct lvts_data *lvts_data; + + lvts_data =3D (struct lvts_data *)platform_get_drvdata(pdev); + + ret =3D lvts_init(lvts_data); + if (ret) + return ret; + + return 0; +} + +static void device_enable_and_init_v4(struct lvts_data *lvts_data) +{ + unsigned int i; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + lvts_write_device(lvts_data, STOP_COUNTING_V4, i); + lvts_write_device(lvts_data, SET_RG_TSFM_LPDLY_V4, i); + lvts_write_device(lvts_data, SET_COUNTING_WINDOW_20US1_V4, i); + lvts_write_device(lvts_data, SET_COUNTING_WINDOW_20US2_V4, i); + lvts_write_device(lvts_data, TSV2F_CHOP_CKSEL_AND_TSV2F_EN_V4, i); + lvts_write_device(lvts_data, TSBG_DEM_CKSEL_X_TSBG_CHOP_EN_V4, i); + lvts_write_device(lvts_data, SET_TS_RSV_V4, i); + lvts_write_device(lvts_data, SET_TS_EN_V4, i); + lvts_write_device(lvts_data, TOGGLE_RG_TSV2F_VCO_RST1_V4, i); + lvts_write_device(lvts_data, TOGGLE_RG_TSV2F_VCO_RST2_V4, i); + } + + lvts_data->counting_window_us =3D 20; +} + +static void device_enable_auto_rck_v4(struct lvts_data *lvts_data) +{ + unsigned int i; + + for (i =3D 0; i < lvts_data->num_tc; i++) + lvts_write_device(lvts_data, SET_LVTS_AUTO_RCK_V4, i); +} + +static int device_read_count_rc_n_v4(struct lvts_data *lvts_data) +{ + /* Resistor-Capacitor Calibration */ + /* count_RC_N: count RC now */ + struct device *dev =3D lvts_data->dev; + const struct tc_settings *tc =3D lvts_data->tc; + struct sensor_cal_data *cal_data =3D &lvts_data->cal_data; + unsigned int offset, size, s_index, data; + void __iomem *base; + int ret, i, j; + char buffer[512]; + + cal_data->count_rc_now =3D devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*cal_data->count_rc_now), GFP_KERNEL); + if (!cal_data->count_rc_now) + return -ENOMEM; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(i); + for (j =3D 0; j < tc[i].num_sensor; j++) { + s_index =3D tc[i].sensor_map[j]; + + lvts_write_device(lvts_data, SELECT_SENSOR_RCK_V4(j), i); + lvts_write_device(lvts_data, SET_DEVICE_SINGLE_MODE_V4, i); + usleep_range(10, 20); + + lvts_write_device(lvts_data, KICK_OFF_RCK_COUNTING_V4, i); + usleep_range(30, 40); + + ret =3D readl_poll_timeout(LVTS_CONFIG_0 + base, data, + !(data & DEVICE_SENSING_STATUS), 2, 200); + if (ret) + dev_err(dev, + "Error: LVTS %d DEVICE_SENSING_STATUS didn't ready\n", i); + + data =3D lvts_read_device(lvts_data, 0x00, i); + + cal_data->count_rc_now[s_index] =3D (data & GENMASK(23, 0)); + } + + /* Recover Setting for Normal Access on + * temperature fetch + */ + lvts_write_device(lvts_data, SET_SENSOR_NO_RCK_V4, i); + lvts_write_device(lvts_data, SET_DEVICE_LOW_POWER_SINGLE_MODE_V4, i); + } + + size =3D sizeof(buffer); + offset =3D snprintf(buffer, size, "[COUNT_RC_NOW] "); + for (i =3D 0; i < lvts_data->num_sensor; i++) + offset +=3D snprintf(buffer + offset, size - offset, "%d:%d ", + i, cal_data->count_rc_now[i]); + + buffer[offset] =3D '\0'; + dev_info(dev, "%s\n", buffer); + + return 0; +} + +static void set_calibration_data_v4(struct lvts_data *lvts_data) +{ + const struct tc_settings *tc =3D lvts_data->tc; + struct sensor_cal_data *cal_data =3D &lvts_data->cal_data; + unsigned int i, j, s_index, e_data; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(i); + + for (j =3D 0; j < tc[i].num_sensor; j++) { + s_index =3D tc[i].sensor_map[j]; + if (IS_ENABLE(FEATURE_DEVICE_AUTO_RCK)) + e_data =3D cal_data->count_r[s_index]; + else + e_data =3D (((unsigned long long) + cal_data->count_rc_now[s_index]) * + cal_data->count_r[s_index]) >> 14; + + writel(e_data, LVTSEDATA00_0 + base + 0x4 * j); + } + } +} + +static void init_controller_v4(struct lvts_data *lvts_data) +{ + struct device *dev =3D lvts_data->dev; + unsigned int i; + void __iomem *base; + + for (i =3D 0; i < lvts_data->num_tc; i++) { + base =3D GET_BASE_ADDR(i); + + lvts_write_device(lvts_data, SET_DEVICE_LOW_POWER_SINGLE_MODE_V4, i); + + writel(SET_SENSOR_INDEX, LVTSTSSEL_0 + base); + writel(SET_CALC_SCALE_RULES, LVTSCALSCALE_0 + base); + + set_polling_speed(lvts_data, i); + set_hw_filter(lvts_data, i); + + dev_info(dev, "lvts%d: read all %d sensors in %d us, one in %d us\n", + i, GET_TC_SENSOR_NUM(i), GROUP_LATENCY_US(i), SENSOR_LATENCY_US(i)); + } +} + +#define MT8192_NUM_LVTS (ARRAY_SIZE(mt8192_tc_settings)) + +enum mt8192_lvts_domain { + MT8192_AP_DOMAIN, + MT8192_MCU_DOMAIN, + MT8192_NUM_DOMAIN +}; + +enum mt8192_lvts_sensor_enum { + MT8192_TS1_0, + MT8192_TS1_1, + MT8192_TS2_0, + MT8192_TS2_1, + MT8192_TS3_0, + MT8192_TS3_1, + MT8192_TS3_2, + MT8192_TS3_3, + MT8192_TS4_0, + MT8192_TS4_1, + MT8192_TS5_0, + MT8192_TS5_1, + MT8192_TS6_0, + MT8192_TS6_1, + MT8192_TS7_0, + MT8192_TS7_1, + MT8192_TS7_2, + MT8192_NUM_TS +}; + +static void mt8192_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct sensor_cal_data *cal_data =3D &lvts_data->cal_data; + + cal_data->golden_temp =3D GET_CAL_DATA_BITMASK(0, 31, 24); + cal_data->count_r[MT8192_TS1_0] =3D GET_CAL_DATA_BITMASK(1, 23, 0); + cal_data->count_r[MT8192_TS1_1] =3D GET_CAL_DATA_BITMASK(2, 23, 0); + cal_data->count_r[MT8192_TS2_0] =3D GET_CAL_DATA_BITMASK(3, 23, 0); + cal_data->count_r[MT8192_TS2_1] =3D GET_CAL_DATA_BITMASK(4, 23, 0); + cal_data->count_r[MT8192_TS3_0] =3D GET_CAL_DATA_BITMASK(5, 23, 0); + cal_data->count_r[MT8192_TS3_1] =3D GET_CAL_DATA_BITMASK(6, 23, 0); + cal_data->count_r[MT8192_TS3_2] =3D GET_CAL_DATA_BITMASK(7, 23, 0); + cal_data->count_r[MT8192_TS3_3] =3D GET_CAL_DATA_BITMASK(8, 23, 0); + cal_data->count_r[MT8192_TS4_0] =3D GET_CAL_DATA_BITMASK(9, 23, 0); + cal_data->count_r[MT8192_TS4_1] =3D GET_CAL_DATA_BITMASK(10, 23, 0); + cal_data->count_r[MT8192_TS5_0] =3D GET_CAL_DATA_BITMASK(11, 23, 0); + cal_data->count_r[MT8192_TS5_1] =3D GET_CAL_DATA_BITMASK(12, 23, 0); + cal_data->count_r[MT8192_TS6_0] =3D GET_CAL_DATA_BITMASK(13, 23, 0); + cal_data->count_r[MT8192_TS6_1] =3D GET_CAL_DATA_BITMASK(14, 23, 0); + cal_data->count_r[MT8192_TS7_0] =3D GET_CAL_DATA_BITMASK(15, 23, 0); + cal_data->count_r[MT8192_TS7_1] =3D GET_CAL_DATA_BITMASK(16, 23, 0); + cal_data->count_r[MT8192_TS7_2] =3D GET_CAL_DATA_BITMASK(17, 23, 0); + + cal_data->count_rc[MT8192_TS1_0] =3D GET_CAL_DATA_BITMASK(21, 23, 0); + + cal_data->count_rc[MT8192_TS2_0] =3D (GET_CAL_DATA_BITMASK(1, 31, 24) << = 16) + + (GET_CAL_DATA_BITMASK(2, 31, 24) << 8) + + GET_CAL_DATA_BITMASK(3, 31, 24); + + cal_data->count_rc[MT8192_TS3_0] =3D (GET_CAL_DATA_BITMASK(4, 31, 24) << = 16) + + (GET_CAL_DATA_BITMASK(5, 31, 24) << 8) + + GET_CAL_DATA_BITMASK(6, 31, 24); + + cal_data->count_rc[MT8192_TS4_0] =3D (GET_CAL_DATA_BITMASK(7, 31, 24) << = 16) + + (GET_CAL_DATA_BITMASK(8, 31, 24) << 8) + + GET_CAL_DATA_BITMASK(9, 31, 24); + + cal_data->count_rc[MT8192_TS5_0] =3D (GET_CAL_DATA_BITMASK(10, 31, 24) <<= 16) + + (GET_CAL_DATA_BITMASK(11, 31, 24) << 8) + + GET_CAL_DATA_BITMASK(12, 31, 24); + + cal_data->count_rc[MT8192_TS6_0] =3D (GET_CAL_DATA_BITMASK(13, 31, 24) <<= 16) + + (GET_CAL_DATA_BITMASK(14, 31, 24) << 8) + + GET_CAL_DATA_BITMASK(15, 31, 24); + + cal_data->count_rc[MT8192_TS7_0] =3D (GET_CAL_DATA_BITMASK(16, 31, 24) <<= 16) + + (GET_CAL_DATA_BITMASK(17, 31, 24) << 8) + + GET_CAL_DATA_BITMASK(18, 31, 24); +} + +static const struct tc_settings mt8192_tc_settings[] =3D { + [0] =3D { + .domain_index =3D MT8192_MCU_DOMAIN, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8192_TS1_0, MT8192_TS1_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(3), + }, + [1] =3D { + .domain_index =3D MT8192_MCU_DOMAIN, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8192_TS2_0, MT8192_TS2_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(4), + }, + [2] =3D { + .domain_index =3D MT8192_MCU_DOMAIN, + .addr_offset =3D 0x200, + .num_sensor =3D 4, + .sensor_map =3D {MT8192_TS3_0, MT8192_TS3_1, MT8192_TS3_2, MT8192_TS3_3}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(5), + }, + [3] =3D { + .domain_index =3D MT8192_AP_DOMAIN, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8192_TS4_0, MT8192_TS4_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(3), + }, + [4] =3D { + .domain_index =3D MT8192_AP_DOMAIN, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8192_TS5_0, MT8192_TS5_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(4), + }, + [5] =3D { + .domain_index =3D MT8192_AP_DOMAIN, + .addr_offset =3D 0x200, + .num_sensor =3D 2, + .sensor_map =3D {MT8192_TS6_0, MT8192_TS6_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(5), + }, + [6] =3D { + .domain_index =3D MT8192_AP_DOMAIN, + .addr_offset =3D 0x300, + .num_sensor =3D 3, + .sensor_map =3D {MT8192_TS7_0, MT8192_TS7_1, MT8192_TS7_2}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT2, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(6), + } +}; + +static const struct lvts_data mt8192_lvts_data =3D { + .num_domain =3D MT8192_NUM_DOMAIN, + .num_tc =3D MT8192_NUM_LVTS, + .tc =3D mt8192_tc_settings, + .num_sensor =3D MT8192_NUM_TS, + .ops =3D { + .efuse_to_cal_data =3D mt8192_efuse_to_cal_data, + .device_enable_and_init =3D device_enable_and_init_v4, + .device_enable_auto_rck =3D device_enable_auto_rck_v4, + .device_read_count_rc_n =3D device_read_count_rc_n_v4, + .set_cal_data =3D set_calibration_data_v4, + .init_controller =3D init_controller_v4, + }, + .feature_bitmap =3D FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr =3D 22, + .num_efuse_block =3D 1, + .cal_data =3D { + .default_golden_temp =3D 50, + .default_count_r =3D 35000, + .default_count_rc =3D 2750, + }, + .coeff =3D { + .a =3D -250460, + .b =3D 250460, + }, +}; + +static const struct of_device_id lvts_of_match[] =3D { + { + .compatible =3D "mediatek,mt8192-lvts", + .data =3D (void *)&mt8192_lvts_data, + }, + { + }, +}; +MODULE_DEVICE_TABLE(of, lvts_of_match); + +static struct platform_driver soc_temp_lvts =3D { + .probe =3D lvts_probe, + .remove =3D lvts_remove, + .suspend =3D lvts_suspend, + .resume =3D lvts_resume, + .driver =3D { + .name =3D "mtk-soc-temp-lvts", + .of_match_table =3D lvts_of_match, + }, +}; + +module_platform_driver(soc_temp_lvts); +MODULE_AUTHOR("Yu-Chia Chang "); +MODULE_AUTHOR("Michael Kao "); +MODULE_DESCRIPTION("MediaTek soc temperature driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/thermal/mediatek/soc_temp_lvts.h b/drivers/thermal/med= iatek/soc_temp_lvts.h new file mode 100644 index 000000000000..8fc0d114b8d0 --- /dev/null +++ b/drivers/thermal/mediatek/soc_temp_lvts.h @@ -0,0 +1,304 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#ifndef __MTK_SOC_TEMP_LVTS_H__ +#define __MTK_SOC_TEMP_LVTS_H__ + +/* + * LVTS HW filter settings + * 000: Get one sample + * 001: Get 2 samples and average them + * 010: Get 4 samples, drop max and min, then average the rest of 2 samples + * 011: Get 6 samples, drop max and min, then average the rest of 4 samples + * 100: Get 10 samples, drop max and min, then average the rest of 8 sampl= es + * 101: Get 18 samples, drop max and min, then average the rest of 16 samp= les + */ +enum lvts_hw_filter { + LVTS_FILTER_1, + LVTS_FILTER_2, + LVTS_FILTER_2_OF_4, + LVTS_FILTER_4_OF_6, + LVTS_FILTER_8_OF_10, + LVTS_FILTER_16_OF_18 +}; + +enum lvts_sensing_point { + SENSING_POINT0, + SENSING_POINT1, + SENSING_POINT2, + SENSING_POINT3, + ALL_SENSING_POINTS +}; + +struct lvts_data; + +struct speed_settings { + unsigned int period_unit; + unsigned int group_interval_delay; + unsigned int filter_interval_delay; + unsigned int sensor_interval_delay; +}; + +struct tc_settings { + unsigned int domain_index; + unsigned int addr_offset; + unsigned int num_sensor; + unsigned int sensor_map[ALL_SENSING_POINTS]; /* In sensor ID */ + struct speed_settings tc_speed; + /* + * HW filter setting + * 000: Get one sample + * 001: Get 2 samples and average them + * 010: Get 4 samples, drop max and min, then average the rest of 2 sampl= es + * 011: Get 6 samples, drop max and min, then average the rest of 4 sampl= es + * 100: Get 10 samples, drop max and min, then average the rest of 8 samp= les + * 101: Get 18 samples, drop max and min, then average the rest of 16 sam= ples + */ + unsigned int hw_filter; + /* + * Dominator_sensing point is used to select a sensing point + * and reference its temperature to trigger Thermal HW Reboot + * When it is ALL_SENSING_POINTS, it will select all sensing points + */ + int dominator_sensing_point; + int hw_reboot_trip_point; /* -274000: Disable HW reboot */ + unsigned int irq_bit; +}; + +struct formula_coeff { + int a; + int b; + unsigned int golden_temp; +}; + +struct sensor_cal_data { + int use_fake_efuse; /* 1: Use fake efuse, 0: Use real efuse */ + unsigned int golden_temp; + unsigned int *count_r; + unsigned int *count_rc; + unsigned int *count_rc_now; + + unsigned int default_golden_temp; + unsigned int default_count_r; + unsigned int default_count_rc; +}; + +struct platform_ops { + void (*efuse_to_cal_data)(struct lvts_data *lvts_data); + void (*device_enable_and_init)(struct lvts_data *lvts_data); + void (*device_enable_auto_rck)(struct lvts_data *lvts_data); + int (*device_read_count_rc_n)(struct lvts_data *lvts_data); + void (*set_cal_data)(struct lvts_data *lvts_data); + void (*init_controller)(struct lvts_data *lvts_data); +}; + +struct power_domain { + void __iomem *base; /* LVTS base addresses */ + unsigned int irq_num; /* LVTS interrupt numbers */ + struct reset_control *reset; +}; + +struct sensor_data { + void __iomem *base; /* Sensor base address */ + int offset; /* Sensor offset */ +}; + +struct lvts_data { + struct device *dev; + struct clk *clk; + unsigned int num_domain; + struct power_domain *domain; + + int num_tc; /* Number of LVTS thermal controllers */ + const struct tc_settings *tc; + int counting_window_us; /* LVTS device counting window */ + + int num_sensor; /* Number of sensors in this platform */ + void __iomem **reg; + + struct platform_ops ops; + int feature_bitmap; /* Show what features are enabled */ + + unsigned int num_efuse_addr; + unsigned int *efuse; + unsigned int num_efuse_block; /* Number of contiguous efuse indexes */ + struct sensor_cal_data cal_data; + struct formula_coeff coeff; +}; + +struct soc_temp_tz { + unsigned int id; /* if id is 0, get max temperature of all sensors */ + struct lvts_data *lvts_data; +}; + +struct match_entry { + char chip[32]; + struct lvts_data *lvts_data; +}; + +struct lvts_match_data { + unsigned int hw_version; + struct match_entry *table; + void (*set_up_common_callbacks)(struct lvts_data *lvts_data); + struct list_head node; +}; + +struct lvts_id { + unsigned int hw_version; + char chip[32]; +}; + +/* LVTS device register */ +#define RG_TSFM_DATA_0 0x00 +#define RG_TSFM_DATA_1 0x01 +#define RG_TSFM_DATA_2 0x02 +#define RG_TSFM_CTRL_0 0x03 +#define RG_TSFM_CTRL_1 0x04 +#define RG_TSFM_CTRL_2 0x05 +#define RG_TSFM_CTRL_3 0x06 +#define RG_TSFM_CTRL_4 0x07 +#define RG_TSV2F_CTRL_0 0x08 +#define RG_TSV2F_CTRL_1 0x09 +#define RG_TSV2F_CTRL_2 0x0A +#define RG_TSV2F_CTRL_3 0x0B +#define RG_TSV2F_CTRL_4 0x0C +#define RG_TSV2F_CTRL_5 0x0D +#define RG_TSV2F_CTRL_6 0x0E +#define RG_TEMP_DATA_0 0x10 +#define RG_TEMP_DATA_1 0x11 +#define RG_TEMP_DATA_2 0x12 +#define RG_TEMP_DATA_3 0x13 +#define RG_RC_DATA_0 0x14 +#define RG_RC_DATA_1 0x15 +#define RG_RC_DATA_2 0x16 +#define RG_RC_DATA_3 0x17 +#define RG_DIV_DATA_0 0x18 +#define RG_DIV_DATA_1 0x19 +#define RG_DIV_DATA_2 0x1A +#define RG_DIV_DATA_3 0x1B +#define RG_TST_DATA_0 0x70 +#define RG_TST_DATA_1 0x71 +#define RG_TST_DATA_2 0x72 +#define RG_TST_CTRL 0x73 +#define RG_DBG_FQMTR 0xF0 +#define RG_DBG_LPSEQ 0xF1 +#define RG_DBG_STATE 0xF2 +#define RG_DBG_CHKSUM 0xF3 +#define RG_DID_LVTS 0xFC +#define RG_DID_REV 0xFD +#define RG_TSFM_RST 0xFF + +/* LVTS controller register */ +#define LVTSMONCTL0_0 0x000 +#define LVTS_SINGLE_SENSE BIT(9) +#define ENABLE_SENSING_POINT(num) (LVTS_SINGLE_SENSE | GENMASK(((num) - 1)= , 0)) +#define DISABLE_SENSING_POINT (LVTS_SINGLE_SENSE | 0x0) +#define LVTSMONCTL1_0 0x004 +#define LVTSMONCTL2_0 0x008 +#define LVTSMONINT_0 0x00C +#define STAGE3_INT_EN BIT(31) +#define LVTSMONINTSTS_0 0x010 +#define LVTSMONIDET0_0 0x014 +#define LVTSMONIDET1_0 0x018 +#define LVTSMONIDET2_0 0x01C +#define LVTSMONIDET3_0 0x020 +#define LVTSH2NTHRE_0 0x024 +#define LVTSHTHRE_0 0x028 +#define LVTSCTHRE_0 0x02C +#define LVTSOFFSETH_0 0x030 +#define LVTSOFFSETL_0 0x034 +#define LVTSMSRCTL0_0 0x038 +#define LVTSMSRCTL1_0 0x03C +#define LVTSTSSEL_0 0x040 +#define SET_SENSOR_INDEX 0x13121110 +#define LVTSDEVICETO_0 0x044 +#define LVTSCALSCALE_0 0x048 +#define SET_CALC_SCALE_RULES 0x00000300 +#define LVTS_ID_0 0x04C +#define LVTS_CONFIG_0 0x050 + +#define BROADCAST_ID_UPDATE BIT(26) +#define DEVICE_SENSING_STATUS BIT(25) +#define DEVICE_ACCESS_STARTUS BIT(24) +#define WRITE_ACCESS BIT(16) +#define DEVICE_WRITE (BIT(31) | CK26M_ACTIVE | DEVICE_ACCESS_STARTUS \ + | BIT(17) | WRITE_ACCESS) +#define DEVICE_READ (BIT(31) | CK26M_ACTIVE | DEVICE_ACCESS_STARTUS \ + | 1 << 17) +#define RESET_ALL_DEVICES (DEVICE_WRITE | RG_TSFM_RST << 8 | 0xFF) +#define READ_BACK_DEVICE_ID (BIT(31) | CK26M_ACTIVE | BROADCAST_ID_UPDATE \ + | DEVICE_ACCESS_STARTUS | BIT(17) \ + | RG_DID_LVTS << 8) +#define READ_DEVICE_REG(reg_idx) (DEVICE_READ | (reg_idx) << 8 | 0x00) +#define LVTSEDATA00_0 0x054 +#define LVTSEDATA01_0 0x058 +#define LVTSEDATA02_0 0x05C +#define LVTSEDATA03_0 0x060 +#define LVTSMSR0_0 0x090 +#define MRS_RAW_MASK GENMASK(15, 0) +#define MRS_RAW_VALID_BIT BIT(16) +#define LVTSMSR1_0 0x094 +#define LVTSMSR2_0 0x098 +#define LVTSMSR3_0 0x09C +#define LVTSIMMD0_0 0x0A0 +#define LVTSIMMD1_0 0x0A4 +#define LVTSIMMD2_0 0x0A8 +#define LVTSIMMD3_0 0x0AC +#define LVTSRDATA0_0 0x0B0 +#define LVTSRDATA1_0 0x0B4 +#define LVTSRDATA2_0 0x0B8 +#define LVTSRDATA3_0 0x0BC +#define LVTSPROTCTL_0 0x0C0 +#define PROTOFFSET GENMASK(15, 0) +#define LVTSPROTTA_0 0x0C4 +#define LVTSPROTTB_0 0x0C8 +#define LVTSPROTTC_0 0x0CC +#define LVTSCLKEN_0 0x0E4 +#define ENABLE_LVTS_CTRL_CLK (1) +#define DISABLE_LVTS_CTRL_CLK (0) +#define LVTSDBGSEL_0 0x0E8 +#define LVTSDBGSIG_0 0x0EC +#define LVTSSPARE0_0 0x0F0 +#define LVTSSPARE1_0 0x0F4 +#define LVTSSPARE2_0 0x0F8 +#define LVTSSPARE3_0 0x0FC +#define THERMINTST 0xF04 + +/* LVTS register mask */ +#define THERMAL_COLD_INTERRUPT_0 0x00000001 +#define THERMAL_HOT_INTERRUPT_0 0x00000002 +#define THERMAL_LOW_OFFSET_INTERRUPT_0 0x00000004 +#define THERMAL_HIGH_OFFSET_INTERRUPT_0 0x00000008 +#define THERMAL_HOT2NORMAL_INTERRUPT_0 0x00000010 +#define THERMAL_COLD_INTERRUPT_1 0x00000020 +#define THERMAL_HOT_INTERRUPT_1 0x00000040 +#define THERMAL_LOW_OFFSET_INTERRUPT_1 0x00000080 +#define THERMAL_HIGH_OFFSET_INTERRUPT_1 0x00000100 +#define THERMAL_HOT2NORMAL_INTERRUPT_1 0x00000200 +#define THERMAL_COLD_INTERRUPT_2 0x00000400 +#define THERMAL_HOT_INTERRUPT_2 0x00000800 +#define THERMAL_LOW_OFFSET_INTERRUPT_2 0x00001000 +#define THERMAL_HIGH_OFFSET_INTERRUPT_2 0x00002000 +#define THERMAL_HOT2NORMAL_INTERRUPT_2 0x00004000 +#define THERMAL_AHB_TIMEOUT_INTERRUPT 0x00008000 +#define THERMAL_DEVICE_TIMEOUT_INTERRUPT 0x00008000 +#define THERMAL_IMMEDIATE_INTERRUPT_0 0x00010000 +#define THERMAL_IMMEDIATE_INTERRUPT_1 0x00020000 +#define THERMAL_IMMEDIATE_INTERRUPT_2 0x00040000 +#define THERMAL_FILTER_INTERRUPT_0 0x00080000 +#define THERMAL_FILTER_INTERRUPT_1 0x00100000 +#define THERMAL_FILTER_INTERRUPT_2 0x00200000 +#define THERMAL_COLD_INTERRUPT_3 0x00400000 +#define THERMAL_HOT_INTERRUPT_3 0x00800000 +#define THERMAL_LOW_OFFSET_INTERRUPT_3 0x01000000 +#define THERMAL_HIGH_OFFSET_INTERRUPT_3 0x02000000 +#define THERMAL_HOT2NORMAL_INTERRUPT_3 0x04000000 +#define THERMAL_IMMEDIATE_INTERRUPT_3 0x08000000 +#define THERMAL_FILTER_INTERRUPT_3 0x10000000 +#define THERMAL_PROTECTION_STAGE_1 0x20000000 +#define THERMAL_PROTECTION_STAGE_2 0x40000000 +#define THERMAL_PROTECTION_STAGE_3 0x80000000 + +#endif /* __MTK_SOC_TEMP_LVTS_H__ */ --=20 2.35.1 From nobody Sat Sep 21 23:31:48 2024 Return-Path: X-Spam-Checker-Version: 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id k24-20020a05600c1c9800b003974027722csm2703693wms.47.2022.05.24.08.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 08:28:08 -0700 (PDT) From: Alexandre Bailon To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, Michael Kao , Ben Tseng , Alexandre Bailon Subject: [PATCH v7 4/6] thermal: mediatek: Add thermal zone settings for mt8195 Date: Tue, 24 May 2022 17:25:51 +0200 Message-Id: <20220524152552.246193-5-abailon@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220524152552.246193-1-abailon@baylibre.com> References: <20220524152552.246193-1-abailon@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Michael Kao Add thermal zone settings for mt8195 Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon --- drivers/thermal/mediatek/soc_temp_lvts.c | 201 +++++++++++++++++++++-- 1 file changed, 187 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/mediatek/soc_temp_lvts.c b/drivers/thermal/med= iatek/soc_temp_lvts.c index 4b8c4c419f8e..c77c045d2599 100644 --- a/drivers/thermal/mediatek/soc_temp_lvts.c +++ b/drivers/thermal/mediatek/soc_temp_lvts.c @@ -49,6 +49,7 @@ =20 #define CLOCK_26MHZ_CYCLE_NS (38) #define BUS_ACCESS_US (2) +#define GOLDEN_TEMP_MAX (62) =20 #define FEATURE_DEVICE_AUTO_RCK (BIT(0)) #define FEATURE_CK26M_ACTIVE (BIT(1)) @@ -544,21 +545,10 @@ static int prepare_calibration_data(struct lvts_data = *lvts_data) if (!cal_data->count_rc) return -ENOMEM; =20 - if (ops->efuse_to_cal_data) + if (ops->efuse_to_cal_data && !cal_data->use_fake_efuse) ops->efuse_to_cal_data(lvts_data); - - cal_data->use_fake_efuse =3D 1; - if (cal_data->golden_temp !=3D 0) { - cal_data->use_fake_efuse =3D 0; - } else { - for (i =3D 0; i < lvts_data->num_sensor; i++) { - if (cal_data->count_r[i] !=3D 0 || - cal_data->count_rc[i] !=3D 0) { - cal_data->use_fake_efuse =3D 0; - break; - } - } - } + if (cal_data->golden_temp =3D=3D 0 || cal_data->golden_temp > GOLDEN_TEMP= _MAX) + cal_data->use_fake_efuse =3D 1; =20 if (cal_data->use_fake_efuse) { /* It means all efuse data are equal to 0 */ @@ -1233,11 +1223,194 @@ static const struct lvts_data mt8192_lvts_data =3D= { }, }; =20 +#define MT8195_NUM_LVTS (ARRAY_SIZE(mt8195_tc_settings)) + +enum mt8195_lvts_domain { + MT8195_AP_DOMAIN, + MT8195_MCU_DOMAIN, + MT8195_NUM_DOMAIN +}; + +enum mt8195_lvts_sensor_enum { + MT8195_TS1_0, + MT8195_TS1_1, + MT8195_TS2_0, + MT8195_TS2_1, + MT8195_TS3_0, + MT8195_TS3_1, + MT8195_TS3_2, + MT8195_TS3_3, + MT8195_TS4_0, + MT8195_TS4_1, + MT8195_TS5_0, + MT8195_TS5_1, + MT8195_TS6_0, + MT8195_TS6_1, + MT8195_TS6_2, + MT8195_TS7_0, + MT8195_TS7_1, + MT8195_NUM_TS +}; + +static void mt8195_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct sensor_cal_data *cal_data =3D &lvts_data->cal_data; + + cal_data->golden_temp =3D GET_CAL_DATA_BITMASK(0, 31, 24); + cal_data->count_r[MT8195_TS1_0] =3D GET_CAL_DATA_BITMASK(1, 23, 0); + cal_data->count_r[MT8195_TS1_1] =3D (GET_CAL_DATA_BITMASK(2, 15, 0) << 8)= + + GET_CAL_DATA_BITMASK(1, 31, 24); + cal_data->count_r[MT8195_TS2_0] =3D GET_CAL_DATA_BITMASK(3, 31, 8); + cal_data->count_r[MT8195_TS2_1] =3D GET_CAL_DATA_BITMASK(4, 23, 0); + cal_data->count_r[MT8195_TS3_0] =3D (GET_CAL_DATA_BITMASK(6, 7, 0) << 16)= + + GET_CAL_DATA_BITMASK(5, 31, 16); + cal_data->count_r[MT8195_TS3_1] =3D GET_CAL_DATA_BITMASK(6, 31, 8); + cal_data->count_r[MT8195_TS3_2] =3D GET_CAL_DATA_BITMASK(7, 23, 0); + cal_data->count_r[MT8195_TS3_3] =3D (GET_CAL_DATA_BITMASK(8, 15, 0) << 8)= + + GET_CAL_DATA_BITMASK(7, 31, 24); + cal_data->count_r[MT8195_TS4_0] =3D GET_CAL_DATA_BITMASK(9, 31, 8); + cal_data->count_r[MT8195_TS4_1] =3D GET_CAL_DATA_BITMASK(10, 23, 0); + cal_data->count_r[MT8195_TS5_0] =3D (GET_CAL_DATA_BITMASK(12, 7, 0) << 16= ) + + GET_CAL_DATA_BITMASK(11, 31, 16); + cal_data->count_r[MT8195_TS5_1] =3D GET_CAL_DATA_BITMASK(12, 31, 8); + cal_data->count_r[MT8195_TS6_0] =3D (GET_CAL_DATA_BITMASK(14, 15, 0) << 8= ) + + GET_CAL_DATA_BITMASK(13, 31, 24); + cal_data->count_r[MT8195_TS6_1] =3D (GET_CAL_DATA_BITMASK(15, 7, 0) << 16= ) + + GET_CAL_DATA_BITMASK(14, 31, 16); + cal_data->count_r[MT8195_TS6_2] =3D GET_CAL_DATA_BITMASK(15, 31, 8); + cal_data->count_r[MT8195_TS7_0] =3D (GET_CAL_DATA_BITMASK(17, 15, 0) << 8= ) + + GET_CAL_DATA_BITMASK(16, 31, 24); + cal_data->count_r[MT8195_TS7_1] =3D (GET_CAL_DATA_BITMASK(18, 7, 0) << 16= ) + + GET_CAL_DATA_BITMASK(17, 31, 16); + cal_data->count_rc[MT8195_TS1_0] =3D (GET_CAL_DATA_BITMASK(3, 7, 0) << 16= ) + + GET_CAL_DATA_BITMASK(2, 31, 16); + cal_data->count_rc[MT8195_TS2_0] =3D (GET_CAL_DATA_BITMASK(5, 15, 0) << 8= ) + + GET_CAL_DATA_BITMASK(4, 31, 24); + cal_data->count_rc[MT8195_TS3_0] =3D (GET_CAL_DATA_BITMASK(9, 7, 0) << 16= ) + + GET_CAL_DATA_BITMASK(8, 31, 16); + cal_data->count_rc[MT8195_TS4_0] =3D (GET_CAL_DATA_BITMASK(11, 15, 0) << = 8) + + GET_CAL_DATA_BITMASK(10, 31, 24); + cal_data->count_rc[MT8195_TS5_0] =3D GET_CAL_DATA_BITMASK(13, 23, 0); + cal_data->count_rc[MT8195_TS6_0] =3D GET_CAL_DATA_BITMASK(16, 23, 0); + cal_data->count_rc[MT8195_TS7_0] =3D GET_CAL_DATA_BITMASK(18, 31, 8); +} + +static const struct tc_settings mt8195_tc_settings[] =3D { + [0] =3D { + .domain_index =3D MT8195_MCU_DOMAIN, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS1_0, MT8195_TS1_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(3), + }, + [1] =3D { + .domain_index =3D MT8195_MCU_DOMAIN, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS2_0, MT8195_TS2_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(4), + }, + [2] =3D { + .domain_index =3D MT8195_MCU_DOMAIN, + .addr_offset =3D 0x200, + .num_sensor =3D 4, + .sensor_map =3D {MT8195_TS3_0, MT8195_TS3_1, MT8195_TS3_2, MT8195_TS3_3}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(5), + }, + [3] =3D { + .domain_index =3D MT8195_AP_DOMAIN, + .addr_offset =3D 0x0, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS4_0, MT8195_TS4_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(3), + }, + [4] =3D { + .domain_index =3D MT8195_AP_DOMAIN, + .addr_offset =3D 0x100, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS5_0, MT8195_TS5_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(4), + }, + [5] =3D { + .domain_index =3D MT8195_AP_DOMAIN, + .addr_offset =3D 0x200, + .num_sensor =3D 3, + .sensor_map =3D {MT8195_TS6_0, MT8195_TS6_1, MT8195_TS6_2}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT1, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(5), + }, + [6] =3D { + .domain_index =3D MT8195_AP_DOMAIN, + .addr_offset =3D 0x300, + .num_sensor =3D 2, + .sensor_map =3D {MT8195_TS7_0, MT8195_TS7_1}, + .tc_speed =3D SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter =3D LVTS_FILTER_2_OF_4, + .dominator_sensing_point =3D SENSING_POINT0, + .hw_reboot_trip_point =3D 117000, + .irq_bit =3D BIT(6), + } +}; + +static const struct lvts_data mt8195_lvts_data =3D { + .num_domain =3D MT8195_NUM_DOMAIN, + .num_tc =3D MT8195_NUM_LVTS, + .tc =3D mt8195_tc_settings, + .num_sensor =3D MT8195_NUM_TS, + .ops =3D { + .efuse_to_cal_data =3D mt8195_efuse_to_cal_data, + .device_enable_and_init =3D device_enable_and_init_v4, + .device_enable_auto_rck =3D device_enable_auto_rck_v4, + .device_read_count_rc_n =3D device_read_count_rc_n_v4, + .set_cal_data =3D set_calibration_data_v4, + .init_controller =3D init_controller_v4, + }, + .feature_bitmap =3D FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr =3D 22, + .num_efuse_block =3D 2, + .cal_data =3D { + .default_golden_temp =3D 50, + .default_count_r =3D 35000, + .default_count_rc =3D 2750, + }, + .coeff =3D { + .a =3D -250460, + .b =3D 250460, + }, +}; + static const struct of_device_id lvts_of_match[] =3D { { .compatible =3D "mediatek,mt8192-lvts", .data =3D (void *)&mt8192_lvts_data, }, + { + .compatible =3D "mediatek,mt8195-lvts", + .data =3D (void *)&mt8195_lvts_data, + }, { }, }; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id k24-20020a05600c1c9800b003974027722csm2703693wms.47.2022.05.24.08.28.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 08:28:09 -0700 (PDT) From: Alexandre Bailon To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, Alexandre Bailon Subject: [PATCH v7 5/6] arm64: dts: mt8195: Add efuse node to mt8195 Date: Tue, 24 May 2022 17:25:52 +0200 Message-Id: <20220524152552.246193-6-abailon@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220524152552.246193-1-abailon@baylibre.com> References: <20220524152552.246193-1-abailon@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This adds the efuse node. This will be required by the thermal driver to get the calibration data. Signed-off-by: Alexandre Bailon --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 0011a8ba8f96..51443e83d906 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1238,6 +1238,23 @@ nor_flash: spi@1132c000 { status =3D "disabled"; }; =20 + efuse: efuse@11c10000 { + compatible =3D "mediatek,efuse"; + reg =3D <0 0x11c10000 0 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + lvts_e_data1: data1 { + reg =3D <0x1bc 0x14>; + }; + lvts_e_data2: data1-1 { + reg =3D <0x1d0 0x38>; + }; + svs_calibration: calib@580 { + reg =3D <0x580 0x64>; + }; + }; + u3phy2: t-phy@11c40000 { compatible =3D "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; #address-cells =3D <1>; --=20 2.35.1 From nobody Sat Sep 21 23:31:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49D97C433F5 for ; Tue, 24 May 2022 15:28:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239045AbiEXP2v (ORCPT ); Tue, 24 May 2022 11:28:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238918AbiEXP2V (ORCPT ); Tue, 24 May 2022 11:28:21 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5112A9CF28 for ; Tue, 24 May 2022 08:28:12 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id e28so25609325wra.10 for ; Tue, 24 May 2022 08:28:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MXAnLmzQrgqQaSJtyjFJWoEYu8dDLIqEgDWHqFINN08=; b=cv59JtLB1DMCmnpxy0QvDJStxO8ZvCXtCfCY4OCgVkzrBXQTcf8ujp/k2ONKQRYaPX wtke5nkEcRjpRVA0Aa/CoVsiD7WaUgQMRCXsn49xDzBfk+GM3NStDzNP9VCTuFpwzzaq unjaa+Ag+9+bZwk595FWb+MVNMylT1Zm4M5bqwaVDD+12GgQuIRH8993Ny3gFJ5MdSfy 5LHu1KGgF7DOtyUzAgrCutpnhb1csg88pJr2wgEtQmFM4mZkqmRGgnv6RfhccH5x1wic 3YBj6Aw9qVpCNcGKB2/cD35dJRTpJnAe0EOdD0feeNkfI40MElsFceNS3cSS0six95uS bf7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MXAnLmzQrgqQaSJtyjFJWoEYu8dDLIqEgDWHqFINN08=; b=Hj1JUULjsXuGrb2A6o//kXSs3BpPHsITBnmbw2Xt4egRnMYoxzh/qK1t0IuT2VIlwO VurwhEbGvymTfnMUBA0uCGAWrp8myaGmPAKe5UPSBa4N9HVqBJW7Wz5/hItyXx6HpSUf IAzD0qZe9oQqs75rfY/8IvGS6iyF2CVmXCM1onQju1hSbCqiVI185Fkqgq79PM1rScB+ qsur2srVT1PZkD0eunmZy3mNq8QKQi9dpttbiAW7+JWaBee1dQ256N+EVq0R50tf/fd9 3/6t+iLM54ynHXKqJkzsrBjFupkP6ZJQSqk+YU3Wf9kDe/11j1/nCnXlWIKQ0E45Dn8t vG0g== X-Gm-Message-State: AOAM531w3PjZWXg3CgDU7rCR8orKl+B8oWKCIWwegiYY8iYXkIq5zDeC yLMBcTXJbfPWi5tIASgyfxm7rg== X-Google-Smtp-Source: ABdhPJzb9pI/bDL6XkMTlf8Z6N07rnuBuKsU8LO2ruGUS0CBYqbWdTzI3s4eD78oq8NcuY2+KRas2Q== X-Received: by 2002:a5d:574a:0:b0:20d:70c:3aa8 with SMTP id q10-20020a5d574a000000b0020d070c3aa8mr23475115wrw.255.1653406091891; Tue, 24 May 2022 08:28:11 -0700 (PDT) Received: from xps-9300.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id k24-20020a05600c1c9800b003974027722csm2703693wms.47.2022.05.24.08.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 08:28:11 -0700 (PDT) From: Alexandre Bailon To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, Tinghan Shen , Ben Tseng , Alexandre Bailon Subject: [PATCH v7 6/6] arm64: dts: mt8195: Add thermal zone Date: Tue, 24 May 2022 17:25:53 +0200 Message-Id: <20220524152552.246193-7-abailon@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220524152552.246193-1-abailon@baylibre.com> References: <20220524152552.246193-1-abailon@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Tinghan Shen This adds the thermal zone for the mt8195. Signed-off-by: Tinghan Shen Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 104 +++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 51443e83d906..8421cf35ae03 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include =20 / { @@ -812,6 +813,21 @@ spi0: spi@1100a000 { status =3D "disabled"; }; =20 + lvts: lvts@1100b000 { + compatible =3D "mediatek,mt8195-lvts"; + #thermal-sensor-cells =3D <1>; + reg =3D <0 0x1100b000 0 0x1000>, + <0 0x11278000 0 0x1000>; + interrupts =3D , + ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + resets =3D <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>, + <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + + nvmem-cells =3D <&lvts_e_data1 &lvts_e_data2>; + nvmem-cell-names =3D "e_data1","e_data2"; + }; + spi1: spi@11010000 { compatible =3D "mediatek,mt8195-spi", "mediatek,mt6765-spi"; @@ -1616,4 +1632,92 @@ vencsys_core1: clock-controller@1b000000 { #clock-cells =3D <1>; }; }; + + thermal_zones: thermal-zones { + cpu-big1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 0>; + }; + cpu-big2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 1>; + }; + cpu-big3-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 2>; + }; + cpu-big4-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 3>; + }; + cpu-little1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 4>; + }; + cpu-little2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 5>; + }; + cpu-little3-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 6>; + }; + cpu-little4-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 7>; + }; + vpu1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 8>; + }; + vpu2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 9>; + }; + gpu1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 10>; + }; + gpu2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 11>; + }; + vdec-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 12>; + }; + img-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 13>; + }; + infra-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 14>; + }; + cam1-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 15>; + }; + cam2-thermal { + polling-delay =3D <0>; /* milliseconds */ + polling-delay-passive =3D <0>; /* milliseconds */ + thermal-sensors =3D <&lvts 16>; + }; + }; }; --=20 2.35.1