From nobody Mon May 6 18:00:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FCB4C433FE for ; Mon, 23 May 2022 18:18:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244604AbiEWSRL (ORCPT ); Mon, 23 May 2022 14:17:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244027AbiEWR5a (ORCPT ); Mon, 23 May 2022 13:57:30 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5F47CC5D8D; Mon, 23 May 2022 10:43:09 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,246,1647270000"; d="scan'208";a="121975207" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 24 May 2022 02:42:55 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 15594400F2AD; Tue, 24 May 2022 02:42:48 +0900 (JST) From: Lad Prabhakar To: Marc Zyngier , Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Linus Walleij , Bartosz Golaszewski , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Andy Gross , Philipp Zabel , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Prabhakar , linux-renesas-soc@vger.kernel.org, Phil Edworthy , Biju Das , Lad Prabhakar Subject: [PATCH v5 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller Date: Mon, 23 May 2022 18:42:34 +0100 Message-Id: <20220523174238.28942-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220523174238.28942-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220523174238.28942-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add DT bindings for the Renesas RZ/G2L Interrupt Controller. Signed-off-by: Lad Prabhakar Reviewed-by: Rob Herring Reviewed-by: Geert Uytterhoeven --- .../renesas,rzg2l-irqc.yaml | 133 ++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= renesas,rzg2l-irqc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas= ,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/r= enesas,rzg2l-irqc.yaml new file mode 100644 index 000000000000..ffbb4ab4d9a7 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-= irqc.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc= .yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55) + +maintainers: + - Lad Prabhakar + - Geert Uytterhoeven + +description: | + IA55 performs various interrupt controls including synchronization for t= he external + interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in p= eripheral + interrupts output by each IP. And it notifies the interrupt to the GIC + - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI inte= rrupts + - GPIO pins used as external interrupt input pins, mapped to 32 GIC SP= I interrupts + - NMI edge select (NMI is not treated as NMI exception and supports fa= ll edge and + stand-up edge detection interrupts) + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-irqc # RZ/G2L + - const: renesas,rzg2l-irqc + + '#interrupt-cells': + description: The first cell should contain external interrupt number (= IRQ0-7) and the + second cell is used to specify the flag. + const: 2 + + '#address-cells': + const: 0 + + interrupt-controller: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 41 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: clk + - const: pclk + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - '#interrupt-cells' + - '#address-cells' + - interrupt-controller + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + + irqc: interrupt-controller@110a0000 { + compatible =3D "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; + reg =3D <0x110a0000 0x10000>; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&cpg CPG_MOD R9A07G044_IA55_CLK>, + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; + clock-names =3D "clk", "pclk"; + power-domains =3D <&cpg>; + resets =3D <&cpg R9A07G044_IA55_RESETN>; + }; --=20 2.25.1 From nobody Mon May 6 18:00:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE4DFC4321E for ; Mon, 23 May 2022 18:18:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244565AbiEWSQ6 (ORCPT ); Mon, 23 May 2022 14:16:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244194AbiEWR55 (ORCPT ); Mon, 23 May 2022 13:57:57 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B781DC5E6D; Mon, 23 May 2022 10:43:14 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,246,1647270000"; d="scan'208";a="121975212" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 24 May 2022 02:43:01 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id A583E400E8FD; Tue, 24 May 2022 02:42:55 +0900 (JST) From: Lad Prabhakar To: Marc Zyngier , Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Linus Walleij , Bartosz Golaszewski , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Andy Gross , Philipp Zabel , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Prabhakar , linux-renesas-soc@vger.kernel.org, Phil Edworthy , Biju Das , Lad Prabhakar Subject: [PATCH v5 2/5] irqchip: Add RZ/G2L IA55 Interrupt Controller driver Date: Mon, 23 May 2022 18:42:35 +0100 Message-Id: <20220523174238.28942-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220523174238.28942-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220523174238.28942-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a driver for the Renesas RZ/G2L Interrupt Controller. This supports external pins being used as interrupts. It supports one line for NMI, 8 external pins and 32 GPIO pins (out of 123) to be used as IRQ lines. Signed-off-by: Lad Prabhakar --- drivers/irqchip/Kconfig | 8 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-renesas-rzg2l.c | 425 ++++++++++++++++++++++++++++ 3 files changed, 434 insertions(+) create mode 100644 drivers/irqchip/irq-renesas-rzg2l.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 15edb9a6fcae..f3d071422f3b 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -242,6 +242,14 @@ config RENESAS_RZA1_IRQC Enable support for the Renesas RZ/A1 Interrupt Controller, to use up to 8 external interrupts with configurable sense select. =20 +config RENESAS_RZG2L_IRQC + bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN_HIERARCHY + help + Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Control= ler + for external devices. + config SL28CPLD_INTC bool "Kontron sl28cpld IRQ controller" depends on MFD_SL28CPLD=3Dy || COMPILE_TEST diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 160a1d8ceaa9..eaa56eec2b23 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_RDA_INTC) +=3D irq-rda-intc.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) +=3D irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) +=3D irq-renesas-irqc.o obj-$(CONFIG_RENESAS_RZA1_IRQC) +=3D irq-renesas-rza1.o +obj-$(CONFIG_RENESAS_RZG2L_IRQC) +=3D irq-renesas-rzg2l.o obj-$(CONFIG_VERSATILE_FPGA_IRQ) +=3D irq-versatile-fpga.o obj-$(CONFIG_ARCH_NSPIRE) +=3D irq-zevio.o obj-$(CONFIG_ARCH_VT8500) +=3D irq-vt8500.o diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c new file mode 100644 index 000000000000..a846c6ee11d7 --- /dev/null +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/G2L IRQC Driver + * + * Copyright (C) 2022 Renesas Electronics Corporation. + * + * Author: Lad Prabhakar + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IRQC_IRQ_START 1 +#define IRQC_IRQ_COUNT 8 +#define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) +#define IRQC_TINT_COUNT 32 +#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) + +#define ISCR 0x10 +#define IITSR 0x14 +#define TSCR 0x20 +#define TITSR0 0x24 +#define TITSR1 0x28 +#define TITSR0_MAX_INT 16 +#define TITSEL_WIDTH 0x2 +#define TSSR(n) (0x30 + ((n) * 4)) +#define TIEN BIT(7) +#define TSSEL_SHIFT(n) (8 * (n)) +#define TSSEL_MASK GENMASK(7, 0) +#define IRQ_MASK 0x3 + +#define TSSR_OFFSET(n) ((n) % 4) +#define TSSR_INDEX(n) ((n) / 4) + +#define TITSR_TITSEL_EDGE_RISING 0 +#define TITSR_TITSEL_EDGE_FALLING 1 +#define TITSR_TITSEL_LEVEL_HIGH 2 +#define TITSR_TITSEL_LEVEL_LOW 3 + +#define IITSR_IITSEL(n, sense) ((sense) << ((n) * 2)) +#define IITSR_IITSEL_LEVEL_LOW 0 +#define IITSR_IITSEL_EDGE_FALLING 1 +#define IITSR_IITSEL_EDGE_RISING 2 +#define IITSR_IITSEL_EDGE_BOTH 3 +#define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) + +#define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) +#define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) + +struct rzg2l_irqc_priv { + void __iomem *base; + struct of_phandle_args map[IRQC_NUM_IRQ]; + raw_spinlock_t lock; +}; + +struct rzg2l_irqc_chip_data { + int tint; +}; + +static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) +{ + return data->domain->host_data; +} + +static void rzg2l_irq_eoi(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d) - IRQC_IRQ_START; + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + u32 bit =3D BIT(hw_irq); + u32 reg; + + reg =3D readl_relaxed(priv->base + ISCR); + if (reg & bit) + writel_relaxed(reg & ~bit, priv->base + ISCR); +} + +static void rzg2l_tint_eoi(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d) - IRQC_TINT_START; + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + u32 bit =3D BIT(hw_irq); + u32 reg; + + reg =3D readl_relaxed(priv->base + TSCR); + if (reg & bit) + writel_relaxed(reg & ~bit, priv->base + TSCR); +} + +static void rzg2l_irqc_eoi(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hw_irq =3D irqd_to_hwirq(d); + + raw_spin_lock(&priv->lock); + if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) + rzg2l_irq_eoi(d); + else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + rzg2l_tint_eoi(d); + raw_spin_unlock(&priv->lock); + irq_chip_eoi_parent(d); +} + +static void rzg2l_irqc_irq_disable(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + + if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + u32 offset =3D hw_irq - IRQC_TINT_START; + u32 tssr_offset =3D TSSR_OFFSET(offset); + u8 tssr_index =3D TSSR_INDEX(offset); + u32 reg; + + raw_spin_lock(&priv->lock); + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + reg &=3D ~(TSSEL_MASK << tssr_offset); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + raw_spin_unlock(&priv->lock); + } + irq_chip_disable_parent(d); +} + +static void rzg2l_irqc_irq_enable(struct irq_data *d) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + + if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned long chip_data =3D *(unsigned long *)d->chip_data; + u32 offset =3D hw_irq - IRQC_TINT_START; + u32 tssr_offset =3D TSSR_OFFSET(offset); + u8 tssr_index =3D TSSR_INDEX(offset); + u32 reg; + + raw_spin_lock(&priv->lock); + reg =3D readl_relaxed(priv->base + TSSR(tssr_index)); + reg |=3D (TIEN | chip_data) << TSSEL_SHIFT(tssr_offset); + writel_relaxed(reg, priv->base + TSSR(tssr_index)); + raw_spin_unlock(&priv->lock); + } + irq_chip_enable_parent(d); +} + +static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d) - IRQC_IRQ_START; + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + u16 sense, tmp; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_LEVEL_LOW: + sense =3D IITSR_IITSEL_LEVEL_LOW; + break; + + case IRQ_TYPE_EDGE_FALLING: + sense =3D IITSR_IITSEL_EDGE_FALLING; + break; + + case IRQ_TYPE_EDGE_RISING: + sense =3D IITSR_IITSEL_EDGE_RISING; + break; + + case IRQ_TYPE_EDGE_BOTH: + sense =3D IITSR_IITSEL_EDGE_BOTH; + break; + + default: + return -EINVAL; + } + + raw_spin_lock(&priv->lock); + tmp =3D readl_relaxed(priv->base + IITSR); + tmp &=3D ~IITSR_IITSEL_MASK(hw_irq); + tmp |=3D IITSR_IITSEL(hw_irq, sense); + writel_relaxed(tmp, priv->base + IITSR); + raw_spin_unlock(&priv->lock); + + return 0; +} + +static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hwirq =3D irqd_to_hwirq(d); + u32 titseln =3D hwirq - IRQC_TINT_START; + u32 offset; + u8 sense; + u32 reg; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + sense =3D TITSR_TITSEL_EDGE_RISING; + break; + + case IRQ_TYPE_EDGE_FALLING: + sense =3D TITSR_TITSEL_EDGE_FALLING; + break; + + default: + return -EINVAL; + } + + offset =3D TITSR0; + if (titseln >=3D TITSR0_MAX_INT) { + titseln -=3D TITSR0_MAX_INT; + offset =3D TITSR1; + } + + raw_spin_lock(&priv->lock); + reg =3D readl_relaxed(priv->base + offset); + reg &=3D ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); + reg |=3D sense << (titseln * TITSEL_WIDTH); + writel_relaxed(reg, priv->base + offset); + raw_spin_unlock(&priv->lock); + + return 0; +} + +static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) +{ + unsigned int hw_irq =3D irqd_to_hwirq(d); + int ret =3D -EINVAL; + + if (hw_irq >=3D IRQC_IRQ_START && hw_irq <=3D IRQC_IRQ_COUNT) + ret =3D rzg2l_irq_set_type(d, type); + else if (hw_irq >=3D IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + ret =3D rzg2l_tint_set_edge(d, type); + if (ret) + return ret; + + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); +} + +static const struct irq_chip irqc_chip =3D { + .name =3D "rzg2l-irqc", + .irq_eoi =3D rzg2l_irqc_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D rzg2l_irqc_irq_disable, + .irq_enable =3D rzg2l_irqc_irq_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_set_type, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + +static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + struct rzg2l_irqc_priv *priv =3D domain->host_data; + unsigned long *chip_data =3D NULL; + struct irq_fwspec spec; + irq_hw_number_t hwirq; + int tint =3D -EINVAL; + unsigned int type; + unsigned int i; + int ret; + + ret =3D irq_domain_translate_twocell(domain, arg, &hwirq, &type); + if (ret) + return ret; + + /* + * For TINT interrupts ie where pinctrl driver is child of irqc domain + * the hwirq and TINT are encoded in fwspec->param[0]. + * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT + * from 16-31 bits. TINT from the pinctrl driver needs to be programmed + * in IRQC registers to enable a given gpio pin as interrupt. + */ + if (hwirq > IRQC_IRQ_COUNT) { + tint =3D TINT_EXTRACT_GPIOINT(hwirq); + hwirq =3D TINT_EXTRACT_HWIRQ(hwirq); + + if (hwirq < IRQC_TINT_START) + return -EINVAL; + } + + if (hwirq > (IRQC_NUM_IRQ - 1)) + return -EINVAL; + + chip_data =3D kzalloc(sizeof(*chip_data), GFP_KERNEL); + if (!chip_data) + return -ENOMEM; + *chip_data =3D tint; + + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip, + chip_data); + if (ret) { + kfree(chip_data); + return ret; + } + + spec.fwnode =3D domain->parent->fwnode; + spec.param_count =3D priv->map[hwirq].args_count; + for (i =3D 0; i < spec.param_count; i++) + spec.param[i] =3D priv->map[hwirq].args[i]; + + ret =3D irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &spec); + if (ret) + kfree(chip_data); + + return ret; +} + +static void rzg2l_irqc_domain_free(struct irq_domain *domain, unsigned int= virq, + unsigned int nr_irqs) +{ + struct irq_data *d; + + d =3D irq_domain_get_irq_data(domain, virq); + if (d) + kfree(d->chip_data); + + irq_domain_free_irqs_common(domain, virq, nr_irqs); +} + +static const struct irq_domain_ops rzg2l_irqc_domain_ops =3D { + .alloc =3D rzg2l_irqc_alloc, + .free =3D rzg2l_irqc_domain_free, + .translate =3D irq_domain_translate_twocell, +}; + +static int rzg2l_irqc_parse_map(struct rzg2l_irqc_priv *priv, + struct device_node *np) +{ + unsigned int i; + int ret; + + for (i =3D 0; i < IRQC_NUM_IRQ; i++) { + ret =3D of_irq_parse_one(np, i, &priv->map[i]); + if (ret) + return ret; + } + + return 0; +} + +static int rzg2l_irqc_init(struct device_node *node, struct device_node *p= arent) +{ + struct irq_domain *irq_domain, *parent_domain; + struct platform_device *pdev; + struct reset_control *resetn; + struct rzg2l_irqc_priv *priv; + int ret; + + pdev =3D of_find_device_by_node(node); + if (!pdev) + return -ENODEV; + + parent_domain =3D irq_find_host(parent); + if (!parent_domain) { + dev_err(&pdev->dev, "cannot find parent domain\n"); + return -ENODEV; + } + + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base =3D devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret =3D rzg2l_irqc_parse_map(priv, node); + if (ret) { + dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); + return ret; + } + + resetn =3D devm_reset_control_get_exclusive_by_index(&pdev->dev, 0); + if (IS_ERR(resetn)) + return IS_ERR(resetn); + + ret =3D reset_control_deassert(resetn); + if (ret) { + dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret); + return ret; + } + + pm_runtime_enable(&pdev->dev); + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret < 0) { + dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); + goto pm_disable; + } + + raw_spin_lock_init(&priv->lock); + + irq_domain =3D irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, + node, &rzg2l_irqc_domain_ops, + priv); + if (!irq_domain) { + dev_err(&pdev->dev, "failed to add irq domain\n"); + ret =3D -ENOMEM; + goto pm_put; + } + + return 0; + +pm_put: + pm_runtime_put(&pdev->dev); +pm_disable: + pm_runtime_disable(&pdev->dev); + reset_control_assert(resetn); + return ret; +} + +IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) +IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init) +IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) +MODULE_AUTHOR("Lad Prabhakar "); +MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Mon May 6 18:00:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB85DC433FE for ; Mon, 23 May 2022 18:18:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244391AbiEWSQg (ORCPT ); Mon, 23 May 2022 14:16:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244349AbiEWR6E (ORCPT ); Mon, 23 May 2022 13:58:04 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D2872C6E62; Mon, 23 May 2022 10:43:18 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,246,1647270000"; d="scan'208";a="120623471" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 24 May 2022 02:43:08 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 42613400E8FF; Tue, 24 May 2022 02:43:02 +0900 (JST) From: Lad Prabhakar To: Marc Zyngier , Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Linus Walleij , Bartosz Golaszewski , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Andy Gross , Philipp Zabel , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Prabhakar , linux-renesas-soc@vger.kernel.org, Phil Edworthy , Biju Das , Lad Prabhakar Subject: [PATCH v5 3/5] gpio: gpiolib: Allow free() callback to be overridden Date: Mon, 23 May 2022 18:42:36 +0100 Message-Id: <20220523174238.28942-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220523174238.28942-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220523174238.28942-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Allow free() callback to be overridden from irq_domain_ops for hierarchical chips. This allows drivers to free up resources which are allocated during child_to_parent_hwirq()/populate_parent_alloc_arg() callbacks. On Renesas RZ/G2L platform a bitmap is maintained for TINT slots, a slot is allocated in child_to_parent_hwirq() callback which is freed up in free callback hence this override. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/gpio/gpiolib.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 690035124faa..8fcb9d23fea5 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1187,15 +1187,18 @@ static void gpiochip_hierarchy_setup_domain_ops(str= uct irq_domain_ops *ops) ops->activate =3D gpiochip_irq_domain_activate; ops->deactivate =3D gpiochip_irq_domain_deactivate; ops->alloc =3D gpiochip_hierarchy_irq_domain_alloc; - ops->free =3D irq_domain_free_irqs_common; =20 /* - * We only allow overriding the translate() function for + * We only allow overriding the translate() and free() functions for * hierarchical chips, and this should only be done if the user - * really need something other than 1:1 translation. + * really need something other than 1:1 translation for translate() + * callback and free if user wants to free up any resources which + * were allocated during callbacks, for example populate_parent_alloc_arg. */ if (!ops->translate) ops->translate =3D gpiochip_hierarchy_irq_domain_translate; + if (!ops->free) + ops->free =3D irq_domain_free_irqs_common; } =20 static int gpiochip_hierarchy_add_domain(struct gpio_chip *gc) --=20 2.25.1 From nobody Mon May 6 18:00:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1BF7C433F5 for ; Mon, 23 May 2022 18:18:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244216AbiEWSQS (ORCPT ); Mon, 23 May 2022 14:16:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244310AbiEWR6D (ORCPT ); Mon, 23 May 2022 13:58:03 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4E6E8C6E6C; Mon, 23 May 2022 10:43:15 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,246,1647270000"; d="scan'208";a="121975224" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 24 May 2022 02:43:14 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id D2F23400E8E8; Tue, 24 May 2022 02:43:08 +0900 (JST) From: Lad Prabhakar To: Marc Zyngier , Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Linus Walleij , Bartosz Golaszewski , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Andy Gross , Philipp Zabel , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Prabhakar , linux-renesas-soc@vger.kernel.org, Phil Edworthy , Biju Das , Lad Prabhakar Subject: [PATCH v5 4/5] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties to handle GPIO IRQ Date: Mon, 23 May 2022 18:42:37 +0100 Message-Id: <20220523174238.28942-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220523174238.28942-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220523174238.28942-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Document the required properties to handle GPIO IRQ. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Reviewed-by: Rob Herring --- .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index 52df1b146174..997b74639112 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -47,6 +47,17 @@ properties: gpio-ranges: maxItems: 1 =20 + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed usin= g the + RZG2L_GPIO() helper macro in a= nd the + second cell is used to specify the flag. + E.g. "interrupts =3D ;" if = P43_0 is + being used as an interrupt. + clocks: maxItems: 1 =20 @@ -110,6 +121,8 @@ required: - gpio-controller - '#gpio-cells' - gpio-ranges + - interrupt-controller + - '#interrupt-cells' - clocks - power-domains - resets @@ -126,6 +139,8 @@ examples: gpio-controller; #gpio-cells =3D <2>; gpio-ranges =3D <&pinctrl 0 0 392>; + interrupt-controller; + #interrupt-cells =3D <2>; clocks =3D <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; resets =3D <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, --=20 2.25.1 From nobody Mon May 6 18:00:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90EBCC433EF for ; Mon, 23 May 2022 18:18:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244136AbiEWSQJ (ORCPT ); Mon, 23 May 2022 14:16:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244605AbiEWR6K (ORCPT ); Mon, 23 May 2022 13:58:10 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 36C11C9663; Mon, 23 May 2022 10:43:26 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.91,246,1647270000"; d="scan'208";a="120623478" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 24 May 2022 02:43:21 +0900 Received: from localhost.localdomain (unknown [10.226.36.204]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 6CAB2400E8E8; Tue, 24 May 2022 02:43:15 +0900 (JST) From: Lad Prabhakar To: Marc Zyngier , Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Linus Walleij , Bartosz Golaszewski , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Andy Gross , Philipp Zabel , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Prabhakar , linux-renesas-soc@vger.kernel.org, Phil Edworthy , Biju Das , Lad Prabhakar Subject: [PATCH v5 5/5] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt Date: Mon, 23 May 2022 18:42:38 +0100 Message-Id: <20220523174238.28942-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220523174238.28942-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220523174238.28942-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add IRQ domain to RZ/G2L pinctrl driver to handle GPIO interrupt. GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be used as IRQ lines at a given time. Selection of pins as IRQ lines is handled by IA55 (which is the IRQC block) which sits in between the GPIO and GIC. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 236 ++++++++++++++++++++++++ 1 file changed, 236 insertions(+) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index a48cac55152c..0793b5718f68 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -9,8 +9,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -89,6 +91,7 @@ #define PIN(n) (0x0800 + 0x10 + (n)) #define IOLH(n) (0x1000 + (n) * 8) #define IEN(n) (0x1800 + (n) * 8) +#define ISEL(n) (0x2c80 + (n) * 8) #define PWPR (0x3014) #define SD_CH(n) (0x3000 + (n) * 4) #define QSPI (0x3008) @@ -112,6 +115,10 @@ #define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10) #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) =20 +#define RZG2L_TINT_MAX_INTERRUPT 32 +#define RZG2L_TINT_IRQ_START_INDEX 9 +#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) + struct rzg2l_dedicated_configs { const char *name; u32 config; @@ -137,6 +144,9 @@ struct rzg2l_pinctrl { =20 struct gpio_chip gpio_chip; struct pinctrl_gpio_range gpio_range; + DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); + spinlock_t bitmap_lock; + unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; =20 spinlock_t lock; }; @@ -883,8 +893,14 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, unsi= gned int offset) =20 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) { + unsigned int virq; + pinctrl_gpio_free(chip->base + offset); =20 + virq =3D irq_find_mapping(chip->irq.domain, offset); + if (virq) + irq_dispose_mapping(virq); + /* * Set the GPIO as an input to ensure that the next GPIO request won't * drive the GPIO pin as an output. @@ -1104,14 +1120,224 @@ static struct { } }; =20 +static int rzg2l_gpio_get_gpioint(unsigned int virq) +{ + unsigned int gpioint; + unsigned int i; + u32 port, bit; + + port =3D virq / 8; + bit =3D virq % 8; + + if (port >=3D ARRAY_SIZE(rzg2l_gpio_configs) || + bit >=3D RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + return -EINVAL; + + gpioint =3D bit; + for (i =3D 0; i < port; i++) + gpioint +=3D RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]); + + return gpioint; +} + +static void rzg2l_gpio_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rzg2l_pinctrl *pctrl =3D container_of(gc, struct rzg2l_pinctrl, gp= io_chip); + unsigned int hwirq =3D irqd_to_hwirq(d); + unsigned long flags; + void __iomem *addr; + u32 port; + u8 bit; + + port =3D RZG2L_PIN_ID_TO_PORT(hwirq); + bit =3D RZG2L_PIN_ID_TO_PIN(hwirq); + + addr =3D pctrl->base + ISEL(port); + if (bit >=3D 4) { + bit -=3D 4; + addr +=3D 4; + } + + spin_lock_irqsave(&pctrl->lock, flags); + writel(readl(addr) & ~BIT(bit * 8), addr); + spin_unlock_irqrestore(&pctrl->lock, flags); + + gpiochip_disable_irq(gc, hwirq); + irq_chip_disable_parent(d); +} + +static void rzg2l_gpio_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rzg2l_pinctrl *pctrl =3D container_of(gc, struct rzg2l_pinctrl, gp= io_chip); + unsigned int hwirq =3D irqd_to_hwirq(d); + unsigned long flags; + void __iomem *addr; + u32 port; + u8 bit; + + gpiochip_enable_irq(gc, hwirq); + + port =3D RZG2L_PIN_ID_TO_PORT(hwirq); + bit =3D RZG2L_PIN_ID_TO_PIN(hwirq); + + addr =3D pctrl->base + ISEL(port); + if (bit >=3D 4) { + bit -=3D 4; + addr +=3D 4; + } + + spin_lock_irqsave(&pctrl->lock, flags); + writel(readl(addr) | BIT(bit * 8), addr); + spin_unlock_irqrestore(&pctrl->lock, flags); + + irq_chip_enable_parent(d); +} + +static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + return irq_chip_set_type_parent(d, type); +} + +static void rzg2l_gpio_irqc_eoi(struct irq_data *d) +{ + irq_chip_eoi_parent(d); +} + +static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_fi= le *p) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(data); + + seq_printf(p, dev_name(gc->parent)); +} + +static const struct irq_chip rzg2l_gpio_irqchip =3D { + .name =3D "rzg2l-gpio", + .irq_disable =3D rzg2l_gpio_irq_disable, + .irq_enable =3D rzg2l_gpio_irq_enable, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_set_type =3D rzg2l_gpio_irq_set_type, + .irq_eoi =3D rzg2l_gpio_irqc_eoi, + .irq_print_chip =3D rzg2l_gpio_irq_print_chip, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + struct rzg2l_pinctrl *pctrl =3D gpiochip_get_data(gc); + unsigned long flags; + int gpioint, irq; + + gpioint =3D rzg2l_gpio_get_gpioint(child); + if (gpioint < 0) + return gpioint; + + spin_lock_irqsave(&pctrl->bitmap_lock, flags); + irq =3D bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUP= T, get_order(1)); + spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); + if (irq < 0) + return -ENOSPC; + pctrl->hwirq[irq] =3D child; + irq +=3D RZG2L_TINT_IRQ_START_INDEX; + + /* All these interrupts are level high in the CPU */ + *parent_type =3D IRQ_TYPE_LEVEL_HIGH; + *parent =3D RZG2L_PACK_HWIRQ(gpioint, irq); + return 0; +} + +static void *rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, + unsigned int parent_hwirq, + unsigned int parent_type) +{ + struct irq_fwspec *fwspec; + + fwspec =3D kzalloc(sizeof(*fwspec), GFP_KERNEL); + if (!fwspec) + return NULL; + + fwspec->fwnode =3D chip->irq.parent_domain->fwnode; + fwspec->param_count =3D 2; + fwspec->param[0] =3D parent_hwirq; + fwspec->param[1] =3D parent_type; + + return fwspec; +} + +static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned= int virq, + unsigned int nr_irqs) +{ + struct irq_data *d; + + d =3D irq_domain_get_irq_data(domain, virq); + if (d) { + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct rzg2l_pinctrl *pctrl =3D container_of(gc, struct rzg2l_pinctrl, g= pio_chip); + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); + unsigned long flags; + unsigned int i; + + for (i =3D 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { + if (pctrl->hwirq[i] =3D=3D hwirq) { + spin_lock_irqsave(&pctrl->bitmap_lock, flags); + bitmap_release_region(pctrl->tint_slot, i, get_order(1)); + spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); + pctrl->hwirq[i] =3D 0; + break; + } + } + } + irq_domain_free_irqs_common(domain, virq, nr_irqs); +} + +static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct rzg2l_pinctrl *pctrl =3D gpiochip_get_data(gc); + struct gpio_chip *chip =3D &pctrl->gpio_chip; + unsigned int offset; + + /* Forbid unused lines to be mapped as IRQs */ + for (offset =3D 0; offset < chip->ngpio; offset++) { + u32 port, bit; + + port =3D offset / 8; + bit =3D offset % 8; + + if (port >=3D ARRAY_SIZE(rzg2l_gpio_configs) || + bit >=3D RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + clear_bit(offset, valid_mask); + } +} + static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) { struct device_node *np =3D pctrl->dev->of_node; struct gpio_chip *chip =3D &pctrl->gpio_chip; const char *name =3D dev_name(pctrl->dev); + struct irq_domain *parent_domain; struct of_phandle_args of_args; + struct device_node *parent_np; + struct gpio_irq_chip *girq; int ret; =20 + parent_np =3D of_irq_find_parent(np); + if (!parent_np) + return -ENXIO; + + parent_domain =3D irq_find_host(parent_np); + of_node_put(parent_np); + if (!parent_domain) + return -EPROBE_DEFER; + ret =3D of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_arg= s); if (ret) { dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); @@ -1138,6 +1364,15 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl = *pctrl) chip->base =3D -1; chip->ngpio =3D of_args.args[2]; =20 + girq =3D &chip->irq; + gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); + girq->fwnode =3D of_node_to_fwnode(np); + girq->parent_domain =3D parent_domain; + girq->child_to_parent_hwirq =3D rzg2l_gpio_child_to_parent_hwirq; + girq->populate_parent_alloc_arg =3D rzg2l_gpio_populate_parent_fwspec; + girq->child_irq_domain_ops.free =3D rzg2l_gpio_irq_domain_free; + girq->init_valid_mask =3D rzg2l_init_irq_valid_mask; + pctrl->gpio_range.id =3D 0; pctrl->gpio_range.pin_base =3D 0; pctrl->gpio_range.base =3D 0; @@ -1253,6 +1488,7 @@ static int rzg2l_pinctrl_probe(struct platform_device= *pdev) } =20 spin_lock_init(&pctrl->lock); + spin_lock_init(&pctrl->bitmap_lock); =20 platform_set_drvdata(pdev, pctrl); =20 --=20 2.25.1