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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:11 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Markus Schneider-Pargmann , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 01/21] dt-bindings: mediatek,dpi: Add DPINTF compatible Date: Mon, 23 May 2022 12:47:34 +0200 Message-Id: <20220523104758.29531-2-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann DPINTF is similar to DPI but does not have the exact same feature set or register layouts. DPINTF is the sink of the display pipeline that is connected to the DisplayPort controller and encoder unit. It takes the same clocks as DPI. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- .../bindings/display/mediatek/mediatek,dpi.yaml | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp= i.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.ya= ml index dd2896a40ff0..6d9f6c11806e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -4,16 +4,16 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: mediatek DPI Controller Device Tree Bindings +title: mediatek DPI/DPINTF Controller =20 maintainers: - CK Hu - Jitao shi =20 description: | - The Mediatek DPI function block is a sink of the display subsystem and - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel - output bus. + The Mediatek DPI and DPINTF function blocks are a sink of the display + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data= on a + parallel output bus. =20 properties: compatible: @@ -23,6 +23,7 @@ properties: - mediatek,mt8173-dpi - mediatek,mt8183-dpi - mediatek,mt8192-dpi + - mediatek,mt8195-dpintf =20 reg: maxItems: 1 @@ -35,12 +36,14 @@ properties: - description: Pixel Clock - description: Engine Clock - description: DPI PLL + - description: Optional CK CG Clock =20 clock-names: items: - const: pixel - const: engine - const: pll + - const: ck_cg =20 pinctrl-0: true pinctrl-1: true @@ -54,7 +57,7 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Output port node. This port should be connected to the input port of= an - attached HDMI or LVDS encoder chip. + attached HDMI, LVDS or DisplayPort encoder chip. =20 required: - compatible --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDA63C433FE for ; Mon, 23 May 2022 10:50:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234391AbiEWKub (ORCPT ); Mon, 23 May 2022 06:50:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234341AbiEWKuV (ORCPT ); Mon, 23 May 2022 06:50:21 -0400 Received: from mail-wm1-x343.google.com (mail-wm1-x343.google.com [IPv6:2a00:1450:4864:20::343]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8D0F4CD5A for ; Mon, 23 May 2022 03:50:19 -0700 (PDT) Received: by mail-wm1-x343.google.com with SMTP id i82-20020a1c3b55000000b00397391910d5so5094766wma.1 for ; Mon, 23 May 2022 03:50:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RBdwv8C2zWSCXm9kFqdZLTYTeRupN3jSjblct2gox8s=; b=Z/xyqPorLXxjtX45nJY9HoVzJk17XbNfLYrKQzUC5oUtkKMtSoV+kWJ/W9h2UwUdlN 1izRYQ+g5TLX3hghia4MPgYalf8vdyabNOS2DaGlsAhoEGt/s+/KnelQ0vZbZtihbBMg 21Pyw395K/H6hYe1NjG4mAI/mc+ABytCuV7klYgDvq9vZJ7hsPVtmwjWKYUbF/bp/EcC Oilliy3/kq69ohuRdHDHt1sN0WqllfmeBK0PA3bmOt33PYByl5DZkyGxt3aG8JeVrdma MXLeIGVJyxZJTBpjD3ztKpUSnkvsiwIvClmunyObwRYCXJLItn7H8y/fT/NKL+YLfjaE ppkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RBdwv8C2zWSCXm9kFqdZLTYTeRupN3jSjblct2gox8s=; b=nBD0fnxXGq4WamY0exa7Q1KFhc4x06Ll9HXYl9RkxpaXmNeC7L1B2Lk6kPs0Gdx2A/ 1mmMOfxM5pP26FXELw30NX6r1WaFWXPo6fDmKz0f2X4WIbH8/rTvwjByc2IttgvHptkh xV/TjK3/fRflNyoukMhqzV/cnZrqBpGIRAA5jOJ0UbiQOH8aaj7FYajVjQmR9MaSatSY JGomvenEL/4CfBQ0YyVd66rmVXa2ADM5HXvGLThyTFYPgOOX/vMG7m/w8+RwUJ6o8mCn nNSDfi6b57QdFvqZotJQWT76oS8JpbDn0QfImZ05fNtmYsH1G/JJFAWXENXmjd4ENtwI MzAA== X-Gm-Message-State: AOAM531WfdpC0WC1myNpVwVUzVLRjVCqqIsn9GGGt+j8wBnnWm0y9JPt vFEJOWRJhAwuYBq/BHtiJHAxaQ== X-Google-Smtp-Source: ABdhPJxU86O9OrfPSwDpzF5vc+DzPzD1gUymNmku2eiSYHqSUNEzJviyarRmUCu72kW//QWtrovSTg== X-Received: by 2002:a05:600c:42d3:b0:397:47ae:188c with SMTP id j19-20020a05600c42d300b0039747ae188cmr6376412wme.150.1653303018361; Mon, 23 May 2022 03:50:18 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:18 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Markus Schneider-Pargmann , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 02/21] dt-bindings: mediatek,dp: Add Display Port binding Date: Mon, 23 May 2022 12:47:35 +0200 Message-Id: <20220523104758.29531-3-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann This controller is present on several mediatek hardware. Currently mt8195 and mt8395 have this controller without a functional difference, so only one compatible field is added. The controller can have two forms, as a normal display port and as an embedded display port. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- .../display/mediatek/mediatek,dp.yaml | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,dp.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp= .yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml new file mode 100644 index 000000000000..36ae0a6df299 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Port Controller + +maintainers: + - CK Hu + - Jitao shi + +description: | + Device tree bindings for the MediaTek (embedded) Display Port controller + present on some MediaTek SoCs. + +properties: + compatible: + enum: + - mediatek,mt8195-dp-tx + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: faxi clock + + clock-names: + items: + - const: faxi + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input endpoint of the controller, usually dp_intf + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the controller + + max-lanes: + maxItems: 1 + description: maximum number of lanes supported by the hardware + + max-linkrate: + maxItems: 1 + description: maximum link rate supported by the hardware + +required: + - compatible + - reg + - interrupts + - ports + - max-lanes + - max-linkrate + +additionalProperties: false + +examples: + - | + #include + #include + edp_tx: edp_tx@1c500000 { + compatible =3D "mediatek,mt8195-dp-tx"; + reg =3D <0 0x1c500000 0 0x8000>; + interrupts =3D ; + power-domains =3D <&spm MT8195_POWER_DOMAIN_EPD_TX>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edp_pin>; + max-lanes =3D /bits/ 8 <4>; + max-linkrate =3D /bits/ 8 <0x1e>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + edp_in: endpoint { + remote-endpoint =3D <&dp_intf0_out>; + }; + }; + port@1 { + reg =3D <1>; + edp_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; + }; --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17E21C433EF for ; Mon, 23 May 2022 10:50:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234397AbiEWKuh (ORCPT ); Mon, 23 May 2022 06:50:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234383AbiEWKu1 (ORCPT ); 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:24 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 03/21] drm/edid: Convert cea_sad helper struct to kernelDoc Date: Mon, 23 May 2022 12:47:36 +0200 Message-Id: <20220523104758.29531-4-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno --- include/drm/drm_edid.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 144c495b99c4..37c420423625 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -359,12 +359,18 @@ struct edid { =20 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) =20 -/* Short Audio Descriptor */ +/** + * struct cea_sad - Short Audio Descriptor. + * @format: See HDMI_AUDIO_CODING_TYPE_*. + * @channels: max number of channels - 1. + * @freq: See CEA_SAD_FREQ_*. + * @byte2: meaning depends on format. + */ struct cea_sad { u8 format; - u8 channels; /* max number of channels - 1 */ + u8 channels; u8 freq; - u8 byte2; /* meaning depends on format */ + u8 byte2; }; =20 struct drm_encoder; --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2917C4167B for ; Mon, 23 May 2022 10:50:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234345AbiEWKux (ORCPT ); Mon, 23 May 2022 06:50:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234393AbiEWKud (ORCPT ); Mon, 23 May 2022 06:50:33 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7ED634D272 for ; Mon, 23 May 2022 03:50:32 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id h5so19619757wrb.11 for ; Mon, 23 May 2022 03:50:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FDUYn8cSKi190xy1Yoj7AgQQXe/6NoP0U/SFF23PsOA=; b=qslf5RL0JGSs8SyIhe+TjKCebf6N8Zx7A/KkiHzfSvQQJ0dBo2BdV1LNUeKcZ3HdC1 bGDP7RCOTJPGKA/yxPuQMQlHQdGWtR+beYXyoVch08XmJA/0B8+MdY7GOt732kH5W/uK gdlKB62ds69Xx6ofbHaABlk3bVaRdGJYupebz/XREkj/+4FAn1NhJJCyF/dh90krSr9H B2/+VIV4I6psrQKH7Hlt3y4qG/J5RJUFbI5V/tHT7AZOw0jIwSQcGN3htwm8AfCMU09P Dbv+zgivZSQgDV6Q8WLNGJ4zOu+H8U9LRJldKifH6/IO4fVqrA663REGasLPNVm2VbRx kJ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FDUYn8cSKi190xy1Yoj7AgQQXe/6NoP0U/SFF23PsOA=; b=DS+DZCJHsYR7B2BQzrg/yvoG24u5Vz43KiDSS9AHhKT1JIXEdcXZK5Zu+RlCXYFbQY 0Jz8VdNKVzfLcnOOBBtRFn+D07TPH5sgaM0pmDgGCdtHeNaC77FGPVvJJAAVKe4jI3Fj fl+gJ3rZNCYv2n4VtOleNBctQY65p+AbqSODjUsuPH2evFB6h/bFtwv9T47khbvNnZB1 B4VdT+LfTcWdGEuXlOAi0PEvqKVzD3TkvOfhdqQ177526Tds+nmnj1CY37OSHz/sb3sk cQNz3XWwGQdwU7HmNGwS+PlpUNzb4LIyM+NxBpgN2ZlbwQ7e9ODMP93XAnv679WPwPF3 rwkw== X-Gm-Message-State: AOAM530XMTuOWi3HUtQdOOF52bZeiXpb+8vl3Pts3v+BVo1Cj+2WtYct XRAyjtssyNOPcLZ9c0cn9Obaog== X-Google-Smtp-Source: ABdhPJzE0Qv4VA9u7coJiou+usu938kD9Ut7aayqEOUmFkVn+Ezo6bsKgGZ2G3/I33F9aqOg1eZDhA== X-Received: by 2002:a5d:4207:0:b0:20e:63c3:e398 with SMTP id n7-20020a5d4207000000b0020e63c3e398mr18889448wrq.642.1653303031027; Mon, 23 May 2022 03:50:31 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:30 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Markus Schneider-Pargmann , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 04/21] drm/edid: Add cea_sad helpers for freq/length Date: Mon, 23 May 2022 12:47:37 +0200 Message-Id: <20220523104758.29531-5-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds two helper functions that extract the frequency and word length from a struct cea_sad. For these helper functions new defines are added that help translate the 'freq' and 'byte2' fields into real numbers. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/drm_edid.c | 74 ++++++++++++++++++++++++++++++++++++++ include/drm/drm_edid.h | 14 ++++++++ 2 files changed, 88 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 561f53831e29..61ef1b1c972c 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -4758,6 +4758,80 @@ int drm_edid_to_speaker_allocation(struct edid *edid= , u8 **sadb) } EXPORT_SYMBOL(drm_edid_to_speaker_allocation); =20 +/** + * drm_cea_sad_get_sample_rate - Extract the sample rate from cea_sad + * @sad: Pointer to the cea_sad struct + * + * Extracts the cea_sad frequency field and returns the sample rate in Hz. + * + * Return: Sample rate in Hz or a negative errno if parsing failed. + */ +int drm_cea_sad_get_sample_rate(const struct cea_sad *sad) +{ + switch (sad->freq) { + case DRM_CEA_SAD_FREQ_32KHZ: + return 32000; + case DRM_CEA_SAD_FREQ_44KHZ: + return 44100; + case DRM_CEA_SAD_FREQ_48KHZ: + return 48000; + case DRM_CEA_SAD_FREQ_88KHZ: + return 88200; + case DRM_CEA_SAD_FREQ_96KHZ: + return 96000; + case DRM_CEA_SAD_FREQ_176KHZ: + return 176400; + case DRM_CEA_SAD_FREQ_192KHZ: + return 192000; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL(drm_cea_sad_get_sample_rate); + +static bool drm_cea_sad_is_uncompressed(const struct cea_sad *sad) +{ + switch (sad->format) { + case HDMI_AUDIO_CODING_TYPE_STREAM: + case HDMI_AUDIO_CODING_TYPE_PCM: + return true; + default: + return false; + } +} + +/** + * drm_cea_sad_get_uncompressed_word_length - Extract word length + * @sad: Pointer to the cea_sad struct + * + * Extracts the cea_sad byte2 field and returns the word length for an + * uncompressed stream. + * + * Note: This function may only be called for uncompressed audio. + * + * Return: Word length in bits or a negative errno if parsing failed. + */ +int drm_cea_sad_get_uncompressed_word_length(const struct cea_sad *sad) +{ + if (!drm_cea_sad_is_uncompressed(sad)) { + DRM_WARN("Unable to get the uncompressed word length for a compressed fo= rmat: %u\n", + sad->format); + return -EINVAL; + } + + switch (sad->byte2) { + case DRM_CEA_SAD_UNCOMPRESSED_WORD_16BIT: + return 16; + case DRM_CEA_SAD_UNCOMPRESSED_WORD_20BIT: + return 20; + case DRM_CEA_SAD_UNCOMPRESSED_WORD_24BIT: + return 24; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL(drm_cea_sad_get_uncompressed_word_length); + /** * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay * @connector: connector associated with the HDMI/DP sink diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 37c420423625..7a939cb95b38 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -373,6 +373,18 @@ struct cea_sad { u8 byte2; }; =20 +#define DRM_CEA_SAD_FREQ_32KHZ BIT(0) +#define DRM_CEA_SAD_FREQ_44KHZ BIT(1) +#define DRM_CEA_SAD_FREQ_48KHZ BIT(2) +#define DRM_CEA_SAD_FREQ_88KHZ BIT(3) +#define DRM_CEA_SAD_FREQ_96KHZ BIT(4) +#define DRM_CEA_SAD_FREQ_176KHZ BIT(5) +#define DRM_CEA_SAD_FREQ_192KHZ BIT(6) + +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_16BIT BIT(0) +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_20BIT BIT(1) +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_24BIT BIT(2) + struct drm_encoder; struct drm_connector; struct drm_connector_state; @@ -380,6 +392,8 @@ struct drm_display_mode; =20 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); +int drm_cea_sad_get_sample_rate(const struct cea_sad *sad); +int drm_cea_sad_get_uncompressed_word_length(const struct cea_sad *sad); int drm_av_sync_delay(struct drm_connector *connector, const struct drm_display_mode *mode); =20 --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA71FC4332F for ; Mon, 23 May 2022 10:50:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234395AbiEWKu5 (ORCPT ); Mon, 23 May 2022 06:50:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234362AbiEWKur (ORCPT ); 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:36 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Markus Schneider-Pargmann , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 05/21] video/hdmi: Add audio_infoframe packing for DP Date: Mon, 23 May 2022 12:47:38 +0200 Message-Id: <20220523104758.29531-6-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann Similar to HDMI, DP uses audio infoframes as well which are structured very similar to the HDMI ones. This patch adds a helper function to pack the HDMI audio infoframe for DP, called hdmi_audio_infoframe_pack_for_dp(). hdmi_audio_infoframe_pack_only() is split into two parts. One of them packs the payload only and can be used for HDMI and DP. Also constify the frame parameter in hdmi_audio_infoframe_check() as it is passed to hdmi_audio_infoframe_check_only() which expects a const. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/video/hdmi.c | 82 ++++++++++++++++++++++++++-------- include/drm/dp/drm_dp_helper.h | 2 + include/linux/hdmi.h | 7 ++- 3 files changed, 71 insertions(+), 20 deletions(-) diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c index 947be761dfa4..5f50237554ed 100644 --- a/drivers/video/hdmi.c +++ b/drivers/video/hdmi.c @@ -21,6 +21,7 @@ * DEALINGS IN THE SOFTWARE. */ =20 +#include #include #include #include @@ -381,12 +382,34 @@ static int hdmi_audio_infoframe_check_only(const stru= ct hdmi_audio_infoframe *fr * * Returns 0 on success or a negative error code on failure. */ -int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame) +int hdmi_audio_infoframe_check(const struct hdmi_audio_infoframe *frame) { return hdmi_audio_infoframe_check_only(frame); } EXPORT_SYMBOL(hdmi_audio_infoframe_check); =20 +static void +hdmi_audio_infoframe_pack_payload(const struct hdmi_audio_infoframe *frame, + u8 *buffer) +{ + u8 channels; + + if (frame->channels >=3D 2) + channels =3D frame->channels - 1; + else + channels =3D 0; + + buffer[0] =3D ((frame->coding_type & 0xf) << 4) | (channels & 0x7); + buffer[1] =3D ((frame->sample_frequency & 0x7) << 2) | + (frame->sample_size & 0x3); + buffer[2] =3D frame->coding_type_ext & 0x1f; + buffer[3] =3D frame->channel_allocation; + buffer[4] =3D (frame->level_shift_value & 0xf) << 3; + + if (frame->downmix_inhibit) + buffer[4] |=3D BIT(7); +} + /** * hdmi_audio_infoframe_pack_only() - write HDMI audio infoframe to binary= buffer * @frame: HDMI audio infoframe @@ -404,7 +427,6 @@ EXPORT_SYMBOL(hdmi_audio_infoframe_check); ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *= frame, void *buffer, size_t size) { - unsigned char channels; u8 *ptr =3D buffer; size_t length; int ret; @@ -420,28 +442,13 @@ ssize_t hdmi_audio_infoframe_pack_only(const struct h= dmi_audio_infoframe *frame, =20 memset(buffer, 0, size); =20 - if (frame->channels >=3D 2) - channels =3D frame->channels - 1; - else - channels =3D 0; - ptr[0] =3D frame->type; ptr[1] =3D frame->version; ptr[2] =3D frame->length; ptr[3] =3D 0; /* checksum */ =20 - /* start infoframe payload */ - ptr +=3D HDMI_INFOFRAME_HEADER_SIZE; - - ptr[0] =3D ((frame->coding_type & 0xf) << 4) | (channels & 0x7); - ptr[1] =3D ((frame->sample_frequency & 0x7) << 2) | - (frame->sample_size & 0x3); - ptr[2] =3D frame->coding_type_ext & 0x1f; - ptr[3] =3D frame->channel_allocation; - ptr[4] =3D (frame->level_shift_value & 0xf) << 3; - - if (frame->downmix_inhibit) - ptr[4] |=3D BIT(7); + hdmi_audio_infoframe_pack_payload(frame, + ptr + HDMI_INFOFRAME_HEADER_SIZE); =20 hdmi_infoframe_set_checksum(buffer, length); =20 @@ -479,6 +486,43 @@ ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_in= foframe *frame, } EXPORT_SYMBOL(hdmi_audio_infoframe_pack); =20 +/** + * hdmi_audio_infoframe_pack_for_dp - Pack a HDMI Audio infoframe for Disp= layPort + * + * @frame: HDMI Audio infoframe + * @sdp: secondary data packet for display port. This is filled wit= h the + * appropriate: data + * @dp_version: Display Port version to be encoded in the header + * + * Packs a HDMI Audio Infoframe to be sent over Display Port. This function + * fills the secondary data packet to be used for Display Port. + * + * Return: Number of total written bytes or a negative errno on failure. + */ +ssize_t +hdmi_audio_infoframe_pack_for_dp(const struct hdmi_audio_infoframe *frame, + struct dp_sdp *sdp, u8 dp_version) +{ + int ret; + + ret =3D hdmi_audio_infoframe_check(frame); + if (ret) + return ret; + + memset(sdp->db, 0, sizeof(sdp->db)); + + /* Secondary-data packet header */ + sdp->sdp_header.HB0 =3D 0; + sdp->sdp_header.HB1 =3D frame->type; + sdp->sdp_header.HB2 =3D DP_SDP_AUDIO_INFOFRAME_HB2; + sdp->sdp_header.HB3 =3D (dp_version & 0x3f) << 2; + + hdmi_audio_infoframe_pack_payload(frame, sdp->db); + + return frame->length + 4; +} +EXPORT_SYMBOL(hdmi_audio_infoframe_pack_for_dp); + /** * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe * @frame: HDMI vendor infoframe diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h index 51e02cf75277..d4adb479263e 100644 --- a/include/drm/dp/drm_dp_helper.h +++ b/include/drm/dp/drm_dp_helper.h @@ -1576,6 +1576,8 @@ int drm_dp_bw_code_to_link_rate(u8 link_bw); #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ /* 0x80+ CEA-861 infoframe types */ =20 +#define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b + /** * struct dp_sdp_header - DP secondary data packet header * @HB0: Secondary Data Packet ID diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h index c8ec982ff498..2f4dcc8d060e 100644 --- a/include/linux/hdmi.h +++ b/include/linux/hdmi.h @@ -336,7 +336,12 @@ ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_in= foframe *frame, void *buffer, size_t size); ssize_t hdmi_audio_infoframe_pack_only(const struct hdmi_audio_infoframe *= frame, void *buffer, size_t size); -int hdmi_audio_infoframe_check(struct hdmi_audio_infoframe *frame); +int hdmi_audio_infoframe_check(const struct hdmi_audio_infoframe *frame); + +struct dp_sdp; +ssize_t +hdmi_audio_infoframe_pack_for_dp(const struct hdmi_audio_infoframe *frame, + struct dp_sdp *sdp, u8 dp_version); =20 enum hdmi_3d_structure { HDMI_3D_STRUCTURE_INVALID =3D -1, --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8E45C433EF for ; Mon, 23 May 2022 10:51:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234431AbiEWKvD (ORCPT ); Mon, 23 May 2022 06:51:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234401AbiEWKur (ORCPT ); Mon, 23 May 2022 06:50:47 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37B714D61A for ; Mon, 23 May 2022 03:50:45 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id p189so8483693wmp.3 for ; Mon, 23 May 2022 03:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ro/qKrk7X6klQMfSiDiwo/RvTYcnnsoepoqTff03G4Y=; b=K29wO0ggdqdppPdkWtuN2ZADX0K3Yqof8o/g4mDzkUMBavn4HHc+KPJwSCm7m4vzDU pM2iHEeLaEhpEg0HRURiniDIgmXS9s+h9RUBtz5faVA9M+uNJOS2s3aRM6E6jK9f6CQx ZsBNw1/TcjUmDo4jgtnarRJluH7zcJczMA2bH9RN0R4aUIvos9srcERnwQ+V3HE29eF3 PUKQcoVwtPA1MYZcJqMkGXfNAvQla0jD3wNoxuTrSWaiZyYpnMLevNQKreTYSdMP+DOi eKpmJHGgOP3TgmfCAibcMh1WnAWcErvEuUaboHnShSmxBxK8PYbvHZBelRPWe68MAn+b x2Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ro/qKrk7X6klQMfSiDiwo/RvTYcnnsoepoqTff03G4Y=; b=lNo8dpJZao+BJ86qBJgfL7frAhzk6tM5AFAKEs+OPJZ+oPg4O8Vmq7mzjAdFNf91ij IPBpPAVn7LFbqPNrqiYsdX4nBmnr6CMKGCxMoJVpwKori/X4t4cYIGh0pZchpVxKpRb0 95ygnO4n8Y229M578jV1bupO8SjfeNruSWWH80ktV4eY4aVlLNWZtGW7IGEYFcbktEg0 wcEov+K4g6dqWF1toFBswcWx/sNbb8CXPJgRlxD3IWBzzkO2/aSsvVwPiy0E/i3sUnQK 2teDFy6JrdXj2TI0xsI5zSZqRuLtmNbiW/h16v3yh0uPxkhWITvw8eSJdZz+pHEREfRx n5QQ== X-Gm-Message-State: AOAM5302Gq2I+ZWe/Vz13KH1n39X3KDB/2wySgcuZqlvccyhwn3KLEVj Xe9qzRacHd5tNGGAI+f95+SQDw== X-Google-Smtp-Source: ABdhPJzvihFTuYQI9KJCujY6AAsplQgAQKhgzZsvez9L+MrU1itYoTWpwtNW/xpzcC8Xx0p4ysAyCw== X-Received: by 2002:a05:600c:4e4d:b0:397:5009:bcf1 with SMTP id e13-20020a05600c4e4d00b003975009bcf1mr2136001wmq.66.1653303043727; Mon, 23 May 2022 03:50:43 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:43 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: AngeloGioacchino Del Regno , Rex-BC Chen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 06/21] drm/mediatek: dpi: move dpi limits to SoC config Date: Mon, 23 May 2022 12:47:39 +0200 Message-Id: <20220523104758.29531-7-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the dpi limits to the SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 4554e2de1430..4746eb342567 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + const struct mtk_dpi_yc_limit *limit; }; =20 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mas= k) @@ -235,9 +236,10 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi= , u32 width, u32 height) mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); } =20 -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, - struct mtk_dpi_yc_limit *limit) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) { + const struct mtk_dpi_yc_limit *limit =3D dpi->conf->limit; + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK); mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, @@ -449,7 +451,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) { - struct mtk_dpi_yc_limit limit; struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync_param hsync; struct mtk_dpi_sync_param vsync_lodd =3D { 0 }; @@ -484,11 +485,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", pll_rate, vm.pixelclock); =20 - limit.c_bottom =3D 0x0010; - limit.c_top =3D 0x0FE0; - limit.y_bottom =3D 0x0010; - limit.y_top =3D 0x0FE0; - dpi_pol.ck_pol =3D MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol =3D MTK_DPI_POLARITY_RISING; dpi_pol.hsync_pol =3D vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? @@ -536,7 +532,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, else mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); =20 - mtk_dpi_config_channel_limit(dpi, &limit); + mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); mtk_dpi_config_yc_map(dpi, dpi->yc_map); @@ -790,12 +786,20 @@ static const u32 mt8183_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_2X12_BE, }; =20 +static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D { + .c_bottom =3D 0x0010, + .c_top =3D 0x0FE0, + .y_bottom =3D 0x0010, + .y_top =3D 0x0FE0, +}; + static const struct mtk_dpi_conf mt8173_conf =3D { .cal_factor =3D mt8173_calculate_factor, .reg_h_fre_con =3D 0xe0, .max_clock_khz =3D 300000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt2701_conf =3D { @@ -805,6 +809,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt8183_conf =3D { @@ -813,6 +818,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .max_clock_khz =3D 100000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static const struct mtk_dpi_conf mt8192_conf =3D { @@ -821,6 +827,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .limit =3D &mtk_dpi_limit, }; =20 static int mtk_dpi_probe(struct platform_device *pdev) --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BF33C433F5 for ; Mon, 23 May 2022 10:52:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234653AbiEWKvn (ORCPT ); Mon, 23 May 2022 06:51:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35860 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234393AbiEWKux (ORCPT ); Mon, 23 May 2022 06:50:53 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C074A4D601 for ; Mon, 23 May 2022 03:50:51 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id t13so1581722wrg.9 for ; Mon, 23 May 2022 03:50:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xJFzCnziuzO8gtG7cVYt2h81Bi7LdQGE5xz4NqwQAZE=; b=EsuvaRpaBPjPspnZmyIitQ4illZAHjDrYUY/jr4vxohXj4mPgY3qtmv9bS9Oo0qG5T hTJpkQvVCGLVdr1OcwzZhoIfF+HSnNP6SUWuqf+HesSrcXkNxGfzZ6p3EmGmMKygMI5s aaZtv2av4kcC3zTncyiioTxeMZoxtYEeMTiNTAdrnKO/2gkPtCZs1ZaBzAteiUKx+z+d CeYX6k/SwCuMf4e5i7JjgAYx3VejfDYpYa7k/cBJHyVWUSXpt+rN223HFIgPxEQN4Tyf Vq1h4FdTef/lIcUdUs3FUVOWCle7fD5L9LVHFEfD6INqpKXdFzK5KfHtoPFQ/cFN9baa r8yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xJFzCnziuzO8gtG7cVYt2h81Bi7LdQGE5xz4NqwQAZE=; b=tEdxsHCN82NeG/2J1CqUTG8DSDj7lQtRCgpFc+QLTz8bri5ykWLf/aTJCCa6hPgY87 TnywWleR9zyHqC481cpyJuZzgMFrXTUOv6H4IdhDg5GLtlSN6dEhzGIskbSROI115Dxq EZsaXfgSnYjunHULam46ax/tM7/+ZawcRK+4bBtmt6v9VQMrGiRJ1ZjaKukSHMyyH8nm FC8ZWOD9Ww8MeoQ471/aCfGR1i7crQYZjobyS6qeWVRH3J5MavW5aLoYj2iRLfWxs0rc xHXb9ubecmgyWNeySqok/OytfWkDlodlfryph2lxgsx+sv623ydQikoDEHGpbA9Ht9LV A3Bg== X-Gm-Message-State: AOAM533XW73pgEVgDO2nSKspFyDlI7zUZ0eLQzvEuq5MaSt7wVFuWgFr G64Q3Zu3Q3jay5ESOmhXwi4uQw== X-Google-Smtp-Source: ABdhPJywDF5lfl2vLEx1Py2Iar0foyNQXqONIrWsCZKNHCX7kA/yZcJf7V5i1heCUswQIbZwujRe6w== X-Received: by 2002:a5d:47c9:0:b0:20f:e7da:6a48 with SMTP id o9-20020a5d47c9000000b0020fe7da6a48mr1598325wrc.315.1653303050201; Mon, 23 May 2022 03:50:50 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:49 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: AngeloGioacchino Del Regno , Rex-BC Chen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 07/21] drm/mediatek: dpi: implement a CK/DE pol toggle in SoC config Date: Mon, 23 May 2022 12:47:40 +0200 Message-Id: <20220523104758.29531-8-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds a bit of flexibility to support SoCs without CK/DE pol support Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 4746eb342567..545a1337cc89 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + bool is_ck_de_pol; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -211,13 +212,20 @@ static void mtk_dpi_config_pol(struct mtk_dpi *dpi, struct mtk_dpi_polarities *dpi_pol) { unsigned int pol; + unsigned int mask; =20 - pol =3D (dpi_pol->ck_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | - (dpi_pol->de_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | - (dpi_pol->hsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL)= | + mask =3D HSYNC_POL | VSYNC_POL; + pol =3D (dpi_pol->hsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : HSYNC_PO= L) | (dpi_pol->vsync_pol =3D=3D MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, - CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); + if (dpi->conf->is_ck_de_pol) { + mask |=3D CK_POL | DE_POL; + pol |=3D (dpi_pol->ck_pol =3D=3D MTK_DPI_POLARITY_RISING ? + 0 : CK_POL) | + (dpi_pol->de_pol =3D=3D MTK_DPI_POLARITY_RISING ? + 0 : DE_POL); + } + + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask); } =20 static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) @@ -799,6 +807,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .max_clock_khz =3D 300000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -809,6 +818,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -818,6 +828,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .max_clock_khz =3D 100000, .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -827,6 +838,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .max_clock_khz =3D 150000, .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol =3D true, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 530AAC433FE for ; Mon, 23 May 2022 10:52:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234678AbiEWKvq (ORCPT ); Mon, 23 May 2022 06:51:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234427AbiEWKvB (ORCPT ); Mon, 23 May 2022 06:51:01 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 013104D627 for ; Mon, 23 May 2022 03:50:56 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id e28so20142536wra.10 for ; Mon, 23 May 2022 03:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9jP9dq0eqNju1JFK7hi0cYxaapGwnNAhPGRZeD+o+7w=; b=M1PApx6JO0ucI5ZRRlGl3kXqjmvvORDiFf9UkR8kuE9PiPMj6LBUsOXOQkYghTqWM6 Y42sddN4qCdj6Cc7brfNShxohE/SwqyqfOLeLv/zN7i4CeqEDu0/IrVGnghkWEatMuph 1lwMHmTxyavp/pTF6hk5EjgcSgP+Kz3zP5jgkEVbTLboSIVw++xZCi7NTOBqv5+bKIVv QL9/y/wZd9lzwop/5tkjaPlvmmFqgs/8W0qu77UmDJvIS55j3zJx+pgxdFe8GwqCcJQo 60IvuR05z6saM5V8DM4eI/hgCPbuj+ZMwVIj1R/1f7dFfIaLu+BjfsfnN+yXwBDedu2x lvXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9jP9dq0eqNju1JFK7hi0cYxaapGwnNAhPGRZeD+o+7w=; b=Gfft7DTxugcpsM12LrDjxr2xd/62Qi9VI+VrPW9+Sy5+3U8rGAFHJVtB8nR1anCDl3 lg61vVJEeeEm0A0hDp5wSNigp+YFXoa/sLUQElaGaOzcGJWwiWC28dhW+pb2PoYjH39R /x+wiElfmsJvVYpE8VxJj1ZRyuAGWPbrYH007eaRGwHFIKH+cxjd/zRsh6pJ0DAX/wZn Rh7wCfitmqwZdFusbd8RRZRd8etfGci0AMOw3Z5nxM9FX5+7Gj4zcyxKVbLslB4z0Y2j +xiW3/dAQ8YwJnzSJsUBpG+VvmkqIcGVOcy5mtlwH3y37XRLAoq2MiPaxYuH/MAejbE5 Y1rQ== X-Gm-Message-State: AOAM532WmiqP+Xt9XnpPQQkhmxjtOUSTJVOUD1gu/s9AS0JweaSZ5LaA 7bBH2PM5b5OzUt/FFGlJzFv4Lg== X-Google-Smtp-Source: ABdhPJzFVsn52LLkc6F5P2MSaLKmhQPgvOfhCMFcPHG2HJ9CtCk4fi83gaSnITOg3ufjkMvUe7umaQ== X-Received: by 2002:a5d:6042:0:b0:20e:65c0:f69b with SMTP id j2-20020a5d6042000000b0020e65c0f69bmr18712524wrt.524.1653303056451; Mon, 23 May 2022 03:50:56 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:56 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: AngeloGioacchino Del Regno , Rex-BC Chen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 08/21] drm/mediatek: dpi: implement a swap_input toggle in SoC config Date: Mon, 23 May 2022 12:47:41 +0200 Message-Id: <20220523104758.29531-9-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds a bit of flexibility to support SoCs without swap_input support Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 545a1337cc89..454f8563efae 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool swap_input_support; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -378,18 +379,21 @@ static void mtk_dpi_config_color_format(struct mtk_dp= i *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); } else if ((format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422) || (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, true); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } else { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, false); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } } @@ -808,6 +812,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -819,6 +824,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -829,6 +835,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .output_fmts =3D mt8183_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 @@ -839,6 +846,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .output_fmts =3D mt8173_output_fmts, .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, + .swap_input_support =3D true, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A946C433F5 for ; Mon, 23 May 2022 10:51:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234702AbiEWKvt (ORCPT ); Mon, 23 May 2022 06:51:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234449AbiEWKvG (ORCPT ); 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:02 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: AngeloGioacchino Del Regno , Rex-BC Chen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 09/21] drm/mediatek: dpi: move dimension mask to SoC config Date: Mon, 23 May 2022 12:47:42 +0200 Message-Id: <20220523104758.29531-10-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the dimension mask to the SoC config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 454f8563efae..bf098f36a466 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -127,6 +127,8 @@ struct mtk_dpi_conf { u32 num_output_fmts; bool is_ck_de_pol; bool swap_input_support; + /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ + u32 dimension_mask; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -156,30 +158,30 @@ static void mtk_dpi_disable(struct mtk_dpi *dpi) static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync) { - mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, - sync->sync_width << HPW, HPW_MASK); - mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, - sync->back_porch << HBP, HBP_MASK); + mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, + dpi->conf->dimension_mask << HPW); + mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP, + dpi->conf->dimension_mask << HBP); mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, - HFP_MASK); + dpi->conf->dimension_mask << HFP); } =20 static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync, u32 width_addr, u32 porch_addr) { - mtk_dpi_mask(dpi, width_addr, - sync->sync_width << VSYNC_WIDTH_SHIFT, - VSYNC_WIDTH_MASK); mtk_dpi_mask(dpi, width_addr, sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, VSYNC_HALF_LINE_MASK); + mtk_dpi_mask(dpi, width_addr, + sync->sync_width << VSYNC_WIDTH_SHIFT, + dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->back_porch << VSYNC_BACK_PORCH_SHIFT, - VSYNC_BACK_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, - VSYNC_FRONT_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); } =20 static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, @@ -813,6 +815,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -825,6 +828,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -836,6 +840,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -847,6 +852,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .num_output_fmts =3D ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol =3D true, .swap_input_support =3D true, + .dimension_mask =3D HPW_MASK, .limit =3D &mtk_dpi_limit, }; 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:09 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: AngeloGioacchino Del Regno , Rex-BC Chen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 10/21] drm/mediatek: dpi: move hvsize_mask to SoC config Date: Mon, 23 May 2022 12:47:43 +0200 Message-Id: <20220523104758.29531-11-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the hvsize mask to SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index bf098f36a466..6eeda222a973 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -129,6 +129,8 @@ struct mtk_dpi_conf { bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; + /* HSIZE and VSIZE mask (no shift) */ + u32 hvsize_mask; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -243,8 +245,10 @@ static void mtk_dpi_config_interface(struct mtk_dpi *d= pi, bool inter) =20 static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 hei= ght) { - mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); - mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); + mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, + dpi->conf->hvsize_mask << HSIZE); + mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, + dpi->conf->hvsize_mask << VSIZE); } =20 static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) @@ -816,6 +820,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -829,6 +834,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -841,6 +847,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; =20 @@ -853,6 +860,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .is_ck_de_pol =3D true, .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, + .hvsize_mask =3D HSIZE_MASK, .limit =3D &mtk_dpi_limit, }; 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:15 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Rex-BC Chen , AngeloGioacchino Del Regno , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 11/21] drm/mediatek: dpi: move swap_shift to SoC config Date: Mon, 23 May 2022 12:47:44 +0200 Message-Id: <20220523104758.29531-12-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the swap shift value to SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 6eeda222a973..6d4d8c6ec47d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -131,6 +131,7 @@ struct mtk_dpi_conf { u32 dimension_mask; /* HSIZE and VSIZE mask (no shift) */ u32 hvsize_mask; + u32 channel_swap_shift; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -349,7 +350,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi = *dpi, break; } =20 - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << dpi->conf->channel_swap_shif= t, + CH_SWAP_MASK); } =20 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) @@ -821,6 +823,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -835,6 +838,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -848,6 +852,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 @@ -861,6 +866,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .swap_input_support =3D true, .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, + .channel_swap_shift =3D CH_SWAP, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E7D4C433F5 for ; Mon, 23 May 2022 10:52:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234585AbiEWKwQ (ORCPT ); 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:22 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: AngeloGioacchino Del Regno , Rex-BC Chen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 12/21] drm/mediatek: dpi: move the yuv422_en_bit to SoC config Date: Mon, 23 May 2022 12:47:45 +0200 Message-Id: <20220523104758.29531-13-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the yuv422 en bit to SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 6d4d8c6ec47d..40254cd9d168 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -132,6 +132,7 @@ struct mtk_dpi_conf { /* HSIZE and VSIZE mask (no shift) */ u32 hvsize_mask; u32 channel_swap_shift; + u32 yuv422_en_bit; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -356,7 +357,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi = *dpi, =20 static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, + dpi->conf->yuv422_en_bit); } =20 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) @@ -824,6 +826,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -839,6 +842,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -853,6 +857,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 @@ -867,6 +872,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .dimension_mask =3D HPW_MASK, .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, + .yuv422_en_bit =3D YUV422_EN, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CFFDC433EF for ; Mon, 23 May 2022 10:52:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234592AbiEWKwY (ORCPT ); Mon, 23 May 2022 06:52:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234607AbiEWKvc (ORCPT ); Mon, 23 May 2022 06:51:32 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 518B82B1B4 for ; Mon, 23 May 2022 03:51:30 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id f2so20791811wrc.0 for ; Mon, 23 May 2022 03:51:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JGvhVV4JqPNXk+p5F/0CMZDfiaz8h8RwYuVglR+Hdfg=; b=SSKJwV3dhXlND8s9/ZiSdxc7iQkclv7sEeQvp7zakKPDyj/A5NxLyj/8NxDKainYsZ 66XRu7ieISGUu3vhVKtVxx2psktGaF7/gSBqnOdTK2U8Jil0Jl/KKe4qfsA4kW4tZF1m r5otL/wEBNRALQlcdG0qNzyuVqJK0l2zU8WbjDqxutAObwUA7Qn3DryKlBsEox8FuH5X t8kqrsI2tDL7+xTsF+ifFgq/UkscxL6yNBR/R/h7PdHdKrZk9p0geJs2s76EVFYKRTxt ISr80sfHjfhqug2M/MI+VRXzC2M9PBoiVntGVHxAhJXAcDUgzs0+Rh9ku8IA7bpwU3lP WbvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JGvhVV4JqPNXk+p5F/0CMZDfiaz8h8RwYuVglR+Hdfg=; b=6oeauHw7V9BlNGvskQARt+KQYIp2NQc3z9QsVBoOkzmXKDsZpGfuyVrtFEmDjBOmGu s+fy20aYBmJQ4MVMMdfqMb+DGzVmbLYqZNM3aZYuK4/KFZ6iLG7WMkHcDWC7Y+1UCBY2 3ZKjXpBetcowqJuf2uVkNsD8SEb8J1ez1bWZ317eqtpZDffq2UBkGxg+9NU5wEpekZoi T0HIqZ1AbMi+MIIeG5xOIKV7K9ypj6a2wrpiaJVEf0YhUQBWWxA175W1zJgyszpRvNYc tuGvKkY0SP5li2z8dyiiqEvEtW9Ai6epu9YDfgnunn2DcH/25561prcCfvJLrk4boZKp lnag== X-Gm-Message-State: AOAM531RiA6iFfyoccwQh+ewOyFQSJEaPvVOX1liGYyidbfCle3ehlzV 9DL72+WU/w2pPAYZAJ90jTIkqw== X-Google-Smtp-Source: ABdhPJzI1cZH2vxHZeGJbkrpsiAZ+QGY1J5LlXZuKh30WZu+XMTP0w16zzNcwHcU73Y9iru6sVfBIw== X-Received: by 2002:a5d:674b:0:b0:20e:6164:d86f with SMTP id l11-20020a5d674b000000b0020e6164d86fmr18179608wrw.297.1653303089880; Mon, 23 May 2022 03:51:29 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:29 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: AngeloGioacchino Del Regno , Rex-BC Chen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 13/21] drm/mediatek: dpi: move the csc_enable bit to SoC config Date: Mon, 23 May 2022 12:47:46 +0200 Message-Id: <20220523104758.29531-14-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add flexibility by moving the csc_enable bit to SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 40254cd9d168..eb969c5c5c2e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -133,6 +133,7 @@ struct mtk_dpi_conf { u32 hvsize_mask; u32 channel_swap_shift; u32 yuv422_en_bit; + u32 csc_enable_bit; const struct mtk_dpi_yc_limit *limit; }; =20 @@ -363,7 +364,8 @@ static void mtk_dpi_config_yuv422_enable(struct mtk_dpi= *dpi, bool enable) =20 static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0, + dpi->conf->csc_enable_bit); } =20 static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) @@ -827,6 +829,7 @@ static const struct mtk_dpi_conf mt8173_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -843,6 +846,7 @@ static const struct mtk_dpi_conf mt2701_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -858,6 +862,7 @@ static const struct mtk_dpi_conf mt8183_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 @@ -873,6 +878,7 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .hvsize_mask =3D HSIZE_MASK, .channel_swap_shift =3D CH_SWAP, .yuv422_en_bit =3D YUV422_EN, + .csc_enable_bit =3D CSC_ENABLE, .limit =3D &mtk_dpi_limit, }; =20 --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A22DAC433EF for ; Mon, 23 May 2022 10:52:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234613AbiEWKwa (ORCPT ); Mon, 23 May 2022 06:52:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234636AbiEWKvj (ORCPT ); Mon, 23 May 2022 06:51:39 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B65C2CCAE for ; Mon, 23 May 2022 03:51:37 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id r23so20787802wrr.2 for ; Mon, 23 May 2022 03:51:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S/+WPxlClGKcWofUCpXvXpeCH//anDZC43gjAoW3AyE=; b=VL+K7whhalHBihc6z7vf2KijkrVqf9zq2TdUapRaqr11xAAaWNdNMuw8R5Rh1hIDBJ QMTj7Tm4X1nM3UNZ0TX/FVPVdrYk9urnbgMFguij8ycpNhjrsCkj/D0KZUzVL2eWtxav KdrnN7EHaP5wPpsP7SOCkjXAwjywwPusoZfAsHEGGqQ9cdHzaXBYEHP4A8sIOz4Ewoq4 H1c+uzluWhhu/u8G05e8/UooXw5OPGYTfQ83U7CoodZXw0emhEGVLvKabWEkZwPEKs+7 ktNWlpQlfohOBB9jD8oAQmMQgjISzh4OUIeuxcQ8zdsGhEHcpG5JXol/5BQGPCGwEoFc rexQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S/+WPxlClGKcWofUCpXvXpeCH//anDZC43gjAoW3AyE=; b=gqWaVup1Wm+HnGcC6QSt/JVK5d8RMdpfV44zIBMIKatCVPE7w1kc6LtV2TIMfTQJol 6s/2Z1NUxgQv4XPCd4LY0mqFclNEjdaLw8/LIFkV67XfP6M2S3ynscfM399I8KQGzk4G HSCf3cnrepU/LMZFA9YfgWEiT7QUNeib7RpChsgGunILoEI1miYwQwXqxoKwUHiguAGH t57gRhw6F+gzPfUmdiKAdDhoA6/x3hrMOeLCn1ZgdnF1Ds0B5aeoFvhmHXd3r5bMK7XI shXXVKvyaC/ozr+MBY1zV2Tz2d2XK8VKCUfV7NYsf+QvUvpPRw1mnJekimwtDkHmLXMX K4OA== X-Gm-Message-State: AOAM5324Z85xtFqy07V/BtAlK2WMDjmelF7ovnbhv+S4zlKQOqju/frJ mUpjMWluipl/lpcShKp4+piBtQ== X-Google-Smtp-Source: ABdhPJxla1xBj+auonHTmY7ZBywwlogv80kEatIKMueKEaS8RwV2O/V1TsPIdUEkZ1bhuocz7/Sfrw== X-Received: by 2002:adf:d1ce:0:b0:20c:5d7c:b513 with SMTP id b14-20020adfd1ce000000b0020c5d7cb513mr18456613wrd.651.1653303096642; Mon, 23 May 2022 03:51:36 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:36 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Markus Schneider-Pargmann , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 14/21] drm/mediatek: dpi: Add dpintf support Date: Mon, 23 May 2022 12:47:47 +0200 Message-Id: <20220523104758.29531-15-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code. This patch adds support for mt8195-dpintf to this dpi driver. Main differences are: - Some features/functional components are not available for dpintf which are now excluded from code execution once is_dpintf is set - dpintf can and needs to choose between different clockdividers based on the clockspeed. This is done by choosing a different clock parent. - There are two additional clocks that need to be managed. These are only set for dpintf and will be set to NULL if not supplied. The clk_* calls handle these as normal clocks then. - Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different. Based on a separate driver for dpintf created by Jason-JH.Lin . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 126 +++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 35 ++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +- include/linux/soc/mediatek/mtk-mmsys.h | 4 +- 6 files changed, 159 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index eb969c5c5c2e..763bfb700135 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -71,6 +71,7 @@ struct mtk_dpi { void __iomem *regs; struct device *dev; struct clk *engine_clk; + struct clk *dpi_ck_cg; struct clk *pixel_clk; struct clk *tvd_clk; int irq; @@ -126,6 +127,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool is_dpintf; bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; @@ -438,6 +440,8 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->dpi_ck_cg); + clk_disable_unprepare(dpi->tvd_clk); } =20 static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -447,12 +451,24 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount !=3D 1) return 0; =20 + ret =3D clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_pixel; + } + ret =3D clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); goto err_refcount; } =20 + ret =3D clk_prepare_enable(dpi->dpi_ck_cg); + if (ret) { + dev_err(dpi->dev, "Failed to enable dpi_ck_cg clock: %d\n", ret); + goto err_ck_cg; + } + ret =3D clk_prepare_enable(dpi->pixel_clk); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); @@ -466,6 +482,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) return 0; =20 err_pixel: + clk_disable_unprepare(dpi->dpi_ck_cg); +err_ck_cg: clk_disable_unprepare(dpi->engine_clk); err_refcount: dpi->refcount--; @@ -498,11 +516,11 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, =20 vm.pixelclock =3D pll_rate / factor; if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || - (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) + (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) { clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); - else + } else { clk_set_rate(dpi->pixel_clk, vm.pixelclock); - + } =20 vm.pixelclock =3D clk_get_rate(dpi->pixel_clk); =20 @@ -515,9 +533,15 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dp= i, MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; dpi_pol.vsync_pol =3D vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; - hsync.sync_width =3D vm.hsync_len; - hsync.back_porch =3D vm.hback_porch; - hsync.front_porch =3D vm.hfront_porch; + if (dpi->conf->is_dpintf) { + hsync.sync_width =3D vm.hsync_len / 4; + hsync.back_porch =3D vm.hback_porch / 4; + hsync.front_porch =3D vm.hfront_porch / 4; + } else { + hsync.sync_width =3D vm.hsync_len; + hsync.back_porch =3D vm.hback_porch; + hsync.front_porch =3D vm.hfront_porch; + } hsync.shift_half_line =3D false; vsync_lodd.sync_width =3D vm.vsync_len; vsync_lodd.back_porch =3D vm.vback_porch; @@ -559,13 +583,20 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->is_dpintf) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } else { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false); =20 + mtk_dpi_enable(dpi); + return 0; } =20 @@ -608,7 +639,6 @@ static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(st= ruct drm_bridge *bridge, u32 *input_fmts; =20 *num_input_fmts =3D 0; - input_fmts =3D kcalloc(1, sizeof(*input_fmts), GFP_KERNEL); if (!input_fmts) @@ -634,15 +664,18 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bri= dge *bridge, if (dpi->conf->num_output_fmts) out_bus_format =3D dpi->conf->output_fmts[0]; =20 - dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", - bridge_state->input_bus_cfg.format, - bridge_state->output_bus_cfg.format); + dev_info(dpi->dev, "input format 0x%04x, output format 0x%04x\n", + bridge_state->input_bus_cfg.format, + bridge_state->output_bus_cfg.format); =20 dpi->output_fmt =3D out_bus_format; dpi->bit_num =3D MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap =3D MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map =3D MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; + if (out_bus_format =3D=3D MEDIA_BUS_FMT_YUYV8_1X16) + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL; + else + dpi->color_format =3D MTK_DPI_COLOR_FORMAT_RGB; =20 return 0; } @@ -687,7 +720,7 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, { struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); =20 - if (mode->clock > dpi->conf->max_clock_khz) + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) return MODE_CLOCK_HIGH; =20 return MODE_OK; @@ -801,6 +834,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } =20 +static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -810,6 +853,12 @@ static const u32 mt8183_output_fmts[] =3D { MEDIA_BUS_FMT_RGB888_2X12_BE, }; =20 +static const u32 mt8195_output_fmts[] =3D { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D { .c_bottom =3D 0x0010, .c_top =3D 0x0FE0, @@ -817,6 +866,13 @@ static const struct mtk_dpi_yc_limit mtk_dpi_limit =3D= { .y_top =3D 0x0FE0, }; =20 +static const struct mtk_dpi_yc_limit mtk_dpintf_limit =3D { + .c_bottom =3D 0x0000, + .c_top =3D 0xFFF, + .y_bottom =3D 0x0000, + .y_top =3D 0xFFF, +}; + static const struct mtk_dpi_conf mt8173_conf =3D { .cal_factor =3D mt8173_calculate_factor, .reg_h_fre_con =3D 0xe0, @@ -882,6 +938,19 @@ static const struct mtk_dpi_conf mt8192_conf =3D { .limit =3D &mtk_dpi_limit, }; =20 +static const struct mtk_dpi_conf mt8195_dpintf_conf =3D { + .cal_factor =3D mt8195_dpintf_calculate_factor, + .output_fmts =3D mt8195_output_fmts, + .num_output_fmts =3D ARRAY_SIZE(mt8195_output_fmts), + .is_dpintf =3D true, + .dimension_mask =3D DPINTF_HPW_MASK, + .hvsize_mask =3D DPINTF_HSIZE_MASK, + .channel_swap_shift =3D DPINTF_CH_SWAP, + .yuv422_en_bit =3D DPINTF_YUV422_EN, + .csc_enable_bit =3D DPINTF_CSC_ENABLE, + .limit =3D &mtk_dpintf_limit, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -929,7 +998,27 @@ static int mtk_dpi_probe(struct platform_device *pdev) if (IS_ERR(dpi->engine_clk)) { ret =3D PTR_ERR(dpi->engine_clk); if (ret !=3D -EPROBE_DEFER) - dev_err(dev, "Failed to get engine clock: %d\n", ret); + dev_err(dev, "Failed to get engine clock: %d\n", + ret); + + return ret; + } + + dpi->dpi_ck_cg =3D devm_clk_get_optional(dev, "ck_cg"); + if (IS_ERR(dpi->dpi_ck_cg)) { + ret =3D PTR_ERR(dpi->dpi_ck_cg); + if (ret !=3D -EPROBE_DEFER) + dev_err(dev, "Failed to get dpi ck cg clock: %d\n", + ret); + + return ret; + } + + dpi->dpi_ck_cg =3D devm_clk_get_optional(dev, "ck_cg"); + if (IS_ERR(dpi->dpi_ck_cg)) { + ret =3D PTR_ERR(dpi->dpi_ck_cg); + if (ret !=3D -EPROBE_DEFER) + dev_err(dev, "Failed to get dpi ck cg clock: %d\n", ret); =20 return ret; } @@ -1004,6 +1093,9 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D= { { .compatible =3D "mediatek,mt8192-dpi", .data =3D &mt8192_conf, }, + { .compatible =3D "mediatek,mt8195-dpintf", + .data =3D &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi= atek/mtk_dpi_regs.h index 3a02fabe1662..dd47dd3f2e4f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,10 +40,15 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29) =20 #define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP BIT(1) #define CH_SWAP_MASK (0x7 << 0) +#define DPINTF_CH_SWAP_MASK (0x7 << 1) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 #define SWAP_BRG 0x02 @@ -80,8 +85,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16) =20 #define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -93,24 +100,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0) =20 #define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16) =20 #define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C =20 #define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) =20 #define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) @@ -217,4 +230,26 @@ =20 #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + +#define RGB_TO_JPEG 0x00 +#define RGB_TO_FULL709 0x01 +#define RGB_TO_BT601 0x02 +#define RGB_TO_BT709 0x03 +#define JPEG_TO_RGB 0x04 +#define FULL709_TO_RGB 0x05 +#define BT601_TO_RGB 0x06 +#define BT709_TO_RGB 0x07 +#define JPEG_TO_BT601 0x08 +#define JPEG_TO_BT709 0x09 +#define BT601_TO_JPEG 0xA +#define BT709_TO_JPEG 0xB +#define BT709_TO_BT601 0xC +#define BT601_TO_BT709 0xD +#define JPEG_TO_CERGB 0x14 +#define FULL709_TO_CERGB 0x15 +#define BT601_TO_CERGB 0x16 +#define BT709_TO_CERGB 0x17 +#define RGB_TO_CERGB 0x1C +#define MATRIX_BIT BIT(8) +#define EXT_MATRIX_EN BIT(12) #endif /* __MTK_DPI_REGS_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.c index 245d0074e12d..3738665a712e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -419,6 +419,11 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_CO= MP_TYPE_MAX] =3D { [MTK_DISP_WDMA] =3D "wdma", [MTK_DPI] =3D "dpi", [MTK_DSI] =3D "dsi", + [MTK_DP_INTF] =3D "dp-intf", + [MTK_DISP_PWM] =3D "pwm", + [MTK_DISP_MUTEX] =3D "mutex", + [MTK_DISP_OD] =3D "od", + [MTK_DISP_BLS] =3D "bls", }; =20 struct mtk_ddp_comp_match { @@ -439,6 +444,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_ID_MAX] =3D { [DDP_COMPONENT_DPI1] =3D { MTK_DPI, 1, &ddp_dpi }, [DDP_COMPONENT_DSC0] =3D { MTK_DISP_DSC, 0, &ddp_dsc }, [DDP_COMPONENT_DSC1] =3D { MTK_DISP_DSC, 1, &ddp_dsc }, + [DDP_COMPONENT_DP_INTF0] =3D { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] =3D { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] =3D { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] =3D { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] =3D { MTK_DSI, 2, &ddp_dsi }, @@ -565,6 +572,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct = mtk_ddp_comp *comp, type =3D=3D MTK_DISP_PWM || type =3D=3D MTK_DISP_RDMA || type =3D=3D MTK_DPI || + type =3D=3D MTK_DP_INTF || type =3D=3D MTK_DSI) return 0; =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/= mediatek/mtk_drm_ddp_comp.h index 825d763d2378..c4e683f46a95 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -37,6 +37,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, + MTK_DP_INTF, MTK_DSI, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index a2a783fc580e..e25ac61aac08 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -690,6 +690,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DPI }, { .compatible =3D "mediatek,mt8183-dpi", .data =3D (void *)MTK_DPI }, + { .compatible =3D "mediatek,mt8195-dpintf", + .data =3D (void *)MTK_DP_INTF }, { .compatible =3D "mediatek,mt2701-dsi", .data =3D (void *)MTK_DSI }, { .compatible =3D "mediatek,mt8173-dsi", @@ -801,8 +803,9 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type =3D=3D MTK_DISP_OVL_2L || comp_type =3D=3D MTK_DISP_OVL_ADAPTOR || comp_type =3D=3D MTK_DISP_RDMA || + comp_type =3D=3D MTK_DSI || comp_type =3D=3D MTK_DPI || - comp_type =3D=3D MTK_DSI) { + comp_type =3D=3D MTK_DP_INTF) { dev_info(dev, "Adding component match for %pOF\n", node); drm_of_component_match_add(dev, &match, component_compare_of, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index 3e998bfb795a..e4b84c347201 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -21,12 +21,12 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DITHER, - DDP_COMPONENT_DP_INTF0, - DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI1, DDP_COMPONENT_DSC0, DDP_COMPONENT_DSC1, + DDP_COMPONENT_DP_INTF0, + DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2, --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29EF4C433EF for ; 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:42 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 15/21] drm/mediatek: dpi: Only enable dpi after the bridge is enabled Date: Mon, 23 May 2022 12:47:48 +0200 Message-Id: <20220523104758.29531-16-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enabling the dpi too early causes glitches on screen. Move the call to mtk_dpi_enable() at the end of the bridge_enable callback to ensure everything is setup properly before enabling dpi. Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 763bfb700135..a6b6d62a17e7 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -478,7 +478,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); =20 - mtk_dpi_enable(dpi); return 0; =20 err_pixel: @@ -711,6 +710,7 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *br= idge) =20 mtk_dpi_power_on(dpi); mtk_dpi_set_display_mode(dpi, &dpi->mode); + mtk_dpi_enable(dpi); } =20 static enum drm_mode_status --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F3F0C433F5 for ; Mon, 23 May 2022 10:52:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234626AbiEWKwj (ORCPT ); Mon, 23 May 2022 06:52:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234449AbiEWKvx (ORCPT ); Mon, 23 May 2022 06:51:53 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25D8A2CCB0 for ; Mon, 23 May 2022 03:51:51 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id e2so9131612wrc.1 for ; Mon, 23 May 2022 03:51:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4zP6HMIa2YPzZ4Ud3UnVV9v/2WWghDZEujrnaWZbPns=; b=CVxXAcJ7h3wlqtwZU9H9KpppU+0u/RTKAuP4gBIGTnyBTrBe1J9DA3/oPGdgksz0xy GLUAXoK2K5PD5Qa5uoLYqngMrUqTrBQJ22WiVornX3mY7lg3WgNkr4opKRljcDGJ+/bZ bW3RuhkiUKraQUELKEkJxDdqc9nVn+Cdrp9idbZpPPJXCWSoi+iPXeHO6GRdDakV8A0+ KEZmDMyXYpfBriNae5MHHjylHFP8Q/FOiVWpPyPtKhse51L0ASaj2EH1H/nCY3QgBzmZ PDdfqUyUduPQmp+OuR3gzYBUFeiFmKAZZCk6UmkCYrXc5uFd1B9NK+3wO+q7fCqOFV0R g8Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4zP6HMIa2YPzZ4Ud3UnVV9v/2WWghDZEujrnaWZbPns=; b=RjoQ6RaLvPbWOW/f/frIM9WCjbAEzkNEyRi4f03sqpxzkjonQ7ICN6o7waDn29VSdr 187u4B+oHB5GFJrS3K4+YCzBbtMq2FWy5Kinvy0EFB+wHxWUQ+2Ei4sWX+bQSY5kMkL8 LdZe4qJ/g3w6nT2+JoCAzLzDvfBJm1SSbh59enfbGUQvDxAaUwSEN2Mn1Ydg6PakvZMm Byvy8hAvDIPSLSaHf5wvcCRVFsZmGlHIPZNpRN19wE4nIEl55PxCIJFQi3BpTz4PYclq TzuW6A3qwJTCI5YHXXw6+BxfWbJy9l39njJPB7wKFYSBuYwQaBs8GOgaIAOVlm+YlHj8 xDMg== X-Gm-Message-State: AOAM530jzzqXS/ZZJ/A7jGZwgIl9arClt0Y+ecsHHUivJbSkoJ3bEMjT Zx9ONP0rmgRcMDlnVCD2W+xSxg== X-Google-Smtp-Source: ABdhPJyQ9VeNqhjj7qlI7JhdS3acBdep+9UKDmpO3Y91brQHC2cBHqOMlHX3SGs3/FwHb18YDgbYJA== X-Received: by 2002:a5d:6484:0:b0:20f:cc0b:e3f1 with SMTP id o4-20020a5d6484000000b0020fcc0be3f1mr8011615wri.237.1653303109362; Mon, 23 May 2022 03:51:49 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:48 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 16/21] drm/meditek: dpi: Add matrix_sel helper Date: Mon, 23 May 2022 12:47:49 +0200 Message-Id: <20220523104758.29531-17-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format. Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 21 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 3 +++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index a6b6d62a17e7..5b88a7ed5845 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -386,6 +386,25 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi= *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); } =20 +static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi, enum mtk_dpi_out_color= _format format) +{ + u32 matrix_sel =3D 0; + + switch (format) { + case MTK_DPI_COLOR_FORMAT_YCBCR_422: + case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL: + case MTK_DPI_COLOR_FORMAT_YCBCR_444: + case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL: + case MTK_DPI_COLOR_FORMAT_XV_YCC: + if (dpi->mode.hdisplay <=3D 720) + matrix_sel =3D 0x2; + break; + default: + break; + } + mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel, INT_MATRIX_SEL_MASK); +} + static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { @@ -393,6 +412,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi = *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); @@ -400,6 +420,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi = *dpi, (format =3D=3D MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi= atek/mtk_dpi_regs.h index dd47dd3f2e4f..91b32dfffced 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -231,6 +231,9 @@ #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) =20 +#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL BIT(0) +#define INT_MATRIX_SEL_MASK (0x1F << 0) #define RGB_TO_JPEG 0x00 #define RGB_TO_FULL709 0x01 #define RGB_TO_BT601 0x02 --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90828C433F5 for ; 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:55 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Markus Schneider-Pargmann , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 17/21] phy: phy-mtk-dp: Add driver for DP phy Date: Mon, 23 May 2022 12:47:50 +0200 Message-Id: <20220523104758.29531-18-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann This is a new driver that supports the integrated DisplayPort phy for mediatek SoCs, especially the mt8195. The phy is integrated into the DisplayPort controller and will be created by the mtk-dp driver. This driver expects a struct regmap to be able to work on the same registers as the DisplayPort controller. It sets the device data to be the struct phy so that the DisplayPort controller can easily work with it. The driver does not have any devicetree bindings because the datasheet does not list the controller and the phy as distinct units. The interaction with the controller can be covered by the configure callback of the phy framework and its displayport parameters. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- MAINTAINERS | 1 + drivers/phy/mediatek/Kconfig | 8 ++ drivers/phy/mediatek/Makefile | 1 + drivers/phy/mediatek/phy-mtk-dp.c | 200 ++++++++++++++++++++++++++++++ 4 files changed, 210 insertions(+) create mode 100644 drivers/phy/mediatek/phy-mtk-dp.c diff --git a/MAINTAINERS b/MAINTAINERS index 4cc47b2dbdc9..bfca96469d80 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6604,6 +6604,7 @@ L: linux-mediatek@lists.infradead.org (moderated for = non-subscribers) S: Supported F: Documentation/devicetree/bindings/display/mediatek/ F: drivers/gpu/drm/mediatek/ +F: drivers/phy/mediatek/phy-mtk-dp.c F: drivers/phy/mediatek/phy-mtk-hdmi* F: drivers/phy/mediatek/phy-mtk-mipi* =20 diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig index 55f8e6c048ab..f7ec86059049 100644 --- a/drivers/phy/mediatek/Kconfig +++ b/drivers/phy/mediatek/Kconfig @@ -55,3 +55,11 @@ config PHY_MTK_MIPI_DSI select GENERIC_PHY help Support MIPI DSI for Mediatek SoCs. + +config PHY_MTK_DP + tristate "MediaTek DP-PHY Driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF + select GENERIC_PHY + help + Support DisplayPort PHY for Mediatek SoCs. diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile index ace660fbed3a..4ba1e0650434 100644 --- a/drivers/phy/mediatek/Makefile +++ b/drivers/phy/mediatek/Makefile @@ -3,6 +3,7 @@ # Makefile for the phy drivers. # =20 +obj-$(CONFIG_PHY_MTK_DP) +=3D phy-mtk-dp.o obj-$(CONFIG_PHY_MTK_TPHY) +=3D phy-mtk-tphy.o obj-$(CONFIG_PHY_MTK_UFS) +=3D phy-mtk-ufs.o obj-$(CONFIG_PHY_MTK_XSPHY) +=3D phy-mtk-xsphy.o diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-m= tk-dp.c new file mode 100644 index 000000000000..6f29854f0c2f --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-dp.c @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek DisplayPort PHY driver + * + * Copyright (c) 2021 BayLibre + * Author: Markus Schneider-Pargmann + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PHY_OFFSET 0x1000 + +#define MTK_DP_PHY_DIG_PLL_CTL_1 (PHY_OFFSET + 0x14) +#define TPLL_SSC_EN BIT(3) + +#define MTK_DP_PHY_DIG_BIT_RATE (PHY_OFFSET + 0x3C) +#define BIT_RATE_RBR 0 +#define BIT_RATE_HBR 1 +#define BIT_RATE_HBR2 2 +#define BIT_RATE_HBR3 3 + +#define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38) +#define DP_GLB_SW_RST_PHYD BIT(0) + +#define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138) +#define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238) +#define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338) +#define MTK_DP_LANE3_DRIVING_PARAM_3 (PHY_OFFSET + 0x438) +#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4) +#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT ((BIT(2) | BIT(4)) << 8) +#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19) +#define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT GENMASK(29, 29) +#define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT) + +#define XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT GENMASK(4, 3) +#define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT GENMASK(12, 9) +#define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT ((BIT(2) | BIT(5)) << 16) +#define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT GENMASK(29, 29) +#define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT (BIT(3) | BIT(5)) +#define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT GENMASK(13, 12) +#define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0 +#define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT GENMASK(10, 10) +#define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT GENMASK(19, 19) +#define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT GENMASK(28, 28) +#define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT 0 +#define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT GENMASK(10, 9) +#define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT GENMASK(19, 18) +#define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT 0 +#define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT) + +#define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT GENMASK(3, 3) +#define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT 0 +#define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \ + XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT) + +struct mtk_dp_phy { + struct regmap *regs; +}; + +static int mtk_dp_phy_init(struct phy *phy) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + u32 driving_params[] =3D { + DRIVING_PARAM_3_DEFAULT, + DRIVING_PARAM_4_DEFAULT, + DRIVING_PARAM_5_DEFAULT, + DRIVING_PARAM_6_DEFAULT, + DRIVING_PARAM_7_DEFAULT, + DRIVING_PARAM_8_DEFAULT + }; + + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, + driving_params, ARRAY_SIZE(driving_params)); + + return 0; +} + +static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts = *opts) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + u32 val; + + if (opts->dp.set_rate) { + switch (opts->dp.link_rate) { + default: + dev_err(&phy->dev, + "Implementation error, unknown linkrate %x\n", + opts->dp.link_rate); + return -EINVAL; + case 1620: + val =3D BIT_RATE_RBR; + break; + case 2700: + val =3D BIT_RATE_HBR; + break; + case 5400: + val =3D BIT_RATE_HBR2; + break; + case 8100: + val =3D BIT_RATE_HBR3; + break; + } + regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); + } + + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1, + TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0); + + return 0; +} + +static int mtk_dp_phy_reset(struct phy *phy) +{ + struct mtk_dp_phy *dp_phy =3D phy_get_drvdata(phy); + + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, + DP_GLB_SW_RST_PHYD, 0); + usleep_range(50, 200); + regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, + DP_GLB_SW_RST_PHYD, 1); + + return 0; +} + +static const struct phy_ops mtk_dp_phy_dev_ops =3D { + .init =3D mtk_dp_phy_init, + .configure =3D mtk_dp_phy_configure, + .reset =3D mtk_dp_phy_reset, + .owner =3D THIS_MODULE, +}; + +static int mtk_dp_phy_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct mtk_dp_phy *dp_phy; + struct phy *phy; + struct regmap *regs; + + regs =3D *(struct regmap **)dev->platform_data; + if (!regs) + return dev_err_probe(dev, EINVAL, "No data passed, requires struct regma= p**\n"); + + dp_phy =3D devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL); + if (!dp_phy) + return -ENOMEM; + + dp_phy->regs =3D regs; + phy =3D devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops); + if (IS_ERR(phy)) + return dev_err_probe(dev, PTR_ERR(phy), "Failed to create DP PHY\n"); + + phy_set_drvdata(phy, dp_phy); + if (!dev->of_node) + phy_create_lookup(phy, "dp", dev_name(dev)); + + return 0; +} + +struct platform_driver mtk_dp_phy_driver =3D { + .probe =3D mtk_dp_phy_probe, + .driver =3D { + .name =3D "mediatek-dp-phy", + }, +}; +module_platform_driver(mtk_dp_phy_driver); + +MODULE_AUTHOR("Markus Schneider-Pargmann "); +MODULE_DESCRIPTION("MediaTek DP PHY Driver"); +MODULE_LICENSE("GPL"); --=20 2.35.1 From nobody Tue May 7 16:44:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E340CC433EF for ; Mon, 23 May 2022 10:53:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234707AbiEWKx2 (ORCPT ); Mon, 23 May 2022 06:53:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234659AbiEWKw6 (ORCPT ); Mon, 23 May 2022 06:52:58 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D93FE2FE60 for ; Mon, 23 May 2022 03:52:05 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id f2so20796320wrc.0 for ; Mon, 23 May 2022 03:52:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D24UX7E5uee5IV3EylV55NJWU1Qz8GiktXXiCLoiGrM=; b=txYtquuIg6uUM+kujYR8ednuwK6dJL9Kxt74XjMjKoK5cz1BtOdryyqWPB4mMUYz7U bt7VIVv9Nw34l4/GFGhliygooRo+LjZrXC3IltDjP+hdP90AgSfN+76etDFoZ6DF3Cqi Kt3vndVRrqPNiRTrBkrK1EHrzFABpiVfuSw00ekpkpRV/HysUA76yLKNam7JteQGaJDQ zRdkK0mdnVNnIbBGDKpgRdkS51FvcG8mtWWmHQbkjox3NinXyHbnw7CuDD0y5miXuF6t m4vzbsdauv1oy0wp4eO/aW+5NWRTQdRpTVzDlqdTuLd7x7R4VV62Q5v2EzKBPaoFvPYN zQqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D24UX7E5uee5IV3EylV55NJWU1Qz8GiktXXiCLoiGrM=; b=nFse9YTVl0kIoO/Xy+VjQlFOAV0qjsVWpzEsu1orJUUqxeepKe3SXYTJ3DPa4oa24Y klD+sYWPktSEcAbv523RSuUPnt2aFYzizXG6ZimpRQeAbrAW4MA/zMtZ43HvyXhl36KO p0ZtOCHvDEqEa4S7MWLcBJujfgaeACSua8vZ9p4OCkp2jWpaVbhvbGXEjJZCbyQE5C1V O/ZSya8IH5Cm7WoBu+lttmBIUo9VXZIDEyIoCrcdgmGjr7HhyX7LYT+n6/sCjvf0W5ey UvGiuXuRXhRxGGhG9TeZEQDRlV2xIRDVLBqMN4WIAFBQxaHK2aHOB1ltVoitKHKK3m/r 6Z6g== X-Gm-Message-State: AOAM531xMITYJnUgeNRJC8EWsPASElDVpQYX2YhWxQo3txm+kOSIRY6w 3NuHfgHRqcpHEVtIwe8Sp8w2CA== X-Google-Smtp-Source: ABdhPJz21ko1lQ1e3l2qHDNA7mSJYKp3KsPpBECSgvnH4UZU33oj8cWSeSRoQ79M+G22yBjeIrkjfg== X-Received: by 2002:adf:f584:0:b0:20d:431:27f8 with SMTP id f4-20020adff584000000b0020d043127f8mr18649480wro.577.1653303123491; Mon, 23 May 2022 03:52:03 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:52:02 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Markus Schneider-Pargmann , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 18/21] drm/mediatek: Add mt8195 Embedded DisplayPort driver Date: Mon, 23 May 2022 12:47:51 +0200 Message-Id: <20220523104758.29531-19-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Markus Schneider-Pargmann This patch adds a DisplayPort driver for the Mediatek mt8195 SoC. It supports the mt8195, the embedded DisplayPort units. It offers DisplayPort 1.4 with up to 4 lanes. The driver creates a child device for the phy. The child device will never exist without the parent being active. As they are sharing a register range, the parent passes a regmap pointer to the child so that both can work with the same register range. The phy driver sets device data that is read by the parent to get the phy device that can be used to control the phy properties. This driver is based on an initial version by Jason-JH.Lin . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/Kconfig | 8 + drivers/gpu/drm/mediatek/Makefile | 2 + drivers/gpu/drm/mediatek/mtk_dp.c | 2570 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dp_reg.h | 570 ++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + drivers/gpu/drm/mediatek/mtk_drm_drv.h | 3 + 6 files changed, 3156 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_dp.c create mode 100644 drivers/gpu/drm/mediatek/mtk_dp_reg.h diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kc= onfig index 2976d21e9a34..a37b6ec9f01e 100644 --- a/drivers/gpu/drm/mediatek/Kconfig +++ b/drivers/gpu/drm/mediatek/Kconfig @@ -21,6 +21,14 @@ config DRM_MEDIATEK This driver provides kernel mode setting and buffer management to userspace. =20 +config DRM_MEDIATEK_DP + tristate "DRM DPTX Support for Mediatek SoCs" + depends on DRM_MEDIATEK + select PHY_MTK_DP + select DRM_DP_HELPER + help + DRM/KMS Display Port driver for Mediatek SoCs. + config DRM_MEDIATEK_HDMI tristate "DRM HDMI Support for Mediatek SoCs" depends on DRM_MEDIATEK diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/M= akefile index 3abd27d7c91d..d4d193f60271 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -25,3 +25,5 @@ mediatek-drm-hdmi-objs :=3D mtk_cec.o \ mtk_hdmi_ddc.o =20 obj-$(CONFIG_DRM_MEDIATEK_HDMI) +=3D mediatek-drm-hdmi.o + +obj-$(CONFIG_DRM_MEDIATEK_DP) +=3D mtk_dp.o diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/m= tk_dp.c new file mode 100644 index 000000000000..8eb17ae82bfd --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -0,0 +-2,2567 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Copyright (c) 2022 BayLibre + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include