From nobody Sun Sep 22 03:28:55 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CB17C433FE for ; Mon, 23 May 2022 09:36:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233438AbiEWJfE (ORCPT ); Mon, 23 May 2022 05:35:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233264AbiEWJeJ (ORCPT ); Mon, 23 May 2022 05:34:09 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 706872612C; Mon, 23 May 2022 02:34:02 -0700 (PDT) X-UUID: a1ac9bd98b7140e280a943176e3a3cef-20220523 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:3917be3f-7522-4df2-a8b4-680935f51f08,OB:10,L OB:50,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham, ACTION:release,TS:90 X-CID-INFO: VERSION:1.1.5,REQID:3917be3f-7522-4df2-a8b4-680935f51f08,OB:10,LOB :50,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:90 X-CID-META: VersionHash:2a19b09,CLOUDID:4cf6477a-5ef6-470b-96c9-bdb8ced32786,C OID:15aacf212e67,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: a1ac9bd98b7140e280a943176e3a3cef-20220523 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 500224977; Mon, 23 May 2022 17:33:50 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 23 May 2022 17:33:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 23 May 2022 17:33:50 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , , Rex-BC Chen Subject: [RESEND v8 14/19] clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 Date: Mon, 23 May 2022 17:33:41 +0800 Message-ID: <20220523093346.28493-15-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220523093346.28493-1-rex-bc.chen@mediatek.com> References: <20220523093346.28493-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The infra_ao reset is needed for MT8192 and MT8195. - Add mtk_clk_rst_desc for MT8192 and MT8195 - Add register reset controller function for MT8192 infra_ao. - Move definition of infra reset from cl-mt8183.c to reset.h because it's the same definition with MT8192 and MT8195. - Add new definition of infra reset_4 for MT8192 and MT8195. - Add infra_ao_idx_map for MT8192 and MT8195. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: N=C3=ADcolas F. R. A. Prado [N=C3=ADcolas: Test for MT8192] Tested-by: N=C3=ADcolas F. R. A. Prado --- drivers/clk/mediatek/clk-mt8183.c | 6 ----- drivers/clk/mediatek/clk-mt8192.c | 29 ++++++++++++++++++++++ drivers/clk/mediatek/clk-mt8195-infra_ao.c | 24 ++++++++++++++++++ drivers/clk/mediatek/reset.h | 7 ++++++ 4 files changed, 60 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index b1d810f85b71..8512101e1189 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -18,12 +18,6 @@ =20 #include =20 -/* Infra global controller reset set register */ -#define INFRA_RST0_SET_OFFSET 0x120 -#define INFRA_RST1_SET_OFFSET 0x130 -#define INFRA_RST2_SET_OFFSET 0x140 -#define INFRA_RST3_SET_OFFSET 0x150 - static DEFINE_SPINLOCK(mt8183_clk_lock); =20 static const struct mtk_fixed_clk top_fixed_clks[] =3D { diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-m= t8192.c index dda211b7a745..ebbd2798d9a3 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -18,6 +18,7 @@ #include "clk-pll.h" =20 #include +#include =20 static DEFINE_SPINLOCK(mt8192_clk_lock); =20 @@ -1114,6 +1115,30 @@ static const struct mtk_gate top_clks[] =3D { GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25), }; =20 +static u16 infra_ao_rst_ofs[] =3D { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, + INFRA_RST4_SET_OFFSET, +}; + +static u16 infra_ao_idx_map[] =3D { + [MT8192_INFRA_RST0_THERM_CTRL_SWRST] =3D 0 * RST_NR_PER_BANK + 0, + [MT8192_INFRA_RST2_PEXTP_PHY_SWRST] =3D 2 * RST_NR_PER_BANK + 15, + [MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] =3D 3 * RST_NR_PER_BANK + 5, + [MT8192_INFRA_RST4_PCIE_TOP_SWRST] =3D 4 * RST_NR_PER_BANK + 1, + [MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] =3D 4 * RST_NR_PER_BANK + 12, +}; + +static const struct mtk_clk_rst_desc clk_rst_desc =3D { + .version =3D MTK_RST_SET_CLR, + .rst_bank_ofs =3D infra_ao_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infra_ao_rst_ofs), + .rst_idx_map =3D infra_ao_idx_map, + .rst_idx_map_nr =3D ARRAY_SIZE(infra_ao_idx_map), +}; + #define MT8192_PLL_FMAX (3800UL * MHZ) #define MT8192_PLL_FMIN (1500UL * MHZ) #define MT8192_INTEGER_BITS 8 @@ -1240,6 +1265,10 @@ static int clk_mt8192_infra_probe(struct platform_de= vice *pdev) if (r) goto free_clk_data; =20 + r =3D mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); + if (r) + goto free_clk_data; + r =3D of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt8195-infra_ao.c b/drivers/clk/media= tek/clk-mt8195-infra_ao.c index 8ebe3b9415c4..97657f255618 100644 --- a/drivers/clk/mediatek/clk-mt8195-infra_ao.c +++ b/drivers/clk/mediatek/clk-mt8195-infra_ao.c @@ -7,6 +7,7 @@ #include "clk-mtk.h" =20 #include +#include #include #include =20 @@ -182,9 +183,32 @@ static const struct mtk_gate infra_ao_clks[] =3D { GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub"= , "mem_466m", 31), }; =20 +static u16 infra_ao_rst_ofs[] =3D { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, + INFRA_RST4_SET_OFFSET, +}; + +static u16 infra_ao_idx_map[] =3D { + [MT8195_INFRA_RST0_THERM_CTRL_SWRST] =3D 0 * RST_NR_PER_BANK + 0, + [MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] =3D 3 * RST_NR_PER_BANK + 5, + [MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] =3D 4 * RST_NR_PER_BANK + 10, +}; + +static struct mtk_clk_rst_desc infra_ao_rst_desc =3D { + .version =3D MTK_RST_SET_CLR, + .rst_bank_ofs =3D infra_ao_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infra_ao_rst_ofs), + .rst_idx_map =3D infra_ao_idx_map, + .rst_idx_map_nr =3D ARRAY_SIZE(infra_ao_idx_map), +}; + static const struct mtk_clk_desc infra_ao_desc =3D { .clks =3D infra_ao_clks, .num_clks =3D ARRAY_SIZE(infra_ao_clks), + .rst_desc =3D &infra_ao_rst_desc, }; =20 static const struct of_device_id of_match_clk_mt8195_infra_ao[] =3D { diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index f7e1f31e3946..6a58a3d59165 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -11,6 +11,13 @@ =20 #define RST_NR_PER_BANK 32 =20 +/* Infra global controller reset set register */ +#define INFRA_RST0_SET_OFFSET 0x120 +#define INFRA_RST1_SET_OFFSET 0x130 +#define INFRA_RST2_SET_OFFSET 0x140 +#define INFRA_RST3_SET_OFFSET 0x150 +#define INFRA_RST4_SET_OFFSET 0x730 + /** * enum mtk_reset_version - Version of MediaTek clock reset controller. * @MTK_RST_SIMPLE: Use the same registers for bit set and clear. --=20 2.18.0