From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F3C8C43219 for ; Fri, 20 May 2022 18:16:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352542AbiETSPz (ORCPT ); Fri, 20 May 2022 14:15:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352539AbiETSPq (ORCPT ); Fri, 20 May 2022 14:15:46 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1B70D1900E1; Fri, 20 May 2022 11:15:22 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D13A01480; Fri, 20 May 2022 11:15:21 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2DB9A3F718; Fri, 20 May 2022 11:15:19 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 01/13] perf vendors events arm64: Arm Cortex-A34 Date: Fri, 20 May 2022 19:14:43 +0100 Message-Id: <20220520181455.340344-2-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-A34 Add corresponding common events Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a34.json which is based on PMU event descriptions from the Arm Cortex-A34 Technical Reference Manual. Common event data based on: https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json which is based on PMU event descriptions found in the Arm Architecture Reference Manual: https://developer.arm.com/documentation/ddi0487/ Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-a34/branch.json | 11 ++++++ .../arch/arm64/arm/cortex-a34/bus.json | 17 +++++++++ .../arch/arm64/arm/cortex-a34/cache.json | 32 +++++++++++++++++ .../arch/arm64/arm/cortex-a34/exception.json | 14 ++++++++ .../arm64/arm/cortex-a34/instruction.json | 29 +++++++++++++++ .../arch/arm64/arm/cortex-a34/memory.json | 8 +++++ .../arch/arm64/common-and-microarch.json | 36 +++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 8 files changed, 148 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/excepti= on.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruc= tion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.= json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json new file mode 100644 index 000000000000..ece201718284 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json @@ -0,0 +1,11 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json new file mode 100644 index 000000000000..8a9a95e05c32 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json @@ -0,0 +1,32 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json= b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json new file mode 100644 index 000000000000..27c3fe9c831a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/exception.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.js= on b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json new file mode 100644 index 000000000000..7c018f439206 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/instruction.json @@ -0,0 +1,29 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "LD_RETIRED" + }, + { + "ArchStdEvent": "ST_RETIRED" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json new file mode 100644 index 000000000000..2c319f936957 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a34/memory.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "UNALIGNED_LDST_RETIRED" + }, + { + "ArchStdEvent": "MEM_ACCESS" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json b/t= ools/perf/pmu-events/arch/arm64/common-and-microarch.json index 80d7a70829a0..20923bf10adc 100644 --- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json +++ b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json @@ -35,6 +35,18 @@ "EventName": "L1D_TLB_REFILL", "BriefDescription": "Attributable Level 1 data TLB refill" }, + { + "PublicDescription": "Instruction architecturally executed, condit= ion code check pass, load", + "EventCode": "0x06", + "EventName": "LD_RETIRED", + "BriefDescription": "Instruction architecturally executed, conditi= on code check pass, load" + }, + { + "PublicDescription": "Instruction architecturally executed, condit= ion code check pass, store", + "EventCode": "0x07", + "EventName": "ST_RETIRED", + "BriefDescription": "Instruction architecturally executed, conditi= on code check pass, store" + }, { "PublicDescription": "Instruction architecturally executed", "EventCode": "0x08", @@ -59,6 +71,30 @@ "EventName": "CID_WRITE_RETIRED", "BriefDescription": "Instruction architecturally executed, conditi= on code check pass, write to CONTEXTIDR" }, + { + "PublicDescription": "Instruction architecturally executed, condit= ion code check pass, software change of the PC", + "EventCode": "0x0C", + "EventName": "PC_WRITE_RETIRED", + "BriefDescription": "Instruction architecturally executed, conditi= on code check pass, software change of the PC" + }, + { + "PublicDescription": "Instruction architecturally executed, immedi= ate branch", + "EventCode": "0x0D", + "EventName": "BR_IMMED_RETIRED", + "BriefDescription": "Instruction architecturally executed, immedia= te branch" + }, + { + "PublicDescription": "Instruction architecturally executed, condit= ion code check pass, procedure return", + "EventCode": "0x0E", + "EventName": "BR_RETURN_RETIRED", + "BriefDescription": "Instruction architecturally executed, conditi= on code check pass, procedure return" + }, + { + "PublicDescription": "Instruction architecturally executed, condit= ion code check pass, unaligned", + "EventCode": "0x0F", + "EventName": "UNALIGNED_LDST_RETIRED", + "BriefDescription": "Instruction architecturally executed, conditi= on code check pass, unaligned" + }, { "PublicDescription": "Mispredicted or not predicted branch specula= tively executed", "EventCode": "0x10", diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index b899db48c12a..461bb8b845d6 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -12,6 +12,7 @@ # # #Family-model,Version,Filename,EventType +0x00000000410fd020,v1,arm/cortex-a34,core 0x00000000410fd030,v1,arm/cortex-a53,core 0x00000000420f1000,v1,arm/cortex-a53,core 0x00000000410fd070,v1,arm/cortex-a57-a72,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E651C433EF for ; Fri, 20 May 2022 18:16:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352558AbiETSQY (ORCPT ); Fri, 20 May 2022 14:16:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352544AbiETSPq (ORCPT ); Fri, 20 May 2022 14:15:46 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 102821900F5; Fri, 20 May 2022 11:15:25 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C2C251477; Fri, 20 May 2022 11:15:24 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1B55D3F718; Fri, 20 May 2022 11:15:21 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 02/13] perf vendors events arm64: Arm Cortex-A35 Date: Fri, 20 May 2022 19:14:44 +0100 Message-Id: <20220520181455.340344-3-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-A35 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a35.json which is based on PMU event descriptions from the Arm Cortex-A35 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-a35/branch.json | 11 +++++ .../arch/arm64/arm/cortex-a35/bus.json | 17 +++++++ .../arch/arm64/arm/cortex-a35/cache.json | 32 ++++++++++++++ .../arch/arm64/arm/cortex-a35/exception.json | 14 ++++++ .../arm64/arm/cortex-a35/instruction.json | 44 +++++++++++++++++++ .../arch/arm64/arm/cortex-a35/memory.json | 8 ++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 7 files changed, 127 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/excepti= on.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruc= tion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.= json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json new file mode 100644 index 000000000000..ece201718284 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/branch.json @@ -0,0 +1,11 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json new file mode 100644 index 000000000000..8a9a95e05c32 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/cache.json @@ -0,0 +1,32 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json= b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json new file mode 100644 index 000000000000..27c3fe9c831a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/exception.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.js= on b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json new file mode 100644 index 000000000000..df9f94cfc8d5 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/instruction.json @@ -0,0 +1,44 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "LD_RETIRED" + }, + { + "ArchStdEvent": "ST_RETIRED" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json new file mode 100644 index 000000000000..2c319f936957 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a35/memory.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "UNALIGNED_LDST_RETIRED" + }, + { + "ArchStdEvent": "MEM_ACCESS" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index 461bb8b845d6..98ba02cce0f7 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -15,6 +15,7 @@ 0x00000000410fd020,v1,arm/cortex-a34,core 0x00000000410fd030,v1,arm/cortex-a53,core 0x00000000420f1000,v1,arm/cortex-a53,core +0x00000000410fd040,v1,arm/cortex-a35,core 0x00000000410fd070,v1,arm/cortex-a57-a72,core 0x00000000410fd080,v1,arm/cortex-a57-a72,core 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98258C433FE for ; Fri, 20 May 2022 18:16:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352582AbiETSQ2 (ORCPT ); Fri, 20 May 2022 14:16:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352546AbiETSPq (ORCPT ); Fri, 20 May 2022 14:15:46 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 25A81190D2E; Fri, 20 May 2022 11:15:28 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF25F1515; Fri, 20 May 2022 11:15:27 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0B4073F718; Fri, 20 May 2022 11:15:24 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 03/13] perf vendors events arm64: Arm Cortex-A55 Date: Fri, 20 May 2022 19:14:45 +0100 Message-Id: <20220520181455.340344-4-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-A55 Add corresponding common events Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a55.json which is based on PMU event descriptions from the Arm Cortex-A55 Technical Reference Manual. Common event data based on: https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json which is based on PMU event descriptions found in the Arm Architecture Reference Manual: https://developer.arm.com/documentation/ddi0487/ Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-a55/branch.json | 59 ++++++ .../arch/arm64/arm/cortex-a55/bus.json | 17 ++ .../arch/arm64/arm/cortex-a55/cache.json | 188 ++++++++++++++++++ .../arch/arm64/arm/cortex-a55/exception.json | 20 ++ .../arm64/arm/cortex-a55/instruction.json | 65 ++++++ .../arch/arm64/arm/cortex-a55/memory.json | 17 ++ .../arch/arm64/arm/cortex-a55/pipeline.json | 80 ++++++++ .../arch/arm64/common-and-microarch.json | 6 + tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 9 files changed, 453 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/excepti= on.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruc= tion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/memory.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a55/pipelin= e.json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.json new file mode 100644 index 000000000000..8633d5db42a0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/branch.json @@ -0,0 +1,59 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + }, + { + "PublicDescription": "Predicted conditional branch executed.This e= vent counts when any branch which can be predicted by the conditional predi= ctor is retired. This event still counts when branch prediction is disabled= due to the MMU being off", + "EventCode": "0xC9", + "EventName": "BR_COND_PRED", + "BriefDescription": "Predicted conditional branch executed.This ev= ent counts when any branch which can be predicted by the conditional predic= tor is retired. This event still counts when branch prediction is disabled = due to the MMU being off" + }, + { + "PublicDescription": "Indirect branch mis-predicted.This event cou= nts when any indirect branch which can be predicted by the BTAC is retired,= and has mispredicted for either the condition or the address. This event s= till counts when branch prediction is disabled due to the MMU being off", + "EventCode": "0xCA", + "EventName": "BR_INDIRECT_MIS_PRED", + "BriefDescription": "Indirect branch mis-predicted.This event coun= ts when any indirect branch which can be predicted by the BTAC is retired, = and has mispredicted for either the condition or the address. This event st= ill counts when branch prediction is disabled due to the MMU being off" + }, + { + "PublicDescription": "Indirect branch mis-predicted due to address= mis-compare.This event counts when any indirect branch which can be predic= ted by the BTAC is retired, was taken and correctly predicted the condition= , and has mispredicted the address. This event still counts when branch pre= diction is disabled due to the MMU being off", + "EventCode": "0xCB", + "EventName": "BR_INDIRECT_ADDR_MIS_PRED", + "BriefDescription": "Indirect branch mis-predicted due to address = mis-compare.This event counts when any indirect branch which can be predict= ed by the BTAC is retired, was taken and correctly predicted the condition,= and has mispredicted the address. This event still counts when branch pred= iction is disabled due to the MMU being off" + }, + { + "PublicDescription": "Conditional branch mis-predicted.This event = counts when any branch which can be predicted by the conditional predictor = is retired, and has mis-predicted the condition. This event still counts wh= en branch prediction is disabled due to the MMU being off. Conditional indi= rect branches which correctly predicted the condition but mis-predicted on = the address do not count this event", + "EventCode": "0xCC", + "EventName": "BR_COND_MIS_PRED", + "BriefDescription": "Conditional branch mis-predicted.This event c= ounts when any branch which can be predicted by the conditional predictor i= s retired, and has mis-predicted the condition. This event still counts whe= n branch prediction is disabled due to the MMU being off. Conditional indir= ect branches which correctly predicted the condition but mis-predicted on t= he address do not count this event" + }, + { + "PublicDescription": "Indirect branch with predicted address execu= ted.This event counts when any indirect branch which can be predicted by th= e BTAC is retired, was taken and correctly predicted the condition. This ev= ent still counts when branch prediction is disabled due to the MMU being of= f", + "EventCode": "0xCD", + "EventName": "BR_INDIRECT_ADDR_PRED", + "BriefDescription": "Indirect branch with predicted address execut= ed.This event counts when any indirect branch which can be predicted by the= BTAC is retired, was taken and correctly predicted the condition. This eve= nt still counts when branch prediction is disabled due to the MMU being off" + }, + { + "PublicDescription": "Procedure return with predicted address exec= uted.This event counts when any procedure return which can be predicted by = the CRS is retired, was taken and correctly predicted the condition. This e= vent still counts when branch prediction is disabled due to the MMU being o= ff", + "EventCode": "0xCE", + "EventName": "BR_RETURN_ADDR_PRED", + "BriefDescription": "Procedure return with predicted address execu= ted.This event counts when any procedure return which can be predicted by t= he CRS is retired, was taken and correctly predicted the condition. This ev= ent still counts when branch prediction is disabled due to the MMU being of= f" + }, + { + "PublicDescription": "Procedure return mis-predicted due to addres= s mis-compare.This event counts when any procedure return which can be pred= icted by the CRS is retired, was taken and correctly predicted the conditio= n, and has mispredicted the address. This event still counts when branch pr= ediction is disabled due to the MMU being off", + "EventCode": "0xCF", + "EventName": "BR_RETURN_ADDR_MIS_PRED", + "BriefDescription": "Procedure return mis-predicted due to address= mis-compare.This event counts when any procedure return which can be predi= cted by the CRS is retired, was taken and correctly predicted the condition= , and has mispredicted the address. This event still counts when branch pre= diction is disabled due to the MMU being off" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.json new file mode 100644 index 000000000000..cd684c7ae026 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/cache.json @@ -0,0 +1,188 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L1D_TLB" + }, + { + "ArchStdEvent": "L1I_TLB" + }, + { + "ArchStdEvent": "L3D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L3D_CACHE" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "DTLB_WALK" + }, + { + "ArchStdEvent": "ITLB_WALK" + }, + { + "ArchStdEvent": "LL_CACHE_RD" + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L3D_CACHE_RD" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL_RD" + }, + { + "PublicDescription": "Level 3 cache refill due to prefetch. This e= vent counts any linefills from the hardware prefetcher which cause an alloc= ation into the L3 cache. Note It might not be possible to both distinguish = hardware vs software prefetches and also which prefetches cause an allocati= on. If so, only hardware prefetches should be counted, regardless of whethe= r they allocate. If either the core is configured without a per-core L2 or = the cluster is configured without an L3 cache, this event is not implemente= d", + "EventCode": "0xC0", + "EventName": "L3D_CACHE_REFILL_PREFETCH", + "BriefDescription": "Level 3 cache refill due to prefetch. This ev= ent counts any linefills from the hardware prefetcher which cause an alloca= tion into the L3 cache. Note It might not be possible to both distinguish h= ardware vs software prefetches and also which prefetches cause an allocatio= n. If so, only hardware prefetches should be counted, regardless of whether= they allocate. If either the core is configured without a per-core L2 or t= he cluster is configured without an L3 cache, this event is not implemented" + }, + { + "PublicDescription": "Level 2 cache refill due to prefetch. +//0 I= f the core is configured with a per-core L2 cache: This event does not coun= t. +//0 If the core is configured without a per-core L2 cache: This event c= ounts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. +//= 0 If there is neither a per-core cache nor a cluster cache configured, this= event is not implemented", + "EventCode": "0xC1", + "EventName": "L2D_CACHE_REFILL_PREFETCH", + "BriefDescription": "Level 2 cache refill due to prefetch. +//0 If= the core is configured with a per-core L2 cache: This event does not count= . +//0 If the core is configured without a per-core L2 cache: This event co= unts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. +//0= If there is neither a per-core cache nor a cluster cache configured, this = event is not implemented" + }, + { + "PublicDescription": "Level 1 data cache refill due to prefetch. T= his event counts any linefills from the prefetcher which cause an allocatio= n into the L1 D-cache", + "EventCode": "0xC2", + "EventName": "L1D_CACHE_REFILL_PREFETCH", + "BriefDescription": "Level 1 data cache refill due to prefetch. Th= is event counts any linefills from the prefetcher which cause an allocation= into the L1 D-cache" + }, + { + "PublicDescription": "Level 2 cache write streaming mode. This eve= nt counts for each cycle where the core is in write-streaming mode and not = allocating writes into the L2 cache", + "EventCode": "0xC3", + "EventName": "L2D_WS_MODE", + "BriefDescription": "Level 2 cache write streaming mode. This even= t counts for each cycle where the core is in write-streaming mode and not a= llocating writes into the L2 cache" + }, + { + "PublicDescription": "Level 1 data cache entering write streaming = mode.This event counts for each entry into write-streaming mode", + "EventCode": "0xC4", + "EventName": "L1D_WS_MODE_ENTRY", + "BriefDescription": "Level 1 data cache entering write streaming m= ode.This event counts for each entry into write-streaming mode" + }, + { + "PublicDescription": "Level 1 data cache write streaming mode.This= event counts for each cycle where the core is in write-streaming mode and = not allocating writes into the L1 D-cache", + "EventCode": "0xC5", + "EventName": "L1D_WS_MODE", + "BriefDescription": "Level 1 data cache write streaming mode.This = event counts for each cycle where the core is in write-streaming mode and n= ot allocating writes into the L1 D-cache" + }, + { + "PublicDescription": "Level 3 cache write streaming mode.This even= t counts for each cycle where the core is in write-streaming mode and not a= llocating writes into the L3 cache", + "EventCode": "0xC7", + "EventName": "L3D_WS_MODE", + "BriefDescription": "Level 3 cache write streaming mode.This event= counts for each cycle where the core is in write-streaming mode and not al= locating writes into the L3 cache" + }, + { + "PublicDescription": "Level 2 TLB last-level walk cache access.Thi= s event does not count if the MMU is disabled", + "EventCode": "0xD0", + "EventName": "L2D_LLWALK_TLB", + "BriefDescription": "Level 2 TLB last-level walk cache access.This= event does not count if the MMU is disabled" + }, + { + "PublicDescription": "Level 2 TLB last-level walk cache refill.Thi= s event does not count if the MMU is disabled", + "EventCode": "0xD1", + "EventName": "L2D_LLWALK_TLB_REFILL", + "BriefDescription": "Level 2 TLB last-level walk cache refill.This= event does not count if the MMU is disabled" + }, + { + "PublicDescription": "Level 2 TLB level-2 walk cache access.This e= vent counts accesses to the level-2 walk cache where the last-level walk ca= che has missed. The event only counts when the translation regime of the pa= gewalk uses level 2 descriptors. This event does not count if the MMU is di= sabled", + "EventCode": "0xD2", + "EventName": "L2D_L2WALK_TLB", + "BriefDescription": "Level 2 TLB level-2 walk cache access.This ev= ent counts accesses to the level-2 walk cache where the last-level walk cac= he has missed. The event only counts when the translation regime of the pag= ewalk uses level 2 descriptors. This event does not count if the MMU is dis= abled" + }, + { + "PublicDescription": "Level 2 TLB level-2 walk cache refill.This e= vent does not count if the MMU is disabled", + "EventCode": "0xD3", + "EventName": "L2D_L2WALK_TLB_REFILL", + "BriefDescription": "Level 2 TLB level-2 walk cache refill.This ev= ent does not count if the MMU is disabled" + }, + { + "PublicDescription": "Level 2 TLB IPA cache access. This event cou= nts on each access to the IPA cache. +//0 If a single pagewalk needs to mak= e multiple accesses to the IPA cache, each access is counted. +//0 If stage= 2 translation is disabled, this event does not count", + "EventCode": "0xD4", + "EventName": "L2D_S2_TLB", + "BriefDescription": "Level 2 TLB IPA cache access. This event coun= ts on each access to the IPA cache. +//0 If a single pagewalk needs to make= multiple accesses to the IPA cache, each access is counted. +//0 If stage = 2 translation is disabled, this event does not count" + }, + { + "PublicDescription": "Level 2 TLB IPA cache refill. This event cou= nts on each refill of the IPA cache. +//0 If a single pagewalk needs to mak= e multiple accesses to the IPA cache, each access which causes a refill is = counted. +//0 If stage 2 translation is disabled, this event does not count= ", + "EventCode": "0xD5", + "EventName": "L2D_S2_TLB_REFILL", + "BriefDescription": "Level 2 TLB IPA cache refill. This event coun= ts on each refill of the IPA cache. +//0 If a single pagewalk needs to make= multiple accesses to the IPA cache, each access which causes a refill is c= ounted. +//0 If stage 2 translation is disabled, this event does not count" + }, + { + "PublicDescription": "Level 2 cache stash dropped.This event count= s on each stash request received from the interconnect or ACP, that is targ= eting L2 and gets dropped due to lack of buffer space to hold the request", + "EventCode": "0xD6", + "EventName": "L2D_CACHE_STASH_DROPPED", + "BriefDescription": "Level 2 cache stash dropped.This event counts= on each stash request received from the interconnect or ACP, that is targe= ting L2 and gets dropped due to lack of buffer space to hold the request" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/exception.json= b/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/exception.json new file mode 100644 index 000000000000..99f1ab987709 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/exception.json @@ -0,0 +1,20 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + }, + { + "PublicDescription": "Predecode error", + "EventCode": "0xC6", + "EventName": "PREDECODE_ERROR", + "BriefDescription": "Predecode error" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruction.js= on b/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruction.json new file mode 100644 index 000000000000..e762fab9e2d8 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/instruction.json @@ -0,0 +1,65 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "LD_RETIRED" + }, + { + "ArchStdEvent": "ST_RETIRED" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_RETIRED" + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "PC_WRITE_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/memory.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a55/memory.json new file mode 100644 index 000000000000..d9229173d189 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/memory.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "UNALIGNED_LDST_RETIRED" + }, + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "REMOTE_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/pipeline.json = b/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/pipeline.json new file mode 100644 index 000000000000..6c6b5869cf70 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/pipeline.json @@ -0,0 +1,80 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + }, + { + "PublicDescription": "No operation issued due to the frontend, cac= he miss.This event counts every cycle the DPU IQ is empty and there is an i= nstruction cache miss being processed", + "EventCode": "0xE1", + "EventName": "STALL_FRONTEND_CACHE", + "BriefDescription": "No operation issued due to the frontend, cach= e miss.This event counts every cycle the DPU IQ is empty and there is an in= struction cache miss being processed" + }, + { + "PublicDescription": "No operation issued due to the frontend, TLB= miss.This event counts every cycle the DPU IQ is empty and there is an ins= truction L1 TLB miss being processed", + "EventCode": "0xE2", + "EventName": "STALL_FRONTEND_TLB", + "BriefDescription": "No operation issued due to the frontend, TLB = miss.This event counts every cycle the DPU IQ is empty and there is an inst= ruction L1 TLB miss being processed" + }, + { + "PublicDescription": "No operation issued due to the frontend, pre= -decode error.This event counts every cycle the DPU IQ is empty and there i= s a pre-decode error being processed", + "EventCode": "0xE3", + "EventName": "STALL_FRONTEND_PDERR", + "BriefDescription": "No operation issued due to the frontend, pre-= decode error.This event counts every cycle the DPU IQ is empty and there is= a pre-decode error being processed" + }, + { + "PublicDescription": "No operation issued due to the backend inter= lock.This event counts every cycle that issue is stalled and there is an in= terlock. Stall cycles due to a stall in Wr (typically awaiting load data) a= re excluded", + "EventCode": "0xE4", + "EventName": "STALL_BACKEND_ILOCK", + "BriefDescription": "No operation issued due to the backend interl= ock.This event counts every cycle that issue is stalled and there is an int= erlock. Stall cycles due to a stall in Wr (typically awaiting load data) ar= e excluded" + }, + { + "PublicDescription": "No operation issued due to the backend, inte= rlock, AGU.This event counts every cycle that issue is stalled and there is= an interlock that is due to a load/store instruction waiting for data to c= alculate the address in the AGU. Stall cycles due to a stall in Wr (typical= ly awaiting load data) are excluded", + "EventCode": "0xE5", + "EventName": "STALL_BACKEND_ILOCK_AGU", + "BriefDescription": "No operation issued due to the backend, inter= lock, AGU.This event counts every cycle that issue is stalled and there is = an interlock that is due to a load/store instruction waiting for data to ca= lculate the address in the AGU. Stall cycles due to a stall in Wr (typicall= y awaiting load data) are excluded" + }, + { + "PublicDescription": "No operation issued due to the backend, inte= rlock, FPU.This event counts every cycle that issue is stalled and there is= an interlock that is due to an FPU/NEON instruction. Stall cycles due to a= stall in the Wr stage (typically awaiting load data) are excluded", + "EventCode": "0xE6", + "EventName": "STALL_BACKEND_ILOCK_FPU", + "BriefDescription": "No operation issued due to the backend, inter= lock, FPU.This event counts every cycle that issue is stalled and there is = an interlock that is due to an FPU/NEON instruction. Stall cycles due to a = stall in the Wr stage (typically awaiting load data) are excluded" + }, + { + "PublicDescription": "No operation issued due to the backend, load= .This event counts every cycle there is a stall in the Wr stage due to a lo= ad", + "EventCode": "0xE7", + "EventName": "STALL_BACKEND_LD", + "BriefDescription": "No operation issued due to the backend, load.= This event counts every cycle there is a stall in the Wr stage due to a loa= d" + }, + { + "PublicDescription": "No operation issued due to the backend, stor= e.This event counts every cycle there is a stall in the Wr stage due to a s= tore", + "EventCode": "0xE8", + "EventName": "STALL_BACKEND_ST", + "BriefDescription": "No operation issued due to the backend, store= .This event counts every cycle there is a stall in the Wr stage due to a st= ore" + }, + { + "PublicDescription": "No operation issued due to the backend, load= , cache miss.This event counts every cycle there is a stall in the Wr stage= due to a load which is waiting on data (due to missing the cache or being = non-cacheable)", + "EventCode": "0xE9", + "EventName": "STALL_BACKEND_LD_CACHE", + "BriefDescription": "No operation issued due to the backend, load,= cache miss.This event counts every cycle there is a stall in the Wr stage = due to a load which is waiting on data (due to missing the cache or being n= on-cacheable)" + }, + { + "PublicDescription": "No operation issued due to the backend, load= , TLB miss.This event counts every cycle there is a stall in the Wr stage d= ue to a load which has missed in the L1 TLB", + "EventCode": "0xEA", + "EventName": "STALL_BACKEND_LD_TLB", + "BriefDescription": "No operation issued due to the backend, load,= TLB miss.This event counts every cycle there is a stall in the Wr stage du= e to a load which has missed in the L1 TLB" + }, + { + "PublicDescription": "No operation issued due to the backend, stor= e, STB full.This event counts every cycle there is a stall in the Wr stage = due to a store which is waiting due to the STB being full", + "EventCode": "0xEB", + "EventName": "STALL_BACKEND_ST_STB", + "BriefDescription": "No operation issued due to the backend, store= , STB full.This event counts every cycle there is a stall in the Wr stage d= ue to a store which is waiting due to the STB being full" + }, + { + "PublicDescription": "No operation issued due to the backend, stor= e, TLB miss.This event counts every cycle there is a stall in the Wr stage = due to a store which has missed in the L1 TLB", + "EventCode": "0xEC", + "EventName": "STALL_BACKEND_ST_TLB", + "BriefDescription": "No operation issued due to the backend, store= , TLB miss.This event counts every cycle there is a stall in the Wr stage d= ue to a store which has missed in the L1 TLB" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json b/t= ools/perf/pmu-events/arch/arm64/common-and-microarch.json index 20923bf10adc..c50b231ce03b 100644 --- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json +++ b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json @@ -293,6 +293,12 @@ "EventName": "LL_CACHE_MISS_RD", "BriefDescription": "Last level cache miss, read" }, + { + "PublicDescription": "Attributable memory read access to another s= ocket in a multi-socket system", + "EventCode": "0x38", + "EventName": "REMOTE_ACCESS_RD", + "BriefDescription": "Attributable memory read access to another so= cket in a multi-socket system" + }, { "PublicDescription": "Level 1 data cache long-latency read miss. = The counter counts each memory read access counted by L1D_CACHE that incurs= additional latency because it returns data from outside the Level 1 data o= r unified cache of this processing element.", "EventCode": "0x39", diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index 98ba02cce0f7..94bf26dda367 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -16,6 +16,7 @@ 0x00000000410fd030,v1,arm/cortex-a53,core 0x00000000420f1000,v1,arm/cortex-a53,core 0x00000000410fd040,v1,arm/cortex-a35,core +0x00000000410fd050,v1,arm/cortex-a55,core 0x00000000410fd070,v1,arm/cortex-a57-a72,core 0x00000000410fd080,v1,arm/cortex-a57-a72,core 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CECA9C4332F for ; Fri, 20 May 2022 18:16:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349284AbiETSQS (ORCPT ); Fri, 20 May 2022 14:16:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39804 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352548AbiETSPq (ORCPT ); Fri, 20 May 2022 14:15:46 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2C4AD1912CC; Fri, 20 May 2022 11:15:31 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DDCE01480; Fri, 20 May 2022 11:15:30 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 18C7B3F718; Fri, 20 May 2022 11:15:27 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 04/13] perf vendors events arm64: Arm Cortex-A510 Date: Fri, 20 May 2022 19:14:46 +0100 Message-Id: <20220520181455.340344-5-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-A510 Add corresponding common events Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a510.json which is based on PMU event descriptions from the Arm Cortex-A510 Technical Reference Manual. Common event data based on: https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json which is based on PMU event descriptions found in the Arm Architecture Reference Manual: https://developer.arm.com/documentation/ddi0487/ Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-a510/branch.json | 59 ++++++ .../arch/arm64/arm/cortex-a510/bus.json | 17 ++ .../arch/arm64/arm/cortex-a510/cache.json | 182 ++++++++++++++++++ .../arch/arm64/arm/cortex-a510/exception.json | 14 ++ .../arm64/arm/cortex-a510/instruction.json | 95 +++++++++ .../arch/arm64/arm/cortex-a510/memory.json | 32 +++ .../arch/arm64/arm/cortex-a510/pipeline.json | 107 ++++++++++ .../arch/arm64/arm/cortex-a510/pmu.json | 8 + .../arch/arm64/arm/cortex-a510/trace.json | 32 +++ .../arch/arm64/common-and-microarch.json | 18 ++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 11 files changed, 565 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch= .json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.js= on create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/except= ion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instru= ction.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory= .json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeli= ne.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.js= on create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.= json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json b= /tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json new file mode 100644 index 000000000000..411fcbdbd7e6 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/branch.json @@ -0,0 +1,59 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + }, + { + "PublicDescription": "Predicted conditional branch executed. This = event counts when any branch that the conditional predictor can predict is = retired. This event still counts when branch prediction is disabled due to = the Memory Management Unit (MMU) being off", + "EventCode": "0xC9", + "EventName": "BR_COND_PRED", + "BriefDescription": "Predicted conditional branch executed. This e= vent counts when any branch that the conditional predictor can predict is r= etired. This event still counts when branch prediction is disabled due to t= he Memory Management Unit (MMU) being off" + }, + { + "PublicDescription": "Indirect branch mispredicted. This event cou= nts when any indirect branch that the Branch Target Address Cache (BTAC) ca= n predict is retired and has mispredicted either the condition or the addre= ss. This event still counts when branch prediction is disabled due to the M= MU being off", + "EventCode": "0xCA", + "EventName": "BR_INDIRECT_MIS_PRED", + "BriefDescription": "Indirect branch mispredicted. This event coun= ts when any indirect branch that the Branch Target Address Cache (BTAC) can= predict is retired and has mispredicted either the condition or the addres= s. This event still counts when branch prediction is disabled due to the MM= U being off" + }, + { + "PublicDescription": "Indirect branch mispredicted due to address = miscompare. This event counts when any indirect branch that the BTAC can pr= edict is retired, was taken, correctly predicted the condition, and has mis= predicted the address. This event still counts when branch prediction is di= sabled due to the MMU being off", + "EventCode": "0xCB", + "EventName": "BR_INDIRECT_ADDR_MIS_PRED", + "BriefDescription": "Indirect branch mispredicted due to address m= iscompare. This event counts when any indirect branch that the BTAC can pre= dict is retired, was taken, correctly predicted the condition, and has misp= redicted the address. This event still counts when branch prediction is dis= abled due to the MMU being off" + }, + { + "PublicDescription": "Conditional branch mispredicted. This event = counts when any branch that the conditional predictor can predict is retire= d and has mispredicted the condition. This event still counts when branch p= rediction is disabled due to the MMU being off. Conditional indirect branch= es that correctly predict the condition but mispredict the address do not c= ount", + "EventCode": "0xCC", + "EventName": "BR_COND_MIS_PRED", + "BriefDescription": "Conditional branch mispredicted. This event c= ounts when any branch that the conditional predictor can predict is retired= and has mispredicted the condition. This event still counts when branch pr= ediction is disabled due to the MMU being off. Conditional indirect branche= s that correctly predict the condition but mispredict the address do not co= unt" + }, + { + "PublicDescription": "Indirect branch with predicted address execu= ted. This event counts when any indirect branch that the BTAC can predict i= s retired, was taken, and correctly predicted the condition. This event sti= ll counts when branch prediction is disabled due to the MMU being off", + "EventCode": "0xCD", + "EventName": "BR_INDIRECT_ADDR_PRED", + "BriefDescription": "Indirect branch with predicted address execut= ed. This event counts when any indirect branch that the BTAC can predict is= retired, was taken, and correctly predicted the condition. This event stil= l counts when branch prediction is disabled due to the MMU being off" + }, + { + "PublicDescription": "Procedure return with predicted address exec= uted. This event counts when any procedure return that the call-return stac= k can predict is retired, was taken, and correctly predicted the condition.= This event still counts when branch prediction is disabled due to the MMU = being off", + "EventCode": "0xCE", + "EventName": "BR_RETURN_ADDR_PRED", + "BriefDescription": "Procedure return with predicted address execu= ted. This event counts when any procedure return that the call-return stack= can predict is retired, was taken, and correctly predicted the condition. = This event still counts when branch prediction is disabled due to the MMU b= eing off" + }, + { + "PublicDescription": "Procedure return mispredicted due to address= miscompare. This event counts when any procedure return that the call-retu= rn stack can predict is retired, was taken, correctly predicted the conditi= on, and has mispredicted the address. This event still counts when branch p= rediction is disabled due to the MMU being off", + "EventCode": "0xCF", + "EventName": "BR_RETURN_ADDR_MIS_PRED", + "BriefDescription": "Procedure return mispredicted due to address = miscompare. This event counts when any procedure return that the call-retur= n stack can predict is retired, was taken, correctly predicted the conditio= n, and has mispredicted the address. This event still counts when branch pr= ediction is disabled due to the MMU being off" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json b/to= ols/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json new file mode 100644 index 000000000000..27cd913e186b --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/cache.json @@ -0,0 +1,182 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L1D_TLB" + }, + { + "ArchStdEvent": "L1I_TLB" + }, + { + "ArchStdEvent": "L3D_CACHE" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "DTLB_WALK" + }, + { + "ArchStdEvent": "ITLB_WALK" + }, + { + "ArchStdEvent": "LL_CACHE_RD" + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_LMISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L3D_CACHE_RD" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL_RD" + }, + { + "PublicDescription": "L2 cache refill due to prefetch. If the comp= lex is configured with a per-complex L2 cache, this event does not count. I= f the complex is configured without a per-complex L2 cache, this event coun= ts the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If nei= ther a per-complex cache or a cluster cache is configured, this event is no= t implemented", + "EventCode": "0xC1", + "EventName": "L2D_CACHE_REFILL_PREFETCH", + "BriefDescription": "L2 cache refill due to prefetch. If the compl= ex is configured with a per-complex L2 cache, this event does not count. If= the complex is configured without a per-complex L2 cache, this event count= s the cluster cache event, as defined by L3D_CACHE_REFILL_PREFETCH. If neit= her a per-complex cache or a cluster cache is configured, this event is not= implemented" + }, + { + "PublicDescription": "L1 data cache refill due to prefetch. This e= vent counts any linefills from the prefetcher that cause an allocation into= the L1 data cache", + "EventCode": "0xC2", + "EventName": "L1D_CACHE_REFILL_PREFETCH", + "BriefDescription": "L1 data cache refill due to prefetch. This ev= ent counts any linefills from the prefetcher that cause an allocation into = the L1 data cache" + }, + { + "PublicDescription": "L2 cache write streaming mode. This event co= unts for each cycle where the core is in write streaming mode and is not al= locating writes into the L2 cache", + "EventCode": "0xC3", + "EventName": "L2D_WS_MODE", + "BriefDescription": "L2 cache write streaming mode. This event cou= nts for each cycle where the core is in write streaming mode and is not all= ocating writes into the L2 cache" + }, + { + "PublicDescription": "L1 data cache entering write streaming mode.= This event counts for each entry into write streaming mode", + "EventCode": "0xC4", + "EventName": "L1D_WS_MODE_ENTRY", + "BriefDescription": "L1 data cache entering write streaming mode. = This event counts for each entry into write streaming mode" + }, + { + "PublicDescription": "L1 data cache write streaming mode. This eve= nt counts for each cycle where the core is in write streaming mode and is n= ot allocating writes into the L1 data cache", + "EventCode": "0xC5", + "EventName": "L1D_WS_MODE", + "BriefDescription": "L1 data cache write streaming mode. This even= t counts for each cycle where the core is in write streaming mode and is no= t allocating writes into the L1 data cache" + }, + { + "PublicDescription": "L3 cache write streaming mode. This event co= unts for each cycle where the core is in write streaming mode and is not al= locating writes into the L3 cache", + "EventCode": "0xC7", + "EventName": "L3D_WS_MODE", + "BriefDescription": "L3 cache write streaming mode. This event cou= nts for each cycle where the core is in write streaming mode and is not all= ocating writes into the L3 cache" + }, + { + "PublicDescription": "Last level cache write streaming mode. This = event counts for each cycle where the core is in write streaming mode and i= s not allocating writes into the system cache", + "EventCode": "0xC8", + "EventName": "LL_WS_MODE", + "BriefDescription": "Last level cache write streaming mode. This e= vent counts for each cycle where the core is in write streaming mode and is= not allocating writes into the system cache" + }, + { + "PublicDescription": "L2 TLB walk cache access. This event does no= t count if the MMU is disabled", + "EventCode": "0xD0", + "EventName": "L2D_WALK_TLB", + "BriefDescription": "L2 TLB walk cache access. This event does not= count if the MMU is disabled" + }, + { + "PublicDescription": "L2 TLB walk cache refill. This event does no= t count if the MMU is disabled", + "EventCode": "0xD1", + "EventName": "L2D_WALK_TLB_REFILL", + "BriefDescription": "L2 TLB walk cache refill. This event does not= count if the MMU is disabled" + }, + { + "PublicDescription": "L2 TLB IPA cache access. This event counts o= n each access to the IPA cache. If a single translation table walk needs to= make multiple accesses to the IPA cache, each access is counted. If stage = 2 translation is disabled, this event does not count", + "EventCode": "0xD4", + "EventName": "L2D_S2_TLB", + "BriefDescription": "L2 TLB IPA cache access. This event counts on= each access to the IPA cache. If a single translation table walk needs to = make multiple accesses to the IPA cache, each access is counted. If stage 2= translation is disabled, this event does not count" + }, + { + "PublicDescription": "L2 TLB IPA cache refill. This event counts o= n each refill of the IPA cache. If a single translation table walk needs to= make multiple accesses to the IPA cache, each access that causes a refill = is counted. If stage 2 translation is disabled, this event does not count", + "EventCode": "0xD5", + "EventName": "L2D_S2_TLB_REFILL", + "BriefDescription": "L2 TLB IPA cache refill. This event counts on= each refill of the IPA cache. If a single translation table walk needs to = make multiple accesses to the IPA cache, each access that causes a refill i= s counted. If stage 2 translation is disabled, this event does not count" + }, + { + "PublicDescription": "L2 cache stash dropped. This event counts on= each stash request that is received from the interconnect or the Accelerat= or Coherency Port (ACP), that targets L2 cache and is dropped due to lack o= f buffer space to hold the request", + "EventCode": "0xD6", + "EventName": "L2D_CACHE_STASH_DROPPED", + "BriefDescription": "L2 cache stash dropped. This event counts on = each stash request that is received from the interconnect or the Accelerato= r Coherency Port (ACP), that targets L2 cache and is dropped due to lack of= buffer space to hold the request" + }, + { + "ArchStdEvent": "L1I_CACHE_LMISS" + }, + { + "ArchStdEvent": "L2D_CACHE_LMISS_RD" + }, + { + "ArchStdEvent": "L3D_CACHE_LMISS_RD" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.jso= n b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json new file mode 100644 index 000000000000..27c3fe9c831a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/exception.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.j= son b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json new file mode 100644 index 000000000000..3039d03412df --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/instruction.json @@ -0,0 +1,95 @@ +[ + { + "ArchStdEvent": "LD_RETIRED" + }, + { + "ArchStdEvent": "ST_RETIRED" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_RETIRED" + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED" + }, + { + "ArchStdEvent": "OP_RETIRED" + }, + { + "ArchStdEvent": "OP_SPEC" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "PC_WRITE_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "SVE_INST_RETIRED" + }, + { + "ArchStdEvent": "SVE_INST_SPEC" + }, + { + "ArchStdEvent": "FP_HP_SPEC" + }, + { + "ArchStdEvent": "FP_SP_SPEC" + }, + { + "ArchStdEvent": "FP_DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT8_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT16_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT32_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT64_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json b= /tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json new file mode 100644 index 000000000000..38f459502514 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/memory.json @@ -0,0 +1,32 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "REMOTE_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "LDST_ALIGN_LAT" + }, + { + "ArchStdEvent": "LD_ALIGN_LAT" + }, + { + "ArchStdEvent": "ST_ALIGN_LAT" + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED" + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json= b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json new file mode 100644 index 000000000000..325daaa7b809 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pipeline.json @@ -0,0 +1,107 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + }, + { + "ArchStdEvent": "STALL" + }, + { + "ArchStdEvent": "STALL_SLOT_BACKEND" + }, + { + "ArchStdEvent": "STALL_SLOT_FRONTEND" + }, + { + "ArchStdEvent": "STALL_SLOT" + }, + { + "PublicDescription": "No operation issued due to the frontend, cac= he miss. This event counts every cycle that the Data Processing Unit (DPU) = instruction queue is empty and there is an instruction cache miss being pro= cessed", + "EventCode": "0xE1", + "EventName": "STALL_FRONTEND_CACHE", + "BriefDescription": "No operation issued due to the frontend, cach= e miss. This event counts every cycle that the Data Processing Unit (DPU) i= nstruction queue is empty and there is an instruction cache miss being proc= essed" + }, + { + "PublicDescription": "No operation issued due to the frontend, TLB= miss. This event counts every cycle that the DPU instruction queue is empt= y and there is an instruction L1 TLB miss being processed", + "EventCode": "0xE2", + "EventName": "STALL_FRONTEND_TLB", + "BriefDescription": "No operation issued due to the frontend, TLB = miss. This event counts every cycle that the DPU instruction queue is empty= and there is an instruction L1 TLB miss being processed" + }, + { + "PublicDescription": "No operation issued due to the frontend, pre= -decode error", + "EventCode": "0xE3", + "EventName": "STALL_FRONTEND_PDERR", + "BriefDescription": "No operation issued due to the frontend, pre-= decode error" + }, + { + "PublicDescription": "No operation issued due to the backend inter= lock. This event counts every cycle where the issue of an operation is stal= led and there is an interlock. Stall cycles due to a stall in the Wr stage = are excluded", + "EventCode": "0xE4", + "EventName": "STALL_BACKEND_ILOCK", + "BriefDescription": "No operation issued due to the backend interl= ock. This event counts every cycle where the issue of an operation is stall= ed and there is an interlock. Stall cycles due to a stall in the Wr stage a= re excluded" + }, + { + "PublicDescription": "No operation issued due to the backend, addr= ess interlock. This event counts every cycle where the issue of an operatio= n is stalled and there is an interlock on an address operand. This type of = interlock is caused by a load/store instruction waiting for data to calcula= te the address. Stall cycles due to a stall in the Wr stage are excluded", + "EventCode": "0xE5", + "EventName": "STALL_BACKEND_ILOCK_ADDR", + "BriefDescription": "No operation issued due to the backend, addre= ss interlock. This event counts every cycle where the issue of an operation= is stalled and there is an interlock on an address operand. This type of i= nterlock is caused by a load/store instruction waiting for data to calculat= e the address. Stall cycles due to a stall in the Wr stage are excluded" + }, + { + "PublicDescription": "No operation issued due to the backend, inte= rlock, or the Vector Processing Unit (VPU). This event counts every cycle w= here there is a stall or an interlock that is caused by a VPU instruction. = Stall cycles due to a stall in the Wr stage are excluded", + "EventCode": "0xE6", + "EventName": "STALL_BACKEND_ILOCK_VPU", + "BriefDescription": "No operation issued due to the backend, inter= lock, or the Vector Processing Unit (VPU). This event counts every cycle wh= ere there is a stall or an interlock that is caused by a VPU instruction. S= tall cycles due to a stall in the Wr stage are excluded" + }, + { + "PublicDescription": "No operation issued due to the backend, load= . This event counts every cycle where there is a stall in the Wr stage due = to a load", + "EventCode": "0xE7", + "EventName": "STALL_BACKEND_LD", + "BriefDescription": "No operation issued due to the backend, load.= This event counts every cycle where there is a stall in the Wr stage due t= o a load" + }, + { + "PublicDescription": "No operation issued due to the backend, stor= e. This event counts every cycle where there is a stall in the Wr stage due= to a store", + "EventCode": "0xE8", + "EventName": "STALL_BACKEND_ST", + "BriefDescription": "No operation issued due to the backend, store= . This event counts every cycle where there is a stall in the Wr stage due = to a store" + }, + { + "PublicDescription": "No operation issued due to the backend, load= , cache miss. This event counts every cycle where there is a stall in the W= r stage due to a load that is waiting on data. The event counts for stalls = that are caused by missing the cache or where the data is Non-cacheable", + "EventCode": "0xE9", + "EventName": "STALL_BACKEND_LD_CACHE", + "BriefDescription": "No operation issued due to the backend, load,= cache miss. This event counts every cycle where there is a stall in the Wr= stage due to a load that is waiting on data. The event counts for stalls t= hat are caused by missing the cache or where the data is Non-cacheable" + }, + { + "PublicDescription": "No operation issued due to the backend, load= , TLB miss. This event counts every cycle where there is a stall in the Wr = stage due to a load that misses in the L1 TLB", + "EventCode": "0xEA", + "EventName": "STALL_BACKEND_LD_TLB", + "BriefDescription": "No operation issued due to the backend, load,= TLB miss. This event counts every cycle where there is a stall in the Wr s= tage due to a load that misses in the L1 TLB" + }, + { + "PublicDescription": "No operation issued due to the backend, stor= e, Store Buffer (STB) full. This event counts every cycle where there is a = stall in the Wr stage because of a store operation that is waiting due to t= he STB being full", + "EventCode": "0xEB", + "EventName": "STALL_BACKEND_ST_STB", + "BriefDescription": "No operation issued due to the backend, store= , Store Buffer (STB) full. This event counts every cycle where there is a s= tall in the Wr stage because of a store operation that is waiting due to th= e STB being full" + }, + { + "PublicDescription": "No operation issued due to the backend, stor= e, TLB miss. This event counts every cycle where there is a stall in the Wr= stage because of a store operation that has missed in the L1 TLB", + "EventCode": "0xEC", + "EventName": "STALL_BACKEND_ST_TLB", + "BriefDescription": "No operation issued due to the backend, store= , TLB miss. This event counts every cycle where there is a stall in the Wr = stage because of a store operation that has missed in the L1 TLB" + }, + { + "PublicDescription": "No operation issued due to the backend, VPU = hazard. This event counts every cycle where the core stalls due to contenti= on for the VPU with the other core", + "EventCode": "0xED", + "EventName": "STALL_BACKEND_VPU_HAZARD", + "BriefDescription": "No operation issued due to the backend, VPU h= azard. This event counts every cycle where the core stalls due to contentio= n for the VPU with the other core" + }, + { + "PublicDescription": "Issue slot not issued due to interlock. For = each cycle, this event counts each dispatch slot that does not issue due to= an interlock", + "EventCode": "0xEE", + "EventName": "STALL_SLOT_BACKEND_ILOCK", + "BriefDescription": "Issue slot not issued due to interlock. For e= ach cycle, this event counts each dispatch slot that does not issue due to = an interlock" + }, + { + "ArchStdEvent": "STALL_BACKEND_MEM" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json b/to= ols/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json new file mode 100644 index 000000000000..d8b7b9f9e5fa --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/pmu.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "PMU_OVFS" + }, + { + "ArchStdEvent": "PMU_HOVFS" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json new file mode 100644 index 000000000000..33672a8711d4 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/trace.json @@ -0,0 +1,32 @@ +[ + { + "ArchStdEvent": "TRB_WRAP" + }, + { + "ArchStdEvent": "TRB_TRIG" + }, + { + "ArchStdEvent": "TRCEXTOUT0" + }, + { + "ArchStdEvent": "TRCEXTOUT1" + }, + { + "ArchStdEvent": "TRCEXTOUT2" + }, + { + "ArchStdEvent": "TRCEXTOUT3" + }, + { + "ArchStdEvent": "CTI_TRIGOUT4" + }, + { + "ArchStdEvent": "CTI_TRIGOUT5" + }, + { + "ArchStdEvent": "CTI_TRIGOUT6" + }, + { + "ArchStdEvent": "CTI_TRIGOUT7" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json b/t= ools/perf/pmu-events/arch/arm64/common-and-microarch.json index c50b231ce03b..876b51dae92e 100644 --- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json +++ b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json @@ -401,6 +401,24 @@ "EventName": "TRB_WRAP", "BriefDescription": "Trace buffer current write pointer wrapped" }, + { + "PublicDescription": "PMU overflow, counters accessible to EL1 and= EL0", + "EventCode": "0x400D", + "EventName": "PMU_OVFS", + "BriefDescription": "PMU overflow, counters accessible to EL1 and = EL0" + }, + { + "PublicDescription": "Trace buffer Trigger Event", + "EventCode": "0x400E", + "EventName": "TRB_TRIG", + "BriefDescription": "Trace buffer Trigger Event" + }, + { + "PublicDescription": "PMU overflow, counters reserved for use by E= L2", + "EventCode": "0x400F", + "EventName": "PMU_HOVFS", + "BriefDescription": "PMU overflow, counters reserved for use by EL= 2" + }, { "PublicDescription": "PE Trace Unit external output 0", "EventCode": "0x4010", diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index 94bf26dda367..6988797359c2 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -22,6 +22,7 @@ 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core 0x00000000410fd400,v1,arm/neoverse-v1,core +0x00000000410fd460,v1,arm/cortex-a510,core 0x00000000410fd490,v1,arm/neoverse-n2,core 0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000430f0af0,v1,cavium/thunderx2,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80D1FC433FE for ; Fri, 20 May 2022 18:17:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352607AbiETSRB (ORCPT ); Fri, 20 May 2022 14:17:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352567AbiETSPs (ORCPT ); Fri, 20 May 2022 14:15:48 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id DF11B1912DA; Fri, 20 May 2022 11:15:33 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B24E1477; Fri, 20 May 2022 11:15:33 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 232D13F718; Fri, 20 May 2022 11:15:31 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 05/13] perf vendors events arm64: Arm Cortex-A65 Date: Fri, 20 May 2022 19:14:47 +0100 Message-Id: <20220520181455.340344-6-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-A65 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a65.json which is based on PMU event descriptions from the Arm Cortex-A65 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-a65/branch.json | 17 ++ .../arch/arm64/arm/cortex-a65/bus.json | 17 ++ .../arch/arm64/arm/cortex-a65/cache.json | 236 ++++++++++++++++++ .../arch/arm64/arm/cortex-a65/dpu.json | 32 +++ .../arch/arm64/arm/cortex-a65/exception.json | 14 ++ .../arch/arm64/arm/cortex-a65/ifu.json | 122 +++++++++ .../arm64/arm/cortex-a65/instruction.json | 71 ++++++ .../arch/arm64/arm/cortex-a65/memory.json | 35 +++ .../arch/arm64/arm/cortex-a65/pipeline.json | 8 + tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 10 files changed, 553 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/branch.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/cache.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/dpu.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/excepti= on.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/ifu.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/instruc= tion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/memory.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a65/pipelin= e.json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/branch.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a65/branch.json new file mode 100644 index 000000000000..2f2d137f5f55 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/branch.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/bus.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a65/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/cache.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-a65/cache.json new file mode 100644 index 000000000000..118c5cb0674b --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/cache.json @@ -0,0 +1,236 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L1D_TLB" + }, + { + "ArchStdEvent": "L1I_TLB" + }, + { + "ArchStdEvent": "L3D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L3D_CACHE" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "DTLB_WALK" + }, + { + "ArchStdEvent": "ITLB_WALK" + }, + { + "ArchStdEvent": "LL_CACHE_RD" + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L3D_CACHE_RD" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL_RD" + }, + { + "PublicDescription": "Merge in the store buffer", + "EventCode": "0xC0", + "EventName": "STB_STALL", + "BriefDescription": "Merge in the store buffer" + }, + { + "PublicDescription": "Level 1 data cache refill started due to pre= fetch. Counts any linefills from the prefetcher which cause an allocation i= nto the L1 D-cache", + "EventCode": "0xC3", + "EventName": "L1D_PREF_LINE_FILL", + "BriefDescription": "Level 1 data cache refill started due to pref= etch. Counts any linefills from the prefetcher which cause an allocation in= to the L1 D-cache" + }, + { + "PublicDescription": "Level 2 cache refill due to prefetch. +//0 I= f the core is configured with a per-core L2 cache: This event does not coun= t. +//0 If the core is configured without a per-core L2 cache: This event c= ounts the cluster cache event, as defined by L3_PREF_LINE_FILL. +//0 If the= re is neither a per-core cache nor a cluster cache configured, this event i= s not implemented", + "EventCode": "0xC4", + "EventName": "L2D_PREF_LINE_FILL", + "BriefDescription": "Level 2 cache refill due to prefetch. +//0 If= the core is configured with a per-core L2 cache: This event does not count= . +//0 If the core is configured without a per-core L2 cache: This event co= unts the cluster cache event, as defined by L3_PREF_LINE_FILL. +//0 If ther= e is neither a per-core cache nor a cluster cache configured, this event is= not implemented" + }, + { + "PublicDescription": "Level 3 cache refill due to prefetch. This e= vent counts any linefills from the hardware prefetcher which cause an alloc= ation into the L3 cache. Note It might not be possible to distinguish betwe= en both hardware and software prefetches and also which prefetches cause an= allocation. If so, only hardware prefetches should be counted, regardless = of whether they allocate. If either the core is configured without a per-co= re L2 or the cluster is configured without an L3 cache, this event is not i= mplemented", + "EventCode": "0xC5", + "EventName": "L3_PREF_LINE_FILL", + "BriefDescription": "Level 3 cache refill due to prefetch. This ev= ent counts any linefills from the hardware prefetcher which cause an alloca= tion into the L3 cache. Note It might not be possible to distinguish betwee= n both hardware and software prefetches and also which prefetches cause an = allocation. If so, only hardware prefetches should be counted, regardless o= f whether they allocate. If either the core is configured without a per-cor= e L2 or the cluster is configured without an L3 cache, this event is not im= plemented" + }, + { + "PublicDescription": "L1D entering write stream mode", + "EventCode": "0xC6", + "EventName": "L1D_WS_MODE_ENTER", + "BriefDescription": "L1D entering write stream mode" + }, + { + "PublicDescription": "L1D is in write stream mode", + "EventCode": "0xC7", + "EventName": "L1D_WS_MODE", + "BriefDescription": "L1D is in write stream mode" + }, + { + "PublicDescription": "Level 2 cache write streaming mode. This eve= nt counts for each cycle where the core is in write-streaming mode and not = allocating writes into the L2 cache", + "EventCode": "0xC8", + "EventName": "L2D_WS_MODE", + "BriefDescription": "Level 2 cache write streaming mode. This even= t counts for each cycle where the core is in write-streaming mode and not a= llocating writes into the L2 cache" + }, + { + "PublicDescription": "Level 3 cache write streaming mode. This eve= nt counts for each cycle where the core is in write-streaming mode and not = allocating writes into the L3 cache", + "EventCode": "0xC9", + "EventName": "L3D_WS_MODE", + "BriefDescription": "Level 3 cache write streaming mode. This even= t counts for each cycle where the core is in write-streaming mode and not a= llocating writes into the L3 cache" + }, + { + "PublicDescription": "Level 2 TLB last-level walk cache access. Th= is event does not count if the MMU is disabled", + "EventCode": "0xCA", + "EventName": "TLB_L2TLB_LLWALK_ACCESS", + "BriefDescription": "Level 2 TLB last-level walk cache access. Thi= s event does not count if the MMU is disabled" + }, + { + "PublicDescription": "Level 2 TLB last-level walk cache refill. Th= is event does not count if the MMU is disabled", + "EventCode": "0xCB", + "EventName": "TLB_L2TLB_LLWALK_REFILL", + "BriefDescription": "Level 2 TLB last-level walk cache refill. Thi= s event does not count if the MMU is disabled" + }, + { + "PublicDescription": "Level 2 TLB level-2 walk cache access. This = event counts accesses to the level-2 walk cache where the last-level walk c= ache has missed. The event only counts when the translation regime of the p= agewalk uses level 2 descriptors. This event does not count if the MMU is d= isabled", + "EventCode": "0xCC", + "EventName": "TLB_L2TLB_L2WALK_ACCESS", + "BriefDescription": "Level 2 TLB level-2 walk cache access. This e= vent counts accesses to the level-2 walk cache where the last-level walk ca= che has missed. The event only counts when the translation regime of the pa= gewalk uses level 2 descriptors. This event does not count if the MMU is di= sabled" + }, + { + "PublicDescription": "Level 2 TLB level-2 walk cache refill. This = event does not count if the MMU is disabled", + "EventCode": "0xCD", + "EventName": "TLB_L2TLB_L2WALK_REFILL", + "BriefDescription": "Level 2 TLB level-2 walk cache refill. This e= vent does not count if the MMU is disabled" + }, + { + "PublicDescription": "Level 2 TLB IPA cache access. This event cou= nts on each access to the IPA cache. +//0 If a single pagewalk needs to mak= e multiple accesses to the IPA cache, each access is counted. +//0 If stage= 2 translation is disabled, this event does not count", + "EventCode": "0xCE", + "EventName": "TLB_L2TLB_S2_ACCESS", + "BriefDescription": "Level 2 TLB IPA cache access. This event coun= ts on each access to the IPA cache. +//0 If a single pagewalk needs to make= multiple accesses to the IPA cache, each access is counted. +//0 If stage = 2 translation is disabled, this event does not count" + }, + { + "PublicDescription": "Level 2 TLB IPA cache refill. This event cou= nts on each refill of the IPA cache. +//0 If a single pagewalk needs to mak= e multiple accesses to the IPA cache, each access which causes a refill is = counted. +//0 If stage 2 translation is disabled, this event does not count= ", + "EventCode": "0xCF", + "EventName": "TLB_L2TLB_S2_REFILL", + "BriefDescription": "Level 2 TLB IPA cache refill. This event coun= ts on each refill of the IPA cache. +//0 If a single pagewalk needs to make= multiple accesses to the IPA cache, each access which causes a refill is c= ounted. +//0 If stage 2 translation is disabled, this event does not count" + }, + { + "PublicDescription": "Unattributable Level 1 data cache write-back= . This event occurs when a requestor outside the PE makes a coherency reque= st that results in writeback", + "EventCode": "0xF0", + "EventName": "L2_L1D_CACHE_WB_UNATT", + "BriefDescription": "Unattributable Level 1 data cache write-back.= This event occurs when a requestor outside the PE makes a coherency reques= t that results in writeback" + }, + { + "PublicDescription": "Unattributable Level 2 data cache access. Th= is event occurs when a requestor outside the PE makes a coherency request t= hat results in level 2 data cache access", + "EventCode": "0xF1", + "EventName": "L2_L2D_CACHE_UNATT", + "BriefDescription": "Unattributable Level 2 data cache access. Thi= s event occurs when a requestor outside the PE makes a coherency request th= at results in level 2 data cache access" + }, + { + "PublicDescription": "Unattributable Level 2 data cache access, re= ad. This event occurs when a requestor outside the PE makes a coherency req= uest that results in level 2 data cache read access", + "EventCode": "0xF2", + "EventName": "L2_L2D_CACHE_RD_UNATT", + "BriefDescription": "Unattributable Level 2 data cache access, rea= d. This event occurs when a requestor outside the PE makes a coherency requ= est that results in level 2 data cache read access" + }, + { + "PublicDescription": "Unattributable Level 3 data cache access. Th= is event occurs when a requestor outside the PE makes a coherency request t= hat results in level 3 data cache read access", + "EventCode": "0xF3", + "EventName": "L2_L3D_CACHE_UNATT", + "BriefDescription": "Unattributable Level 3 data cache access. Thi= s event occurs when a requestor outside the PE makes a coherency request th= at results in level 3 data cache read access" + }, + { + "PublicDescription": "Unattributable Level 3 data cache access, re= ad. This event occurs when a requestor outside the PE makes a coherency req= uest that results in level 3 data cache read access", + "EventCode": "0xF4", + "EventName": "L2_L3D_CACHE_RD_UNATT", + "BriefDescription": "Unattributable Level 3 data cache access, rea= d. This event occurs when a requestor outside the PE makes a coherency requ= est that results in level 3 data cache read access" + }, + { + "PublicDescription": "Unattributable Level 3 data or unified cache= allocation without refill. This event occurs when a requestor outside the = PE makes a coherency request that results in level 3 cache allocate without= refill", + "EventCode": "0xF5", + "EventName": "L2_L3D_CACHE_ALLOC_UNATT", + "BriefDescription": "Unattributable Level 3 data or unified cache = allocation without refill. This event occurs when a requestor outside the P= E makes a coherency request that results in level 3 cache allocate without = refill" + }, + { + "PublicDescription": "Unattributable Level 3 data or unified cache= refill. This event occurs when a requestor outside the PE makes a coherenc= y request that results in level 3 cache refill", + "EventCode": "0xF6", + "EventName": "L2_L3D_CACHE_REFILL_UNATT", + "BriefDescription": "Unattributable Level 3 data or unified cache = refill. This event occurs when a requestor outside the PE makes a coherency= request that results in level 3 cache refill" + }, + { + "PublicDescription": "Level 2 cache stash dropped. This event coun= ts on each stash request received from the interconnect or ACP, that is tar= geting L2 and gets dropped due to lack of buffer space to hold the request.= L2 and L3 cache events (L2D_CACHE*, L3D_CACHE*) The behavior of these even= ts depends on the configuration of the core. If the private L2 cache is pre= sent, the L2D_CACHE* events count the activity in the private L2 cache, and= the L3D_CACHE* events count the activity in the DSU L3 cache (if present).= If the private L2 cache is not present but the DSU L3 cache is present, th= e L2D_CACHE* events count activity in the DSU L3 cache and the L3D_CACHE* e= vents do not count. The L2D_CACHE_WB, L2D_CACHE_WR and L2D_CACHE_REFILL_WR = events do not count in this configuration. If neither the private L2 cache = nor the DSU L3 cache are present, neither the L2D_CACHE* or L3D_CACHE* even= ts will count", + "EventCode": "0xF7", + "EventName": "L2D_CACHE_STASH_DROPPED", + "BriefDescription": "Level 2 cache stash dropped. This event count= s on each stash request received from the interconnect or ACP, that is targ= eting L2 and gets dropped due to lack of buffer space to hold the request. = L2 and L3 cache events (L2D_CACHE*, L3D_CACHE*) The behavior of these event= s depends on the configuration of the core. If the private L2 cache is pres= ent, the L2D_CACHE* events count the activity in the private L2 cache, and = the L3D_CACHE* events count the activity in the DSU L3 cache (if present). = If the private L2 cache is not present but the DSU L3 cache is present, the= L2D_CACHE* events count activity in the DSU L3 cache and the L3D_CACHE* ev= ents do not count. The L2D_CACHE_WB, L2D_CACHE_WR and L2D_CACHE_REFILL_WR e= vents do not count in this configuration. If neither the private L2 cache n= or the DSU L3 cache are present, neither the L2D_CACHE* or L3D_CACHE* event= s will count" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/dpu.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a65/dpu.json new file mode 100644 index 000000000000..b8e402a91bdd --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/dpu.json @@ -0,0 +1,32 @@ +[ + { + "PublicDescription": "Instruction retired, indirect branch, mispre= dicted", + "EventCode": "0xE9", + "EventName": "DPU_BR_IND_MIS", + "BriefDescription": "Instruction retired, indirect branch, mispred= icted" + }, + { + "PublicDescription": "Instruction retired, conditional branch, mis= predicted", + "EventCode": "0xEA", + "EventName": "DPU_BR_COND_MIS", + "BriefDescription": "Instruction retired, conditional branch, misp= redicted" + }, + { + "PublicDescription": "Memory error (any type) from IFU", + "EventCode": "0xEB", + "EventName": "DPU_MEM_ERR_IFU", + "BriefDescription": "Memory error (any type) from IFU" + }, + { + "PublicDescription": "Memory error (any type) from DCU", + "EventCode": "0xEC", + "EventName": "DPU_MEM_ERR_DCU", + "BriefDescription": "Memory error (any type) from DCU" + }, + { + "PublicDescription": "Memory error (any type) from TLB", + "EventCode": "0xED", + "EventName": "DPU_MEM_ERR_TLB", + "BriefDescription": "Memory error (any type) from TLB" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/exception.json= b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/exception.json new file mode 100644 index 000000000000..27c3fe9c831a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/exception.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/ifu.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a65/ifu.json new file mode 100644 index 000000000000..13178c5dca14 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/ifu.json @@ -0,0 +1,122 @@ +[ + { + "PublicDescription": "I-Cache miss on an access from the prefetch = block", + "EventCode": "0xD0", + "EventName": "IFU_IC_MISS_WAIT", + "BriefDescription": "I-Cache miss on an access from the prefetch b= lock" + }, + { + "PublicDescription": "Counts the cycles spent on a request for Lev= el 2 TLB lookup after a Level 1l ITLB miss", + "EventCode": "0xD1", + "EventName": "IFU_IUTLB_MISS_WAIT", + "BriefDescription": "Counts the cycles spent on a request for Leve= l 2 TLB lookup after a Level 1l ITLB miss" + }, + { + "PublicDescription": "Micro-predictor conditional/direction mispre= dict, with respect to. if3/if4 predictor", + "EventCode": "0xD2", + "EventName": "IFU_MICRO_COND_MISPRED", + "BriefDescription": "Micro-predictor conditional/direction mispred= ict, with respect to. if3/if4 predictor" + }, + { + "PublicDescription": "Micro-predictor address mispredict, with res= pect to if3/if4 predictor", + "EventCode": "0xD3", + "EventName": "IFU_MICRO_CADDR_MISPRED", + "BriefDescription": "Micro-predictor address mispredict, with resp= ect to if3/if4 predictor" + }, + { + "PublicDescription": "Micro-predictor hit with immediate redirect", + "EventCode": "0xD4", + "EventName": "IFU_MICRO_HIT", + "BriefDescription": "Micro-predictor hit with immediate redirect" + }, + { + "PublicDescription": "Micro-predictor negative cache hit", + "EventCode": "0xD6", + "EventName": "IFU_MICRO_NEG_HIT", + "BriefDescription": "Micro-predictor negative cache hit" + }, + { + "PublicDescription": "Micro-predictor correction", + "EventCode": "0xD7", + "EventName": "IFU_MICRO_CORRECTION", + "BriefDescription": "Micro-predictor correction" + }, + { + "PublicDescription": "A 2nd instruction could have been pushed but= was not because it was nonsequential", + "EventCode": "0xD8", + "EventName": "IFU_MICRO_NO_INSTR1", + "BriefDescription": "A 2nd instruction could have been pushed but = was not because it was nonsequential" + }, + { + "PublicDescription": "Micro-predictor miss", + "EventCode": "0xD9", + "EventName": "IFU_MICRO_NO_PRED", + "BriefDescription": "Micro-predictor miss" + }, + { + "PublicDescription": "Thread flushed due to TLB miss", + "EventCode": "0xDA", + "EventName": "IFU_FLUSHED_TLB_MISS", + "BriefDescription": "Thread flushed due to TLB miss" + }, + { + "PublicDescription": "Thread flushed due to reasons other than TLB= miss", + "EventCode": "0xDB", + "EventName": "IFU_FLUSHED_EXCL_TLB_MISS", + "BriefDescription": "Thread flushed due to reasons other than TLB = miss" + }, + { + "PublicDescription": "This thread and the other thread both ready = for scheduling in if0", + "EventCode": "0xDC", + "EventName": "IFU_ALL_THRDS_RDY", + "BriefDescription": "This thread and the other thread both ready f= or scheduling in if0" + }, + { + "PublicDescription": "This thread was arbitrated when the other th= read was also ready for scheduling", + "EventCode": "0xDD", + "EventName": "IFU_WIN_ARB_OTHER_RDY", + "BriefDescription": "This thread was arbitrated when the other thr= ead was also ready for scheduling" + }, + { + "PublicDescription": "This thread was arbitrated when the other th= read was also active, but not necessarily ready. For example, waiting for I= -Cache or TLB", + "EventCode": "0xDE", + "EventName": "IFU_WIN_ARB_OTHER_ACT", + "BriefDescription": "This thread was arbitrated when the other thr= ead was also active, but not necessarily ready. For example, waiting for I-= Cache or TLB" + }, + { + "PublicDescription": "This thread was not arbitrated because it wa= s not ready for scheduling. For example, due to a cache miss or TLB miss", + "EventCode": "0xDF", + "EventName": "IFU_NOT_RDY_FOR_ARB", + "BriefDescription": "This thread was not arbitrated because it was= not ready for scheduling. For example, due to a cache miss or TLB miss" + }, + { + "PublicDescription": "The thread moved from an active state to an = inactive state (long-term sleep state, causing deallocation of some resourc= es)", + "EventCode": "0xE0", + "EventName": "IFU_GOTO_IDLE", + "BriefDescription": "The thread moved from an active state to an i= nactive state (long-term sleep state, causing deallocation of some resource= s)" + }, + { + "PublicDescription": "I-Cache lookup under miss from other thread", + "EventCode": "0xE1", + "EventName": "IFU_IC_LOOKUP_UNDER_MISS", + "BriefDescription": "I-Cache lookup under miss from other thread" + }, + { + "PublicDescription": "I-Cache miss under miss from other thread", + "EventCode": "0xE2", + "EventName": "IFU_IC_MISS_UNDER_MISS", + "BriefDescription": "I-Cache miss under miss from other thread" + }, + { + "PublicDescription": "This thread pushed an instruction into the I= Q", + "EventCode": "0xE3", + "EventName": "IFU_INSTR_PUSHED", + "BriefDescription": "This thread pushed an instruction into the IQ" + }, + { + "PublicDescription": "I-Cache Speculative line fill", + "EventCode": "0xE4", + "EventName": "IFU_IC_LF_SP", + "BriefDescription": "I-Cache Speculative line fill" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/instruction.js= on b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/instruction.json new file mode 100644 index 000000000000..2e0d60779dce --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/instruction.json @@ -0,0 +1,71 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "LD_RETIRED" + }, + { + "ArchStdEvent": "ST_RETIRED" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_RETIRED" + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "PublicDescription": "Instruction retired, conditional branch", + "EventCode": "0xE8", + "EventName": "DPU_BR_COND_RETIRED", + "BriefDescription": "Instruction retired, conditional branch" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/memory.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a65/memory.json new file mode 100644 index 000000000000..18d527f7fad4 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/memory.json @@ -0,0 +1,35 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "REMOTE_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC" + }, + { + "PublicDescription": "External memory request", + "EventCode": "0xC1", + "EventName": "BIU_EXT_MEM_REQ", + "BriefDescription": "External memory request" + }, + { + "PublicDescription": "External memory request to non-cacheable mem= ory", + "EventCode": "0xC2", + "EventName": "BIU_EXT_MEM_REQ_NC", + "BriefDescription": "External memory request to non-cacheable memo= ry" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/pipeline.json = b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/pipeline.json new file mode 100644 index 000000000000..eeac798d403a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a65/pipeline.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index 6988797359c2..b90bd3850531 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -17,6 +17,7 @@ 0x00000000420f1000,v1,arm/cortex-a53,core 0x00000000410fd040,v1,arm/cortex-a35,core 0x00000000410fd050,v1,arm/cortex-a55,core +0x00000000410fd060,v1,arm/cortex-a65,core 0x00000000410fd070,v1,arm/cortex-a57-a72,core 0x00000000410fd080,v1,arm/cortex-a57-a72,core 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9A2FC433F5 for ; Fri, 20 May 2022 18:16:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233174AbiETSQe (ORCPT ); Fri, 20 May 2022 14:16:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352565AbiETSPs (ORCPT ); Fri, 20 May 2022 14:15:48 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A03531912E4; Fri, 20 May 2022 11:15:36 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 58FBF1515; Fri, 20 May 2022 11:15:36 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D46C33F718; Fri, 20 May 2022 11:15:33 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 06/13] perf vendors events arm64: Arm Cortex-A73 Date: Fri, 20 May 2022 19:14:48 +0100 Message-Id: <20220520181455.340344-7-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-A73 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a73.json which is based on PMU event descriptions from the Arm Cortex-A73 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-a73/branch.json | 11 ++ .../arch/arm64/arm/cortex-a73/bus.json | 23 ++++ .../arch/arm64/arm/cortex-a73/cache.json | 107 ++++++++++++++++++ .../arch/arm64/arm/cortex-a73/etm.json | 14 +++ .../arch/arm64/arm/cortex-a73/exception.json | 14 +++ .../arm64/arm/cortex-a73/instruction.json | 65 +++++++++++ .../arch/arm64/arm/cortex-a73/memory.json | 14 +++ .../arch/arm64/arm/cortex-a73/mmu.json | 44 +++++++ .../arch/arm64/arm/cortex-a73/pipeline.json | 38 +++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 10 files changed, 331 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/excepti= on.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/instruc= tion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a73/pipelin= e.json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json new file mode 100644 index 000000000000..ece201718284 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/branch.json @@ -0,0 +1,11 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json new file mode 100644 index 000000000000..103bb2535775 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/bus.json @@ -0,0 +1,23 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_SHARED" + }, + { + "ArchStdEvent": "BUS_ACCESS_NOT_SHARED" + }, + { + "ArchStdEvent": "BUS_ACCESS_NORMAL" + }, + { + "ArchStdEvent": "BUS_ACCESS_PERIPH" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json new file mode 100644 index 000000000000..b9b3d3fb07b2 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/cache.json @@ -0,0 +1,107 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL" + }, + { + "PublicDescription": "Number of ways read in the instruction cache= - Tag RAM", + "EventCode": "0xC2", + "EventName": "I_TAG_RAM_RD", + "BriefDescription": "Number of ways read in the instruction cache = - Tag RAM" + }, + { + "PublicDescription": "Number of ways read in the instruction cache= - Data RAM", + "EventCode": "0xC3", + "EventName": "I_DATA_RAM_RD", + "BriefDescription": "Number of ways read in the instruction cache = - Data RAM" + }, + { + "PublicDescription": "Number of ways read in the instruction BTAC = RAM", + "EventCode": "0xC4", + "EventName": "I_BTAC_RAM_RD", + "BriefDescription": "Number of ways read in the instruction BTAC R= AM" + }, + { + "PublicDescription": "Level 1 PLD TLB refill", + "EventCode": "0xE7", + "EventName": "PLD_UTLB_REFILL", + "BriefDescription": "Level 1 PLD TLB refill" + }, + { + "PublicDescription": "Level 1 CP15 TLB refill", + "EventCode": "0xE8", + "EventName": "CP15_UTLB_REFILL", + "BriefDescription": "Level 1 CP15 TLB refill" + }, + { + "PublicDescription": "Level 1 TLB flush", + "EventCode": "0xE9", + "EventName": "UTLB_FLUSH", + "BriefDescription": "Level 1 TLB flush" + }, + { + "PublicDescription": "Level 2 TLB access", + "EventCode": "0xEA", + "EventName": "TLB_ACCESS", + "BriefDescription": "Level 2 TLB access" + }, + { + "PublicDescription": "Level 2 TLB miss", + "EventCode": "0xEB", + "EventName": "TLB_MISS", + "BriefDescription": "Level 2 TLB miss" + }, + { + "PublicDescription": "Data cache hit in itself due to VIPT aliasin= g", + "EventCode": "0xEC", + "EventName": "DCACHE_SELF_HIT_VIPT", + "BriefDescription": "Data cache hit in itself due to VIPT aliasing" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json new file mode 100644 index 000000000000..fce852e82369 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/etm.json @@ -0,0 +1,14 @@ +[ + { + "PublicDescription": "ETM trace unit output 0", + "EventCode": "0xDE", + "EventName": "ETM_EXT_OUT0", + "BriefDescription": "ETM trace unit output 0" + }, + { + "PublicDescription": "ETM trace unit output 1", + "EventCode": "0xDF", + "EventName": "ETM_EXT_OUT1", + "BriefDescription": "ETM trace unit output 1" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/exception.json= b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/exception.json new file mode 100644 index 000000000000..b77f1228873d --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/exception.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "EXC_HVC" + }, + { + "PublicDescription": "Number of Traps to hypervisor", + "EventCode": "0xDC", + "EventName": "EXC_TRAP_HYP", + "BriefDescription": "Number of Traps to hypervisor" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/instruction.js= on b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/instruction.json new file mode 100644 index 000000000000..91a7863ddc9a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/instruction.json @@ -0,0 +1,65 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "ArchStdEvent": "LDREX_SPEC" + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "ArchStdEvent": "DSB_SPEC" + }, + { + "ArchStdEvent": "DMB_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json new file mode 100644 index 000000000000..34e9cab7f0b9 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/memory.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json new file mode 100644 index 000000000000..b85c9cc81f23 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/mmu.json @@ -0,0 +1,44 @@ +[ + { + "PublicDescription": "Duration of a translation table walk handled= by the MMU", + "EventCode": "0xE0", + "EventName": "MMU_PTW", + "BriefDescription": "Duration of a translation table walk handled = by the MMU" + }, + { + "PublicDescription": "Duration of a Stage 1 translation table walk= handled by the MMU", + "EventCode": "0xE1", + "EventName": "MMU_PTW_ST1", + "BriefDescription": "Duration of a Stage 1 translation table walk = handled by the MMU" + }, + { + "PublicDescription": "Duration of a Stage 2 translation table walk= handled by the MMU", + "EventCode": "0xE2", + "EventName": "MMU_PTW_ST2", + "BriefDescription": "Duration of a Stage 2 translation table walk = handled by the MMU" + }, + { + "PublicDescription": "Duration of a translation table walk request= ed by the LSU", + "EventCode": "0xE3", + "EventName": "MMU_PTW_LSU", + "BriefDescription": "Duration of a translation table walk requeste= d by the LSU" + }, + { + "PublicDescription": "Duration of a translation table walk request= ed by the Instruction Side", + "EventCode": "0xE4", + "EventName": "MMU_PTW_ISIDE", + "BriefDescription": "Duration of a translation table walk requeste= d by the Instruction Side" + }, + { + "PublicDescription": "Duration of a translation table walk request= ed by a Preload instruction or Prefetch request", + "EventCode": "0xE5", + "EventName": "MMU_PTW_PLD", + "BriefDescription": "Duration of a translation table walk requeste= d by a Preload instruction or Prefetch request" + }, + { + "PublicDescription": "Duration of a translation table walk request= ed by a CP15 operation (maintenance by MVA and VA to PA operations)", + "EventCode": "0xE6", + "EventName": "MMU_PTW_CP15", + "BriefDescription": "Duration of a translation table walk requeste= d by a CP15 operation (maintenance by MVA and VA to PA operations)" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/pipeline.json = b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/pipeline.json new file mode 100644 index 000000000000..1730969e49f7 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/pipeline.json @@ -0,0 +1,38 @@ +[ + { + "PublicDescription": "A linefill caused an instruction side stall", + "EventCode": "0xC0", + "EventName": "LF_STALL", + "BriefDescription": "A linefill caused an instruction side stall" + }, + { + "PublicDescription": "A translation table walk caused an instructi= on side stall", + "EventCode": "0xC1", + "EventName": "PTW_STALL", + "BriefDescription": "A translation table walk caused an instructio= n side stall" + }, + { + "PublicDescription": "Duration for which all slots in the Load-Sto= re Unit are busy", + "EventCode": "0xD3", + "EventName": "D_LSU_SLOT_FULL", + "BriefDescription": "Duration for which all slots in the Load-Stor= e Unit are busy" + }, + { + "PublicDescription": "Duration for which all slots in the load-sto= re issue queue are busy", + "EventCode": "0xD8", + "EventName": "LS_IQ_FULL", + "BriefDescription": "Duration for which all slots in the load-stor= e issue queue are busy" + }, + { + "PublicDescription": "Duration for which all slots in the data pro= cessing issue queue are busy", + "EventCode": "0xD9", + "EventName": "DP_IQ_FULL", + "BriefDescription": "Duration for which all slots in the data proc= essing issue queue are busy" + }, + { + "PublicDescription": "Duration for which all slots in the Data Eng= ine issue queue are busy", + "EventCode": "0xDA", + "EventName": "DE_IQ_FULL", + "BriefDescription": "Duration for which all slots in the Data Engi= ne issue queue are busy" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index b90bd3850531..36b8f3506b74 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -20,6 +20,7 @@ 0x00000000410fd060,v1,arm/cortex-a65,core 0x00000000410fd070,v1,arm/cortex-a57-a72,core 0x00000000410fd080,v1,arm/cortex-a57-a72,core +0x00000000410fd090,v1,arm/cortex-a73,core 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core 0x00000000410fd400,v1,arm/neoverse-v1,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17F15C433F5 for ; Fri, 20 May 2022 18:16:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352579AbiETSQx (ORCPT ); Fri, 20 May 2022 14:16:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352564AbiETSPs (ORCPT ); Fri, 20 May 2022 14:15:48 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 53B911912E7; Fri, 20 May 2022 11:15:39 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 171141516; Fri, 20 May 2022 11:15:39 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 923F03F718; Fri, 20 May 2022 11:15:36 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 07/13] perf vendors events arm64: Arm Cortex-A75 Date: Fri, 20 May 2022 19:14:49 +0100 Message-Id: <20220520181455.340344-8-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-A75 Add corresponding common events Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a75.json which is based on PMU event descriptions from the Arm Cortex-A75 Technical Reference Manual. Common event data based on: https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json which is based on PMU event descriptions found in the Arm Architecture Reference Manual: https://developer.arm.com/documentation/ddi0487/ Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-a75/branch.json | 11 ++ .../arch/arm64/arm/cortex-a75/bus.json | 17 ++ .../arch/arm64/arm/cortex-a75/cache.json | 164 ++++++++++++++++++ .../arch/arm64/arm/cortex-a75/etm.json | 14 ++ .../arch/arm64/arm/cortex-a75/exception.json | 17 ++ .../arm64/arm/cortex-a75/instruction.json | 74 ++++++++ .../arch/arm64/arm/cortex-a75/memory.json | 17 ++ .../arch/arm64/arm/cortex-a75/mmu.json | 44 +++++ .../arch/arm64/arm/cortex-a75/pipeline.json | 44 +++++ .../arch/arm64/common-and-microarch.json | 6 + tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 11 files changed, 409 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/excepti= on.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/instruc= tion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipelin= e.json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json new file mode 100644 index 000000000000..ece201718284 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/branch.json @@ -0,0 +1,11 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json new file mode 100644 index 000000000000..7efa09800a51 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/cache.json @@ -0,0 +1,164 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L1D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L1D_TLB" + }, + { + "ArchStdEvent": "L1I_TLB" + }, + { + "ArchStdEvent": "L3D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L3D_CACHE" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "L2I_TLB" + }, + { + "ArchStdEvent": "DTLB_WALK" + }, + { + "ArchStdEvent": "ITLB_WALK" + }, + { + "ArchStdEvent": "LL_CACHE_RD" + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L3D_CACHE_RD" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL_RD" + }, + { + "PublicDescription": "Number of ways read in the instruction cache= - Tag RAM", + "EventCode": "0xC2", + "EventName": "I_TAG_RAM_RD", + "BriefDescription": "Number of ways read in the instruction cache = - Tag RAM" + }, + { + "PublicDescription": "Number of ways read in the instruction cache= - Data RAM", + "EventCode": "0xC3", + "EventName": "I_DATA_RAM_RD", + "BriefDescription": "Number of ways read in the instruction cache = - Data RAM" + }, + { + "PublicDescription": "Number of ways read in the instruction BTAC = RAM", + "EventCode": "0xC4", + "EventName": "I_BTAC_RAM_RD", + "BriefDescription": "Number of ways read in the instruction BTAC R= AM" + }, + { + "PublicDescription": "Level 1 PLD TLB refill", + "EventCode": "0xE7", + "EventName": "L1PLD_TLB_REFILL", + "BriefDescription": "Level 1 PLD TLB refill" + }, + { + "PublicDescription": "Level 2 preload and MMU prefetcher TLB acces= s. This event only counts software and hardware prefetches at Level 2", + "EventCode": "0xE8", + "EventName": "L2PLD_TLB", + "BriefDescription": "Level 2 preload and MMU prefetcher TLB access= . This event only counts software and hardware prefetches at Level 2" + }, + { + "PublicDescription": "Level 1 TLB flush", + "EventCode": "0xE9", + "EventName": "UTLB_FLUSH", + "BriefDescription": "Level 1 TLB flush" + }, + { + "PublicDescription": "Level 2 TLB access", + "EventCode": "0xEA", + "EventName": "TLB_ACCESS", + "BriefDescription": "Level 2 TLB access" + }, + { + "PublicDescription": "Level 1 preload TLB access. This event only = counts software and hardware prefetches at Level 1. This event counts all a= ccesses to the preload data micro TLB, that is L1 prefetcher and preload in= structions. This event does not take into account whether the MMU is enable= d or not", + "EventCode": "0xEB", + "EventName": "L1PLD_TLB", + "BriefDescription": "Level 1 preload TLB access. This event only c= ounts software and hardware prefetches at Level 1. This event counts all ac= cesses to the preload data micro TLB, that is L1 prefetcher and preload ins= tructions. This event does not take into account whether the MMU is enabled= or not" + }, + { + "PublicDescription": "Prefetch access to unified TLB that caused a= page table walk. This event counts software and hardware prefetches", + "EventCode": "0xEC", + "EventName": "PLDTLB_WALK", + "BriefDescription": "Prefetch access to unified TLB that caused a = page table walk. This event counts software and hardware prefetches" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json new file mode 100644 index 000000000000..fce852e82369 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/etm.json @@ -0,0 +1,14 @@ +[ + { + "PublicDescription": "ETM trace unit output 0", + "EventCode": "0xDE", + "EventName": "ETM_EXT_OUT0", + "BriefDescription": "ETM trace unit output 0" + }, + { + "PublicDescription": "ETM trace unit output 1", + "EventCode": "0xDF", + "EventName": "ETM_EXT_OUT1", + "BriefDescription": "ETM trace unit output 1" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/exception.json= b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/exception.json new file mode 100644 index 000000000000..5b04d01de703 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/exception.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "EXC_UNDEF" + }, + { + "ArchStdEvent": "EXC_HVC" + }, + { + "PublicDescription": "Number of traps to hypervisor. This event co= unts the number of exception traps taken to EL2, excluding HVC instructions= . This event is set every time that an exception is executed because of a d= ecoded trap to the hypervisor. CCFAIL exceptions and traps caused by HVC in= structions are excluded. This event is not counted when it is accessible fr= om Non-secure EL0 or EL1", + "EventCode": "0xDC", + "EventName": "EXC_TRAP_HYP", + "BriefDescription": "Number of traps to hypervisor. This event cou= nts the number of exception traps taken to EL2, excluding HVC instructions.= This event is set every time that an exception is executed because of a de= coded trap to the hypervisor. CCFAIL exceptions and traps caused by HVC ins= tructions are excluded. This event is not counted when it is accessible fro= m Non-secure EL0 or EL1" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/instruction.js= on b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/instruction.json new file mode 100644 index 000000000000..930ce8a259f3 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/instruction.json @@ -0,0 +1,74 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_RETIRED" + }, + { + "ArchStdEvent": "LDREX_SPEC" + }, + { + "ArchStdEvent": "STREX_PASS_SPEC" + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC" + }, + { + "ArchStdEvent": "STREX_SPEC" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "ArchStdEvent": "DSB_SPEC" + }, + { + "ArchStdEvent": "DMB_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.json new file mode 100644 index 000000000000..929fc545470f --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/memory.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "REMOTE_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json new file mode 100644 index 000000000000..0e63e68bc8cb --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/mmu.json @@ -0,0 +1,44 @@ +[ + { + "PublicDescription": "Duration of a translation table walk handled= by the MMU", + "EventCode": "0xE0", + "EventName": "MMU_PTW", + "BriefDescription": "Duration of a translation table walk handled = by the MMU" + }, + { + "PublicDescription": "Duration of a Stage 1 translation table walk= handled by the MMU. This event is not counted when it is accessible from N= on-secure EL0 or EL1", + "EventCode": "0xE1", + "EventName": "MMU_PTW_ST1", + "BriefDescription": "Duration of a Stage 1 translation table walk = handled by the MMU. This event is not counted when it is accessible from No= n-secure EL0 or EL1" + }, + { + "PublicDescription": "Duration of a Stage 2 translation table walk= handled by the MMU. This event is not counted when it is accessible from N= on-secure EL0 or EL1", + "EventCode": "0xE2", + "EventName": "MMU_PTW_ST2", + "BriefDescription": "Duration of a Stage 2 translation table walk = handled by the MMU. This event is not counted when it is accessible from No= n-secure EL0 or EL1" + }, + { + "PublicDescription": "Duration of a translation table walk request= ed by the LSU", + "EventCode": "0xE3", + "EventName": "MMU_PTW_LSU", + "BriefDescription": "Duration of a translation table walk requeste= d by the LSU" + }, + { + "PublicDescription": "Duration of a translation table walk request= ed by the instruction side", + "EventCode": "0xE4", + "EventName": "MMU_PTW_ISIDE", + "BriefDescription": "Duration of a translation table walk requeste= d by the instruction side" + }, + { + "PublicDescription": "Duration of a translation table walk request= ed by a Preload instruction or Prefetch request", + "EventCode": "0xE5", + "EventName": "MMU_PTW_PLD", + "BriefDescription": "Duration of a translation table walk requeste= d by a Preload instruction or Prefetch request" + }, + { + "PublicDescription": "Duration of a translation table walk request= ed by an address translation operation", + "EventCode": "0xE6", + "EventName": "MMU_PTW_CP15", + "BriefDescription": "Duration of a translation table walk requeste= d by an address translation operation" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json = b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json new file mode 100644 index 000000000000..0f8f50823cf1 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/pipeline.json @@ -0,0 +1,44 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + }, + { + "PublicDescription": "A linefill caused an instruction side stall", + "EventCode": "0xC0", + "EventName": "LF_STALL", + "BriefDescription": "A linefill caused an instruction side stall" + }, + { + "PublicDescription": "A translation table walk caused an instructi= on side stall", + "EventCode": "0xC1", + "EventName": "PTW_STALL", + "BriefDescription": "A translation table walk caused an instructio= n side stall" + }, + { + "PublicDescription": "Duration for which all slots in the Load-Sto= re Unit (LSU) are busy", + "EventCode": "0xD3", + "EventName": "D_LSU_SLOT_FULL", + "BriefDescription": "Duration for which all slots in the Load-Stor= e Unit (LSU) are busy" + }, + { + "PublicDescription": "Duration for which all slots in the load-sto= re issue queue are busy. This event counts the cycles where all slots in th= e LS IQs are full with micro-operations waiting for issuing, and the dispat= ch stage is not empty", + "EventCode": "0xD8", + "EventName": "LS_IQ_FULL", + "BriefDescription": "Duration for which all slots in the load-stor= e issue queue are busy. This event counts the cycles where all slots in the= LS IQs are full with micro-operations waiting for issuing, and the dispatc= h stage is not empty" + }, + { + "PublicDescription": "Duration for which all slots in the data pro= cessing issue queue are busy. This event counts the cycles where all slots = in the DP0 and DP1 IQs are full with micro-operations waiting for issuing, = and the despatch stage is not empty", + "EventCode": "0xD9", + "EventName": "DP_IQ_FULL", + "BriefDescription": "Duration for which all slots in the data proc= essing issue queue are busy. This event counts the cycles where all slots i= n the DP0 and DP1 IQs are full with micro-operations waiting for issuing, a= nd the despatch stage is not empty" + }, + { + "PublicDescription": "Duration for which all slots in the data eng= ine issue queue are busy. This event is set every time that the data engine= rename has at least one valid instruction, excluding No Operations (NOPs),= that cannot move to the issue stage because accpt_instr is LOW", + "EventCode": "0xDA", + "EventName": "DE_IQ_FULL", + "BriefDescription": "Duration for which all slots in the data engi= ne issue queue are busy. This event is set every time that the data engine = rename has at least one valid instruction, excluding No Operations (NOPs), = that cannot move to the issue stage because accpt_instr is LOW" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json b/t= ools/perf/pmu-events/arch/arm64/common-and-microarch.json index 876b51dae92e..492083b99256 100644 --- a/tools/perf/pmu-events/arch/arm64/common-and-microarch.json +++ b/tools/perf/pmu-events/arch/arm64/common-and-microarch.json @@ -179,6 +179,12 @@ "EventName": "BUS_CYCLES", "BriefDescription": "Bus cycle" }, + { + "PublicDescription": "Level 1 data cache allocation without refill= ", + "EventCode": "0x1F", + "EventName": "L1D_CACHE_ALLOCATE", + "BriefDescription": "Level 1 data cache allocation without refill" + }, { "PublicDescription": "Attributable Level 2 data cache allocation w= ithout refill", "EventCode": "0x20", diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index 36b8f3506b74..ea3cd63ea4c9 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -21,6 +21,7 @@ 0x00000000410fd070,v1,arm/cortex-a57-a72,core 0x00000000410fd080,v1,arm/cortex-a57-a72,core 0x00000000410fd090,v1,arm/cortex-a73,core +0x00000000410fd0a0,v1,arm/cortex-a75,core 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core 0x00000000410fd400,v1,arm/neoverse-v1,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CF08C433F5 for ; Fri, 20 May 2022 18:16:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346985AbiETSQr (ORCPT ); Fri, 20 May 2022 14:16:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352566AbiETSPs (ORCPT ); Fri, 20 May 2022 14:15:48 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 15FCF193209; Fri, 20 May 2022 11:15:42 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C80F21477; Fri, 20 May 2022 11:15:41 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4FEC63F718; Fri, 20 May 2022 11:15:39 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 08/13] perf vendors events arm64: Arm Cortex-A77 Date: Fri, 20 May 2022 19:14:50 +0100 Message-Id: <20220520181455.340344-9-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-A77 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a77.json which is based on PMU event descriptions from the Arm Cortex-A77 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-a77/branch.json | 17 +++ .../arch/arm64/arm/cortex-a77/bus.json | 17 +++ .../arch/arm64/arm/cortex-a77/cache.json | 143 ++++++++++++++++++ .../arch/arm64/arm/cortex-a77/exception.json | 47 ++++++ .../arm64/arm/cortex-a77/instruction.json | 77 ++++++++++ .../arch/arm64/arm/cortex-a77/memory.json | 23 +++ .../arch/arm64/arm/cortex-a77/pipeline.json | 8 + tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 8 files changed, 333 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/excepti= on.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruc= tion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipelin= e.json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json new file mode 100644 index 000000000000..2f2d137f5f55 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/branch.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json new file mode 100644 index 000000000000..cbb365f5091f --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/cache.json @@ -0,0 +1,143 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L1D_TLB" + }, + { + "ArchStdEvent": "L1I_TLB" + }, + { + "ArchStdEvent": "L3D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L3D_CACHE" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "DTLB_WALK" + }, + { + "ArchStdEvent": "ITLB_WALK" + }, + { + "ArchStdEvent": "LL_CACHE_RD" + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_TLB_RD" + }, + { + "ArchStdEvent": "L1D_TLB_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_TLB_RD" + }, + { + "ArchStdEvent": "L2D_TLB_WR" + }, + { + "ArchStdEvent": "L3D_CACHE_RD" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json= b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json new file mode 100644 index 000000000000..344a2d552ad5 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/exception.json @@ -0,0 +1,47 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_UNDEF" + }, + { + "ArchStdEvent": "EXC_SVC" + }, + { + "ArchStdEvent": "EXC_PABORT" + }, + { + "ArchStdEvent": "EXC_DABORT" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + }, + { + "ArchStdEvent": "EXC_SMC" + }, + { + "ArchStdEvent": "EXC_HVC" + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER" + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ" + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.js= on b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json new file mode 100644 index 000000000000..1a74786271d4 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/instruction.json @@ -0,0 +1,77 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_RETIRED" + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED" + }, + { + "ArchStdEvent": "LDREX_SPEC" + }, + { + "ArchStdEvent": "STREX_PASS_SPEC" + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC" + }, + { + "ArchStdEvent": "STREX_SPEC" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "PC_WRITE_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "ArchStdEvent": "DSB_SPEC" + }, + { + "ArchStdEvent": "DMB_SPEC" + }, + { + "ArchStdEvent": "RC_LD_SPEC" + }, + { + "ArchStdEvent": "RC_ST_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json new file mode 100644 index 000000000000..5aff6e93c1ad --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/memory.json @@ -0,0 +1,23 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "REMOTE_ACCESS" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json = b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json new file mode 100644 index 000000000000..eeac798d403a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a77/pipeline.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index ea3cd63ea4c9..c4b0e910d066 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -24,6 +24,7 @@ 0x00000000410fd0a0,v1,arm/cortex-a75,core 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core +0x00000000410fd0d0,v1,arm/cortex-a77,core 0x00000000410fd400,v1,arm/neoverse-v1,core 0x00000000410fd460,v1,arm/cortex-a510,core 0x00000000410fd490,v1,arm/neoverse-n2,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D58CC433F5 for ; Fri, 20 May 2022 18:17:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352618AbiETSRE (ORCPT ); Fri, 20 May 2022 14:17:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352569AbiETSPs (ORCPT ); Fri, 20 May 2022 14:15:48 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C256ABA9; Fri, 20 May 2022 11:15:44 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 85469152B; Fri, 20 May 2022 11:15:44 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0CDC53F718; Fri, 20 May 2022 11:15:41 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 09/13] perf vendors events arm64: Arm Cortex-A78 Date: Fri, 20 May 2022 19:14:51 +0100 Message-Id: <20220520181455.340344-10-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-A78 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a78.json which is based on PMU event descriptions from the Arm Cortex-A78 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-a78/branch.json | 17 ++ .../arch/arm64/arm/cortex-a78/bus.json | 20 +++ .../arch/arm64/arm/cortex-a78/cache.json | 155 ++++++++++++++++++ .../arch/arm64/arm/cortex-a78/exception.json | 47 ++++++ .../arm64/arm/cortex-a78/instruction.json | 80 +++++++++ .../arch/arm64/arm/cortex-a78/memory.json | 23 +++ .../arch/arm64/arm/cortex-a78/pipeline.json | 23 +++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 8 files changed, 366 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/excepti= on.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruc= tion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipelin= e.json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json new file mode 100644 index 000000000000..2f2d137f5f55 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/branch.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json b/too= ls/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json new file mode 100644 index 000000000000..579c1c993d17 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/bus.json @@ -0,0 +1,20 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + }, + { + "ArchStdEvent": "CNT_CYCLES" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json new file mode 100644 index 000000000000..0141f749bff3 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/cache.json @@ -0,0 +1,155 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L1D_TLB" + }, + { + "ArchStdEvent": "L1I_TLB" + }, + { + "ArchStdEvent": "L3D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L3D_CACHE" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "DTLB_WALK" + }, + { + "ArchStdEvent": "ITLB_WALK" + }, + { + "ArchStdEvent": "LL_CACHE_RD" + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_LMISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_TLB_RD" + }, + { + "ArchStdEvent": "L1D_TLB_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_TLB_RD" + }, + { + "ArchStdEvent": "L2D_TLB_WR" + }, + { + "ArchStdEvent": "L3D_CACHE_RD" + }, + { + "ArchStdEvent": "L1I_CACHE_LMISS" + }, + { + "ArchStdEvent": "L2D_CACHE_LMISS_RD" + }, + { + "ArchStdEvent": "L3D_CACHE_LMISS_RD" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json= b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json new file mode 100644 index 000000000000..344a2d552ad5 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/exception.json @@ -0,0 +1,47 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_UNDEF" + }, + { + "ArchStdEvent": "EXC_SVC" + }, + { + "ArchStdEvent": "EXC_PABORT" + }, + { + "ArchStdEvent": "EXC_DABORT" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + }, + { + "ArchStdEvent": "EXC_SMC" + }, + { + "ArchStdEvent": "EXC_HVC" + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER" + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ" + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.js= on b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json new file mode 100644 index 000000000000..a9edd52843a1 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/instruction.json @@ -0,0 +1,80 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_RETIRED" + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED" + }, + { + "ArchStdEvent": "OP_RETIRED" + }, + { + "ArchStdEvent": "OP_SPEC" + }, + { + "ArchStdEvent": "LDREX_SPEC" + }, + { + "ArchStdEvent": "STREX_PASS_SPEC" + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC" + }, + { + "ArchStdEvent": "STREX_SPEC" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "PC_WRITE_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "ArchStdEvent": "DSB_SPEC" + }, + { + "ArchStdEvent": "DMB_SPEC" + }, + { + "ArchStdEvent": "RC_LD_SPEC" + }, + { + "ArchStdEvent": "RC_ST_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json new file mode 100644 index 000000000000..5aff6e93c1ad --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/memory.json @@ -0,0 +1,23 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "REMOTE_ACCESS" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json = b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json new file mode 100644 index 000000000000..f9fae15f7555 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a78/pipeline.json @@ -0,0 +1,23 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + }, + { + "ArchStdEvent": "STALL" + }, + { + "ArchStdEvent": "STALL_SLOT_BACKEND" + }, + { + "ArchStdEvent": "STALL_SLOT_FRONTEND" + }, + { + "ArchStdEvent": "STALL_SLOT" + }, + { + "ArchStdEvent": "STALL_BACKEND_MEM" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index c4b0e910d066..a3ca05e61012 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -26,6 +26,7 @@ 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core 0x00000000410fd0d0,v1,arm/cortex-a77,core 0x00000000410fd400,v1,arm/neoverse-v1,core +0x00000000410fd410,v1,arm/cortex-a78,core 0x00000000410fd460,v1,arm/cortex-a510,core 0x00000000410fd490,v1,arm/neoverse-n2,core 0x00000000420f5160,v1,cavium/thunderx2,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C30FC433EF for ; Fri, 20 May 2022 18:17:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348185AbiETSRH (ORCPT ); Fri, 20 May 2022 14:17:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352520AbiETSPu (ORCPT ); Fri, 20 May 2022 14:15:50 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A09302678; Fri, 20 May 2022 11:15:47 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 422FA1516; Fri, 20 May 2022 11:15:47 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BE24B3F718; Fri, 20 May 2022 11:15:44 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 10/13] perf vendors events arm64: Arm Cortex-A710 Date: Fri, 20 May 2022 19:14:52 +0100 Message-Id: <20220520181455.340344-11-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-A710 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a710.json which is based on PMU event descriptions from the Arm Cortex-A710 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-a710/branch.json | 17 ++ .../arch/arm64/arm/cortex-a710/bus.json | 20 +++ .../arch/arm64/arm/cortex-a710/cache.json | 155 ++++++++++++++++++ .../arch/arm64/arm/cortex-a710/exception.json | 47 ++++++ .../arm64/arm/cortex-a710/instruction.json | 134 +++++++++++++++ .../arch/arm64/arm/cortex-a710/memory.json | 41 +++++ .../arch/arm64/arm/cortex-a710/pipeline.json | 23 +++ .../arch/arm64/arm/cortex-a710/trace.json | 29 ++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 9 files changed, 467 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch= .json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.js= on create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/except= ion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instru= ction.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory= .json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeli= ne.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.= json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json b= /tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json new file mode 100644 index 000000000000..2f2d137f5f55 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/branch.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json b/to= ols/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json new file mode 100644 index 000000000000..579c1c993d17 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/bus.json @@ -0,0 +1,20 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + }, + { + "ArchStdEvent": "CNT_CYCLES" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json new file mode 100644 index 000000000000..0141f749bff3 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/cache.json @@ -0,0 +1,155 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L1D_TLB" + }, + { + "ArchStdEvent": "L1I_TLB" + }, + { + "ArchStdEvent": "L3D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L3D_CACHE" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "DTLB_WALK" + }, + { + "ArchStdEvent": "ITLB_WALK" + }, + { + "ArchStdEvent": "LL_CACHE_RD" + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_LMISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_TLB_RD" + }, + { + "ArchStdEvent": "L1D_TLB_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_TLB_RD" + }, + { + "ArchStdEvent": "L2D_TLB_WR" + }, + { + "ArchStdEvent": "L3D_CACHE_RD" + }, + { + "ArchStdEvent": "L1I_CACHE_LMISS" + }, + { + "ArchStdEvent": "L2D_CACHE_LMISS_RD" + }, + { + "ArchStdEvent": "L3D_CACHE_LMISS_RD" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.jso= n b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json new file mode 100644 index 000000000000..344a2d552ad5 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/exception.json @@ -0,0 +1,47 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_UNDEF" + }, + { + "ArchStdEvent": "EXC_SVC" + }, + { + "ArchStdEvent": "EXC_PABORT" + }, + { + "ArchStdEvent": "EXC_DABORT" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + }, + { + "ArchStdEvent": "EXC_SMC" + }, + { + "ArchStdEvent": "EXC_HVC" + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER" + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ" + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.j= son b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json new file mode 100644 index 000000000000..964f47c6b099 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/instruction.json @@ -0,0 +1,134 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_RETIRED" + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED" + }, + { + "ArchStdEvent": "OP_RETIRED" + }, + { + "ArchStdEvent": "OP_SPEC" + }, + { + "ArchStdEvent": "LDREX_SPEC" + }, + { + "ArchStdEvent": "STREX_PASS_SPEC" + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC" + }, + { + "ArchStdEvent": "STREX_SPEC" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "PC_WRITE_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "ArchStdEvent": "DSB_SPEC" + }, + { + "ArchStdEvent": "DMB_SPEC" + }, + { + "ArchStdEvent": "RC_LD_SPEC" + }, + { + "ArchStdEvent": "RC_ST_SPEC" + }, + { + "ArchStdEvent": "ASE_INST_SPEC" + }, + { + "ArchStdEvent": "SVE_INST_SPEC" + }, + { + "ArchStdEvent": "FP_HP_SPEC" + }, + { + "ArchStdEvent": "FP_SP_SPEC" + }, + { + "ArchStdEvent": "FP_DP_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_EMPTY_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_FULL_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_PARTIAL_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_NOT_FULL_SPEC" + }, + { + "ArchStdEvent": "SVE_LDFF_SPEC" + }, + { + "ArchStdEvent": "SVE_LDFF_FAULT_SPEC" + }, + { + "ArchStdEvent": "FP_SCALE_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_FIXED_OPS_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT8_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT16_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT32_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT64_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json b= /tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json new file mode 100644 index 000000000000..7b2b21ac150f --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/memory.json @@ -0,0 +1,41 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "REMOTE_ACCESS" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC" + }, + { + "ArchStdEvent": "LDST_ALIGN_LAT" + }, + { + "ArchStdEvent": "LD_ALIGN_LAT" + }, + { + "ArchStdEvent": "ST_ALIGN_LAT" + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED" + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json= b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json new file mode 100644 index 000000000000..f9fae15f7555 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/pipeline.json @@ -0,0 +1,23 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + }, + { + "ArchStdEvent": "STALL" + }, + { + "ArchStdEvent": "STALL_SLOT_BACKEND" + }, + { + "ArchStdEvent": "STALL_SLOT_FRONTEND" + }, + { + "ArchStdEvent": "STALL_SLOT" + }, + { + "ArchStdEvent": "STALL_BACKEND_MEM" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json b/= tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json new file mode 100644 index 000000000000..3116135c59e2 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a710/trace.json @@ -0,0 +1,29 @@ +[ + { + "ArchStdEvent": "TRB_WRAP" + }, + { + "ArchStdEvent": "TRCEXTOUT0" + }, + { + "ArchStdEvent": "TRCEXTOUT1" + }, + { + "ArchStdEvent": "TRCEXTOUT2" + }, + { + "ArchStdEvent": "TRCEXTOUT3" + }, + { + "ArchStdEvent": "CTI_TRIGOUT4" + }, + { + "ArchStdEvent": "CTI_TRIGOUT5" + }, + { + "ArchStdEvent": "CTI_TRIGOUT6" + }, + { + "ArchStdEvent": "CTI_TRIGOUT7" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index a3ca05e61012..fb2d5459c42d 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -28,6 +28,7 @@ 0x00000000410fd400,v1,arm/neoverse-v1,core 0x00000000410fd410,v1,arm/cortex-a78,core 0x00000000410fd460,v1,arm/cortex-a510,core +0x00000000410fd470,v1,arm/cortex-a710,core 0x00000000410fd490,v1,arm/neoverse-n2,core 0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000430f0af0,v1,cavium/thunderx2,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FC14C433EF for ; Fri, 20 May 2022 18:17:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348305AbiETSRN (ORCPT ); Fri, 20 May 2022 14:17:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352517AbiETSPw (ORCPT ); Fri, 20 May 2022 14:15:52 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 405BB636C; Fri, 20 May 2022 11:15:50 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F352A1477; Fri, 20 May 2022 11:15:49 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7B0D83F718; Fri, 20 May 2022 11:15:47 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 11/13] perf vendors events arm64: Arm Cortex-X1 Date: Fri, 20 May 2022 19:14:53 +0100 Message-Id: <20220520181455.340344-12-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-X1 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-x1.json which is based on PMU event descriptions from the Arm Cortex-X1 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-x1/branch.json | 17 ++ .../arch/arm64/arm/cortex-x1/bus.json | 20 +++ .../arch/arm64/arm/cortex-x1/cache.json | 155 ++++++++++++++++++ .../arch/arm64/arm/cortex-x1/exception.json | 47 ++++++ .../arch/arm64/arm/cortex-x1/instruction.json | 80 +++++++++ .../arch/arm64/arm/cortex-x1/memory.json | 23 +++ .../arch/arm64/arm/cortex-x1/pipeline.json | 23 +++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 8 files changed, 366 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/branch.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/cache.js= on create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/exceptio= n.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/instruct= ion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/memory.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x1/pipeline= .json diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/branch.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-x1/branch.json new file mode 100644 index 000000000000..2f2d137f5f55 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/branch.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/bus.json b/tool= s/perf/pmu-events/arch/arm64/arm/cortex-x1/bus.json new file mode 100644 index 000000000000..579c1c993d17 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/bus.json @@ -0,0 +1,20 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + }, + { + "ArchStdEvent": "CNT_CYCLES" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/cache.json b/to= ols/perf/pmu-events/arch/arm64/arm/cortex-x1/cache.json new file mode 100644 index 000000000000..0141f749bff3 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/cache.json @@ -0,0 +1,155 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L1D_TLB" + }, + { + "ArchStdEvent": "L1I_TLB" + }, + { + "ArchStdEvent": "L3D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L3D_CACHE" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "DTLB_WALK" + }, + { + "ArchStdEvent": "ITLB_WALK" + }, + { + "ArchStdEvent": "LL_CACHE_RD" + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_LMISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_TLB_RD" + }, + { + "ArchStdEvent": "L1D_TLB_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_TLB_RD" + }, + { + "ArchStdEvent": "L2D_TLB_WR" + }, + { + "ArchStdEvent": "L3D_CACHE_RD" + }, + { + "ArchStdEvent": "L1I_CACHE_LMISS" + }, + { + "ArchStdEvent": "L2D_CACHE_LMISS_RD" + }, + { + "ArchStdEvent": "L3D_CACHE_LMISS_RD" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/exception.json = b/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/exception.json new file mode 100644 index 000000000000..344a2d552ad5 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/exception.json @@ -0,0 +1,47 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_UNDEF" + }, + { + "ArchStdEvent": "EXC_SVC" + }, + { + "ArchStdEvent": "EXC_PABORT" + }, + { + "ArchStdEvent": "EXC_DABORT" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + }, + { + "ArchStdEvent": "EXC_SMC" + }, + { + "ArchStdEvent": "EXC_HVC" + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER" + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ" + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/instruction.jso= n b/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/instruction.json new file mode 100644 index 000000000000..a9edd52843a1 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/instruction.json @@ -0,0 +1,80 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_RETIRED" + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED" + }, + { + "ArchStdEvent": "OP_RETIRED" + }, + { + "ArchStdEvent": "OP_SPEC" + }, + { + "ArchStdEvent": "LDREX_SPEC" + }, + { + "ArchStdEvent": "STREX_PASS_SPEC" + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC" + }, + { + "ArchStdEvent": "STREX_SPEC" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "PC_WRITE_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "ArchStdEvent": "DSB_SPEC" + }, + { + "ArchStdEvent": "DMB_SPEC" + }, + { + "ArchStdEvent": "RC_LD_SPEC" + }, + { + "ArchStdEvent": "RC_ST_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/memory.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-x1/memory.json new file mode 100644 index 000000000000..5aff6e93c1ad --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/memory.json @@ -0,0 +1,23 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "REMOTE_ACCESS" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/pipeline.json b= /tools/perf/pmu-events/arch/arm64/arm/cortex-x1/pipeline.json new file mode 100644 index 000000000000..f9fae15f7555 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x1/pipeline.json @@ -0,0 +1,23 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + }, + { + "ArchStdEvent": "STALL" + }, + { + "ArchStdEvent": "STALL_SLOT_BACKEND" + }, + { + "ArchStdEvent": "STALL_SLOT_FRONTEND" + }, + { + "ArchStdEvent": "STALL_SLOT" + }, + { + "ArchStdEvent": "STALL_BACKEND_MEM" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index fb2d5459c42d..32c4cd0ba2aa 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -27,6 +27,7 @@ 0x00000000410fd0d0,v1,arm/cortex-a77,core 0x00000000410fd400,v1,arm/neoverse-v1,core 0x00000000410fd410,v1,arm/cortex-a78,core +0x00000000410fd440,v1,arm/cortex-x1,core 0x00000000410fd460,v1,arm/cortex-a510,core 0x00000000410fd470,v1,arm/cortex-a710,core 0x00000000410fd490,v1,arm/neoverse-n2,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55FA0C433FE for ; Fri, 20 May 2022 18:17:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352536AbiETSRS (ORCPT ); Fri, 20 May 2022 14:17:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352526AbiETSPz (ORCPT ); Fri, 20 May 2022 14:15:55 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F096112094; Fri, 20 May 2022 11:15:52 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B175C153B; Fri, 20 May 2022 11:15:52 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 386283F718; Fri, 20 May 2022 11:15:50 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 12/13] perf vendors events arm64: Arm Cortex-X2 Date: Fri, 20 May 2022 19:14:54 +0100 Message-Id: <20220520181455.340344-13-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Cortex-X2 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-x2.json which is based on PMU event descriptions from the Arm Cortex-X2 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/cortex-x2/branch.json | 17 ++ .../arch/arm64/arm/cortex-x2/bus.json | 20 +++ .../arch/arm64/arm/cortex-x2/cache.json | 155 ++++++++++++++++++ .../arch/arm64/arm/cortex-x2/exception.json | 47 ++++++ .../arch/arm64/arm/cortex-x2/instruction.json | 134 +++++++++++++++ .../arch/arm64/arm/cortex-x2/memory.json | 41 +++++ .../arch/arm64/arm/cortex-x2/pipeline.json | 23 +++ .../arch/arm64/arm/cortex-x2/trace.json | 29 ++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 9 files changed, 467 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/branch.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/cache.js= on create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/exceptio= n.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/instruct= ion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/memory.j= son create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/pipeline= .json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-x2/trace.js= on diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/branch.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-x2/branch.json new file mode 100644 index 000000000000..2f2d137f5f55 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/branch.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/bus.json b/tool= s/perf/pmu-events/arch/arm64/arm/cortex-x2/bus.json new file mode 100644 index 000000000000..579c1c993d17 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/bus.json @@ -0,0 +1,20 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + }, + { + "ArchStdEvent": "CNT_CYCLES" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/cache.json b/to= ols/perf/pmu-events/arch/arm64/arm/cortex-x2/cache.json new file mode 100644 index 000000000000..0141f749bff3 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/cache.json @@ -0,0 +1,155 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L1D_TLB" + }, + { + "ArchStdEvent": "L1I_TLB" + }, + { + "ArchStdEvent": "L3D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L3D_CACHE" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "DTLB_WALK" + }, + { + "ArchStdEvent": "ITLB_WALK" + }, + { + "ArchStdEvent": "LL_CACHE_RD" + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_LMISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_TLB_RD" + }, + { + "ArchStdEvent": "L1D_TLB_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_TLB_RD" + }, + { + "ArchStdEvent": "L2D_TLB_WR" + }, + { + "ArchStdEvent": "L3D_CACHE_RD" + }, + { + "ArchStdEvent": "L1I_CACHE_LMISS" + }, + { + "ArchStdEvent": "L2D_CACHE_LMISS_RD" + }, + { + "ArchStdEvent": "L3D_CACHE_LMISS_RD" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/exception.json = b/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/exception.json new file mode 100644 index 000000000000..344a2d552ad5 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/exception.json @@ -0,0 +1,47 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_UNDEF" + }, + { + "ArchStdEvent": "EXC_SVC" + }, + { + "ArchStdEvent": "EXC_PABORT" + }, + { + "ArchStdEvent": "EXC_DABORT" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + }, + { + "ArchStdEvent": "EXC_SMC" + }, + { + "ArchStdEvent": "EXC_HVC" + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER" + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ" + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/instruction.jso= n b/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/instruction.json new file mode 100644 index 000000000000..964f47c6b099 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/instruction.json @@ -0,0 +1,134 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_RETIRED" + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED" + }, + { + "ArchStdEvent": "OP_RETIRED" + }, + { + "ArchStdEvent": "OP_SPEC" + }, + { + "ArchStdEvent": "LDREX_SPEC" + }, + { + "ArchStdEvent": "STREX_PASS_SPEC" + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC" + }, + { + "ArchStdEvent": "STREX_SPEC" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "PC_WRITE_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "ArchStdEvent": "DSB_SPEC" + }, + { + "ArchStdEvent": "DMB_SPEC" + }, + { + "ArchStdEvent": "RC_LD_SPEC" + }, + { + "ArchStdEvent": "RC_ST_SPEC" + }, + { + "ArchStdEvent": "ASE_INST_SPEC" + }, + { + "ArchStdEvent": "SVE_INST_SPEC" + }, + { + "ArchStdEvent": "FP_HP_SPEC" + }, + { + "ArchStdEvent": "FP_SP_SPEC" + }, + { + "ArchStdEvent": "FP_DP_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_EMPTY_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_FULL_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_PARTIAL_SPEC" + }, + { + "ArchStdEvent": "SVE_PRED_NOT_FULL_SPEC" + }, + { + "ArchStdEvent": "SVE_LDFF_SPEC" + }, + { + "ArchStdEvent": "SVE_LDFF_FAULT_SPEC" + }, + { + "ArchStdEvent": "FP_SCALE_OPS_SPEC" + }, + { + "ArchStdEvent": "FP_FIXED_OPS_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT8_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT16_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT32_SPEC" + }, + { + "ArchStdEvent": "ASE_SVE_INT64_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/memory.json b/t= ools/perf/pmu-events/arch/arm64/arm/cortex-x2/memory.json new file mode 100644 index 000000000000..7b2b21ac150f --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/memory.json @@ -0,0 +1,41 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "REMOTE_ACCESS" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC" + }, + { + "ArchStdEvent": "LDST_ALIGN_LAT" + }, + { + "ArchStdEvent": "LD_ALIGN_LAT" + }, + { + "ArchStdEvent": "ST_ALIGN_LAT" + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED" + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_CHECKED_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/pipeline.json b= /tools/perf/pmu-events/arch/arm64/arm/cortex-x2/pipeline.json new file mode 100644 index 000000000000..f9fae15f7555 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/pipeline.json @@ -0,0 +1,23 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + }, + { + "ArchStdEvent": "STALL" + }, + { + "ArchStdEvent": "STALL_SLOT_BACKEND" + }, + { + "ArchStdEvent": "STALL_SLOT_FRONTEND" + }, + { + "ArchStdEvent": "STALL_SLOT" + }, + { + "ArchStdEvent": "STALL_BACKEND_MEM" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/trace.json b/to= ols/perf/pmu-events/arch/arm64/arm/cortex-x2/trace.json new file mode 100644 index 000000000000..3116135c59e2 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-x2/trace.json @@ -0,0 +1,29 @@ +[ + { + "ArchStdEvent": "TRB_WRAP" + }, + { + "ArchStdEvent": "TRCEXTOUT0" + }, + { + "ArchStdEvent": "TRCEXTOUT1" + }, + { + "ArchStdEvent": "TRCEXTOUT2" + }, + { + "ArchStdEvent": "TRCEXTOUT3" + }, + { + "ArchStdEvent": "CTI_TRIGOUT4" + }, + { + "ArchStdEvent": "CTI_TRIGOUT5" + }, + { + "ArchStdEvent": "CTI_TRIGOUT6" + }, + { + "ArchStdEvent": "CTI_TRIGOUT7" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index 32c4cd0ba2aa..14ff5ab9dbde 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -30,6 +30,7 @@ 0x00000000410fd440,v1,arm/cortex-x1,core 0x00000000410fd460,v1,arm/cortex-a510,core 0x00000000410fd470,v1,arm/cortex-a710,core +0x00000000410fd480,v1,arm/cortex-x2,core 0x00000000410fd490,v1,arm/neoverse-n2,core 0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000430f0af0,v1,cavium/thunderx2,core --=20 2.25.1 From nobody Thu May 7 19:05:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06FACC433EF for ; Fri, 20 May 2022 18:17:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352632AbiETSRX (ORCPT ); Fri, 20 May 2022 14:17:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352573AbiETSP5 (ORCPT ); Fri, 20 May 2022 14:15:57 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id ACAF7165A1; Fri, 20 May 2022 11:15:55 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6F8F11570; Fri, 20 May 2022 11:15:55 -0700 (PDT) Received: from hype-n1-sdp.warwick.arm.com (hype-n1-sdp.warwick.arm.com [10.32.32.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EA5D73F718; Fri, 20 May 2022 11:15:52 -0700 (PDT) From: Nick Forrington To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org Cc: Nick Forrington , John Garry , Will Deacon , James Clark , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Andrew Kilroy , Kajol Jain , Andi Kleen , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 13/13] perf vendors events arm64: Arm Neoverse E1 Date: Fri, 20 May 2022 19:14:55 +0100 Message-Id: <20220520181455.340344-14-nick.forrington@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220520181455.340344-1-nick.forrington@arm.com> References: <20220520181455.340344-1-nick.forrington@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add PMU events for Arm Neoverse E1 Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/neoverse-e1.json which is based on PMU event descriptions from the Arm Neoverse E1 Technical Reference Manual. Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry Signed-off-by: Nick Forrington --- .../arch/arm64/arm/neoverse-e1/branch.json | 17 +++ .../arch/arm64/arm/neoverse-e1/bus.json | 17 +++ .../arch/arm64/arm/neoverse-e1/cache.json | 107 ++++++++++++++++++ .../arch/arm64/arm/neoverse-e1/exception.json | 14 +++ .../arm64/arm/neoverse-e1/instruction.json | 65 +++++++++++ .../arch/arm64/arm/neoverse-e1/memory.json | 23 ++++ .../arch/arm64/arm/neoverse-e1/pipeline.json | 8 ++ .../arch/arm64/arm/neoverse-e1/spe.json | 14 +++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + 9 files changed, 266 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch= .json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.js= on create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.= json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/except= ion.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instru= ction.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory= .json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeli= ne.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.js= on diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json b= /tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json new file mode 100644 index 000000000000..2f2d137f5f55 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/branch.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "BR_PRED" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json b/to= ols/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json new file mode 100644 index 000000000000..75d850b781ac --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/bus.json @@ -0,0 +1,17 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS" + }, + { + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json b/= tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json new file mode 100644 index 000000000000..3ad15e3a93a9 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/cache.json @@ -0,0 +1,107 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L1D_CACHE" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "ArchStdEvent": "L1I_CACHE" + }, + { + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "ArchStdEvent": "L2D_CACHE" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "ArchStdEvent": "L1D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L1D_TLB" + }, + { + "ArchStdEvent": "L1I_TLB" + }, + { + "ArchStdEvent": "L3D_CACHE_ALLOCATE" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL" + }, + { + "ArchStdEvent": "L3D_CACHE" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL" + }, + { + "ArchStdEvent": "L2D_TLB" + }, + { + "ArchStdEvent": "DTLB_WALK" + }, + { + "ArchStdEvent": "ITLB_WALK" + }, + { + "ArchStdEvent": "LL_CACHE_RD" + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L3D_CACHE_RD" + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL_RD" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.jso= n b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json new file mode 100644 index 000000000000..27c3fe9c831a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/exception.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_FIQ" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.j= son b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json new file mode 100644 index 000000000000..6c3b8f772e7f --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/instruction.json @@ -0,0 +1,65 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "ArchStdEvent": "LD_RETIRED" + }, + { + "ArchStdEvent": "ST_RETIRED" + }, + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "PC_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_IMMED_RETIRED" + }, + { + "ArchStdEvent": "BR_RETURN_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "ArchStdEvent": "BR_RETIRED" + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json b= /tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json new file mode 100644 index 000000000000..78ed6dfcedc1 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/memory.json @@ -0,0 +1,23 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "REMOTE_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json= b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json new file mode 100644 index 000000000000..eeac798d403a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/pipeline.json @@ -0,0 +1,8 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "ArchStdEvent": "STALL_BACKEND" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json b/to= ols/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json new file mode 100644 index 000000000000..20f2165c85fe --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-e1/spe.json @@ -0,0 +1,14 @@ +[ + { + "ArchStdEvent": "SAMPLE_POP" + }, + { + "ArchStdEvent": "SAMPLE_FEED" + }, + { + "ArchStdEvent": "SAMPLE_FILTRATE" + }, + { + "ArchStdEvent": "SAMPLE_COLLISION" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-= events/arch/arm64/mapfile.csv index 14ff5ab9dbde..ed29e4433c67 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -32,6 +32,7 @@ 0x00000000410fd470,v1,arm/cortex-a710,core 0x00000000410fd480,v1,arm/cortex-x2,core 0x00000000410fd490,v1,arm/neoverse-n2,core +0x00000000410fd4a0,v1,arm/neoverse-e1,core 0x00000000420f5160,v1,cavium/thunderx2,core 0x00000000430f0af0,v1,cavium/thunderx2,core 0x00000000460f0010,v1,fujitsu/a64fx,core --=20 2.25.1