From nobody Sun Sep 22 03:24:27 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D671C433EF for ; Fri, 20 May 2022 13:33:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349876AbiETNdd (ORCPT ); Fri, 20 May 2022 09:33:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349823AbiETNdQ (ORCPT ); Fri, 20 May 2022 09:33:16 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFBD7163F45; Fri, 20 May 2022 06:33:14 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 03B501F463C2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1653053593; bh=cXo3YsE0OfrL8V3lpZRyZ78kDPt4+NdotzMnyfoCs5E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RxMpqV+oXdfwcVD0PJs5lOPr9ZaiQ5A8AU+QbZz6gplaOxdXYDaaAflReiTJh7SrZ QqMwW6Kt5RE+oQd5fUkK+kkacAm0lKwVnW8MLvXo2L0tjObqvCedl76fFhxTH7QbPe qqsAyssCpiHwaDOkPFuV1BQLfXKc9c0vjnCBqXhs6RFrFLj7ziCbxjsRO2QTj33fMf PEkxbWDs3d+bjWtdjbuXE3Wx2x8oi0C19fM8l2O21c8aQeSanEIhUxRVrbqJbGjwz6 HUiDaZS1dYhJDJ7LnSqxyNkKDjEyxEfrjX59LXcOd5UQoGzrnfresJ8pQEzRh1S5hd 0SIV6l/QaK8Jw== From: AngeloGioacchino Del Regno To: lgirdwood@gmail.com Cc: broonie@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH 4/4] regulator: Add driver for MT6332 PMIC regulators Date: Fri, 20 May 2022 15:33:05 +0200 Message-Id: <20220520133305.265310-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520133305.265310-1-angelogioacchino.delregno@collabora.com> References: <20220520133305.265310-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a driver for the regulators found in the MT6332 PMICs, including six buck and four LDO regulators. Signed-off-by: AngeloGioacchino Del Regno --- drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6332-regulator.c | 431 +++++++++++++++++++++ include/linux/regulator/mt6332-regulator.h | 27 ++ 4 files changed, 468 insertions(+) create mode 100644 drivers/regulator/mt6332-regulator.c create mode 100644 include/linux/regulator/mt6332-regulator.h diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index dfb52b093c6f..511441acb592 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -786,6 +786,15 @@ config REGULATOR_MT6331 This driver supports the control of different power rails of device through regulator interface =20 +config REGULATOR_MT6332 + tristate "MediaTek MT6332 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6332 PMIC. + This driver supports the control of different power rails of device + through regulator interface + config REGULATOR_MT6358 tristate "MediaTek MT6358 PMIC" depends on MFD_MT6397 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 3799e2673825..13dbac706ed8 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -95,6 +95,7 @@ obj-$(CONFIG_REGULATOR_MT6311) +=3D mt6311-regulator.o obj-$(CONFIG_REGULATOR_MT6315) +=3D mt6315-regulator.o obj-$(CONFIG_REGULATOR_MT6323) +=3D mt6323-regulator.o obj-$(CONFIG_REGULATOR_MT6331) +=3D mt6331-regulator.o +obj-$(CONFIG_REGULATOR_MT6332) +=3D mt6332-regulator.o obj-$(CONFIG_REGULATOR_MT6358) +=3D mt6358-regulator.o obj-$(CONFIG_REGULATOR_MT6359) +=3D mt6359-regulator.o obj-$(CONFIG_REGULATOR_MT6360) +=3D mt6360-regulator.o diff --git a/drivers/regulator/mt6332-regulator.c b/drivers/regulator/mt633= 2-regulator.c new file mode 100644 index 000000000000..fdad39eeded3 --- /dev/null +++ b/drivers/regulator/mt6332-regulator.c @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + * + * Based on mt6323-regulator.c, + * Copyright (c) 2016 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MT6332_LDO_MODE_NORMAL 0 +#define MT6332_LDO_MODE_LP 1 + +/* + * MT6332 regulators information + * + * @desc: standard fields of regulator description. + * @qi: Mask for query enable signal status of regulators + * @vselon_reg: Register sections for hardware control mode of bucks + * @vselctrl_reg: Register for controlling the buck control mode. + * @vselctrl_mask: Mask for query buck's voltage control mode. + * @status_reg: Register for regulator enable status where qi unavailable + * @status_mask: Mask for querying regulator enable status + */ +struct mt6332_regulator_info { + struct regulator_desc desc; + u32 qi; + u32 vselon_reg; + u32 vselctrl_reg; + u32 vselctrl_mask; + u32 modeset_reg; + u32 modeset_mask; + u32 status_reg; + u32 status_mask; +}; + +#define MT6332_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ + vosel, vosel_mask, voselon, vosel_ctrl) \ +[MT6332_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6332_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6332_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D (max - min)/step + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(0), \ + }, \ + .qi =3D BIT(13), \ + .vselon_reg =3D voselon, \ + .vselctrl_reg =3D vosel_ctrl, \ + .vselctrl_mask =3D BIT(1), \ + .status_mask =3D 0, \ +} + +#define MT6332_LDO_LINEAR(match, vreg, min, max, step, volt_ranges, \ + enreg, vosel, vosel_mask, voselon, vosel_ctrl)\ +[MT6332_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6332_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6332_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D (max - min)/step + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(0), \ + }, \ + .qi =3D BIT(15), \ + .vselon_reg =3D voselon, \ + .vselctrl_reg =3D vosel_ctrl, \ + .vselctrl_mask =3D BIT(1), \ + .status_mask =3D 0, \ +} + +#define MT6332_LDO_AO(match, vreg, ldo_volt_table, vosel, vosel_mask) \ +[MT6332_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6332_volt_table_ao_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6332_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ARRAY_SIZE(ldo_volt_table), \ + .volt_table =3D ldo_volt_table, \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + }, \ +} + +#define MT6332_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ + vosel_mask, _modeset_reg, _modeset_mask) \ +[MT6332_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6332_volt_table_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6332_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ARRAY_SIZE(ldo_volt_table), \ + .volt_table =3D ldo_volt_table, \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ + .status_mask =3D 0, \ +} + +#define MT6332_REG_FIXED(match, vreg, enreg, enbit, qibit, volt, \ + stabit, _modeset_reg, _modeset_mask) \ +[MT6332_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .ops =3D &mt6332_volt_fixed_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6332_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .min_uV =3D volt, \ + }, \ + .qi =3D BIT(qibit), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ + .status_reg =3D MT6332_EN_STATUS0, \ + .status_mask =3D BIT(stabit), \ +} + +static const struct linear_range boost_volt_range[] =3D { + REGULATOR_LINEAR_RANGE(3500000, 0, 0x7f, 31250), +}; + +static const struct linear_range buck_volt_range[] =3D { + REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250), +}; + +static const struct linear_range buck_pa_volt_range[] =3D { + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), +}; + +static const struct linear_range buck_rf_volt_range[] =3D { + REGULATOR_LINEAR_RANGE(1050000, 0, 0x7f, 9375), +}; + +static const unsigned int ldo_volt_table1[] =3D { + 2800000, 3000000, 0, 3200000 +}; + +static const unsigned int ldo_volt_table2[] =3D { + 1200000, 1300000, 1400000, 1500000, 1600000, 1700000, 1800000, 1800000, +}; + +static int mt6332_get_status(struct regulator_dev *rdev) +{ + struct mt6332_regulator_info *info =3D rdev_get_drvdata(rdev); + u32 reg, en_mask, regval; + int ret; + + if (info->qi > 0) { + reg =3D info->desc.enable_reg; + en_mask =3D info->qi; + } else { + reg =3D info->status_reg; + en_mask =3D info->status_mask; + } + + ret =3D regmap_read(rdev->regmap, reg, ®val); + if (ret !=3D 0) { + dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret); + return ret; + } + + return (regval & en_mask) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; +} + +static int mt6332_ldo_set_mode(struct regulator_dev *rdev, unsigned int mo= de) +{ + int ret, val =3D 0; + struct mt6332_regulator_info *info =3D rdev_get_drvdata(rdev); + + if (!info->modeset_mask) { + dev_err(&rdev->dev, "regulator %s doesn't support set_mode\n", + info->desc.name); + return -EINVAL; + } + + switch (mode) { + case REGULATOR_MODE_STANDBY: + val =3D MT6332_LDO_MODE_LP; + break; + case REGULATOR_MODE_NORMAL: + val =3D MT6332_LDO_MODE_NORMAL; + break; + default: + return -EINVAL; + } + + val <<=3D ffs(info->modeset_mask) - 1; + + ret =3D regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6332_ldo_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6332_regulator_info *info =3D rdev_get_drvdata(rdev); + + if (!info->modeset_mask) { + dev_err(&rdev->dev, "regulator %s doesn't support get_mode\n", + info->desc.name); + return -EINVAL; + } + + ret =3D regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &=3D info->modeset_mask; + val >>=3D ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode =3D REGULATOR_MODE_STANDBY; + else + mode =3D REGULATOR_MODE_NORMAL; + + return mode; +} + +static const struct regulator_ops mt6332_volt_range_ops =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .get_status =3D mt6332_get_status, +}; + +static const struct regulator_ops mt6332_volt_table_ops =3D { + .list_voltage =3D regulator_list_voltage_table, + .map_voltage =3D regulator_map_voltage_iterate, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .get_status =3D mt6332_get_status, + .set_mode =3D mt6332_ldo_set_mode, + .get_mode =3D mt6332_ldo_get_mode, +}; + +static const struct regulator_ops mt6332_volt_table_ao_ops =3D { + .list_voltage =3D regulator_list_voltage_table, + .map_voltage =3D regulator_map_voltage_iterate, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .set_mode =3D mt6332_ldo_set_mode, + .get_mode =3D mt6332_ldo_get_mode, +}; + +static const struct regulator_ops mt6332_volt_fixed_ops =3D { + .list_voltage =3D regulator_list_voltage_linear, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .get_status =3D mt6332_get_status, + .set_mode =3D mt6332_ldo_set_mode, + .get_mode =3D mt6332_ldo_get_mode, +}; + +/* The array is indexed by id(MT6332_ID_XXX) */ +static struct mt6332_regulator_info mt6332_regulators[] =3D { + MT6332_BUCK("buck-vdram", VDRAM, 700000, 1493750, 6250, buck_volt_range, + MT6332_EN_STATUS0, MT6332_VDRAM_CON11, GENMASK(6, 0), + MT6332_VDRAM_CON12, MT6332_VDRAM_CON7), + MT6332_BUCK("buck-vdvfs2", VDVFS2, 700000, 1312500, 6250, buck_volt_range, + MT6332_VDVFS2_CON9, MT6332_VDVFS2_CON11, GENMASK(6, 0), + MT6332_VDVFS2_CON12, MT6332_VDVFS2_CON7), + MT6332_BUCK("buck-vpa", VPA, 500000, 3400000, 50000, buck_pa_volt_range, + MT6332_VPA_CON9, MT6332_VPA_CON11, GENMASK(5, 0), + MT6332_VPA_CON12, MT6332_VPA_CON7), + MT6332_BUCK("buck-vrf18a", VRF1, 1050000, 2240625, 9375, buck_rf_volt_ran= ge, + MT6332_VRF1_CON9, MT6332_VRF1_CON11, GENMASK(6, 0), + MT6332_VRF1_CON12, MT6332_VRF1_CON7), + MT6332_BUCK("buck-vrf18b", VRF2, 1050000, 2240625, 9375, buck_rf_volt_ran= ge, + MT6332_VRF2_CON9, MT6332_VRF2_CON11, GENMASK(6, 0), + MT6332_VRF2_CON12, MT6332_VRF2_CON7), + MT6332_BUCK("buck-vsbst", VSBST, 3500000, 7468750, 31250, boost_volt_rang= e, + MT6332_VSBST_CON8, MT6332_VSBST_CON12, GENMASK(6, 0), + MT6332_VSBST_CON13, MT6332_VSBST_CON8), + MT6332_LDO("ldo-vauxb32", VAUXB32, ldo_volt_table1, MT6332_LDO_CON1, 10, + MT6332_LDO_CON9, GENMASK(6, 5), MT6332_LDO_CON1, GENMASK(1, 0)), + MT6332_REG_FIXED("ldo-vbif28", VBIF28, MT6332_LDO_CON2, 10, 0, 2800000, 1= , 0, 0), + MT6332_REG_FIXED("ldo-vusb33", VUSB33, MT6332_LDO_CON3, 10, 0, 3300000, 2= , 0, 0), + MT6332_LDO_LINEAR("ldo-vsram", VSRAM_DVFS2, 700000, 1493750, 6250, buck_v= olt_range, + MT6332_EN_STATUS0, MT6332_LDO_CON8, GENMASK(15, 9), + MT6332_VDVFS2_CON23, MT6332_VDVFS2_CON22), + MT6332_LDO_AO("ldo-vdig18", VDIG18, ldo_volt_table2, MT6332_LDO_CON12, GE= NMASK(11, 9)), +}; + +static int mt6332_set_buck_vosel_reg(struct platform_device *pdev) +{ + struct mt6397_chip *mt6332 =3D dev_get_drvdata(pdev->dev.parent); + int i; + u32 regval; + + for (i =3D 0; i < MT6332_ID_VREG_MAX; i++) { + if (mt6332_regulators[i].vselctrl_reg) { + if (regmap_read(mt6332->regmap, + mt6332_regulators[i].vselctrl_reg, + ®val) < 0) { + dev_err(&pdev->dev, + "Failed to read buck ctrl\n"); + return -EIO; + } + + if (regval & mt6332_regulators[i].vselctrl_mask) { + mt6332_regulators[i].desc.vsel_reg =3D + mt6332_regulators[i].vselon_reg; + } + } + } + + return 0; +} + +static int mt6332_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6332 =3D dev_get_drvdata(pdev->dev.parent); + struct regulator_config config =3D {}; + struct regulator_dev *rdev; + int i; + u32 reg_value; + + /* Query buck controller to select activated voltage register part */ + if (mt6332_set_buck_vosel_reg(pdev)) + return -EIO; + + /* Read PMIC chip revision to update constraints and voltage table */ + if (regmap_read(mt6332->regmap, MT6332_HWCID, ®_value) < 0) { + dev_err(&pdev->dev, "Failed to read Chip ID\n"); + return -EIO; + } + reg_value &=3D GENMASK(7, 0); + + dev_info(&pdev->dev, "Chip ID =3D 0x%x\n", reg_value); + + /* + * ChipID 0x10 is "MT6332 E1", has a different voltage table and + * it's currently not supported in this driver. Upon detection of + * this ID, refuse to register the regulators, as we will wrongly + * interpret the VSEL for this revision, potentially overvolting + * some device. + */ + if (reg_value =3D=3D 0x10) { + dev_err(&pdev->dev, "Chip version not supported. Bailing out.\n"); + return -EINVAL; + } + + for (i =3D 0; i < MT6332_ID_VREG_MAX; i++) { + config.dev =3D &pdev->dev; + config.driver_data =3D &mt6332_regulators[i]; + config.regmap =3D mt6332->regmap; + rdev =3D devm_regulator_register(&pdev->dev, + &mt6332_regulators[i].desc, &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6332_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + return 0; +} + +static const struct platform_device_id mt6332_platform_ids[] =3D { + {"mt6332-regulator", 0}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6332_platform_ids); + +static struct platform_driver mt6332_regulator_driver =3D { + .driver =3D { + .name =3D "mt6332-regulator", + }, + .probe =3D mt6332_regulator_probe, + .id_table =3D mt6332_platform_ids, +}; + +module_platform_driver(mt6332_regulator_driver); + +MODULE_AUTHOR("AngeloGioacchino Del Regno "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6332 PMIC"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/regulator/mt6332-regulator.h b/include/linux/reg= ulator/mt6332-regulator.h new file mode 100644 index 000000000000..af5e3ed31029 --- /dev/null +++ b/include/linux/regulator/mt6332-regulator.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 Collabora Ltd. + * Author: AngeloGioacchino Del Regno + */ + +#ifndef __LINUX_REGULATOR_MT6332_H +#define __LINUX_REGULATOR_MT6332_H + +enum { + /* BUCK */ + MT6332_ID_VDRAM =3D 0, + MT6332_ID_VDVFS2, + MT6332_ID_VPA, + MT6332_ID_VRF1, + MT6332_ID_VRF2, + MT6332_ID_VSBST, + /* LDO */ + MT6332_ID_VAUXB32, + MT6332_ID_VBIF28, + MT6332_ID_VDIG18, + MT6332_ID_VSRAM_DVFS2, + MT6332_ID_VUSB33, + MT6332_ID_VREG_MAX +}; + +#endif /* __LINUX_REGULATOR_MT6332_H */ --=20 2.35.1