From nobody Sun Sep 22 03:32:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9313C433EF for ; Fri, 20 May 2022 12:41:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349430AbiETMln (ORCPT ); Fri, 20 May 2022 08:41:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349435AbiETMk6 (ORCPT ); Fri, 20 May 2022 08:40:58 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27E8A111F; Fri, 20 May 2022 05:40:51 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 768931F462E1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1653050448; bh=+kbdRYsHxe7PHtaPpuxGhKRfW2O1PwuOiUr+rtEeRxY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U1ebcW7jSpjpGZ5vMRp7vlIg70ya+Mv38Al6huikRRQVbjh83elt02K4kiu7z1pZ/ zBKd6qwMu3dKUuS2r3mmRigWmMLiHUFX1WcOr4HtctPMiH+m3NAO8N8v46jW4RqIFz 264LpVSRaxVvyT/040zkeG1pBAP5nWiLeCiinhPKnw9SZ1as7D+X4RpguzBkbKJBy6 n2JQmQKGPU4oTN9/PAxvGB2fNafw86Ew6EnmjpUrWfmE4sw9asH4deouiGyOcxyzrm ylPzU8h75BInT7cVR26hoHdJYVlgphTXZholSbtrgak5LnMipWQYNVRh4h/ASh6Wxt omeN0q2TRVbFA== From: AngeloGioacchino Del Regno To: lee.jones@linaro.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, zhiyong.tao@mediatek.com, henryc.chen@mediatek.com, johnson.wang@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] soc: mediatek: pwrap: Add support for MT6795 Helio X10 Date: Fri, 20 May 2022 14:40:39 +0200 Message-Id: <20220520124039.228314-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> References: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the necessary bits to support the MT6795 Helio X10 smartphone SoC: this is always paired with a MT6331 PMIC, with MT6332 companion. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 131 ++++++++++++++++++++++++++- 1 file changed, 130 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index f2fe51feb237..200c53e2f76a 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -639,6 +639,91 @@ static int mt6779_regs[] =3D { [PWRAP_WACS2_VLDCLR] =3D 0xC28, }; =20 +static int mt6795_regs[] =3D { + [PWRAP_MUX_SEL] =3D 0x0, + [PWRAP_WRAP_EN] =3D 0x4, + [PWRAP_DIO_EN] =3D 0x8, + [PWRAP_SIDLY] =3D 0xc, + [PWRAP_RDDMY] =3D 0x10, + [PWRAP_SI_CK_CON] =3D 0x14, + [PWRAP_CSHEXT_WRITE] =3D 0x18, + [PWRAP_CSHEXT_READ] =3D 0x1c, + [PWRAP_CSLEXT_START] =3D 0x20, + [PWRAP_CSLEXT_END] =3D 0x24, + [PWRAP_STAUPD_PRD] =3D 0x28, + [PWRAP_STAUPD_GRPEN] =3D 0x2c, + [PWRAP_EINT_STA0_ADR] =3D 0x30, + [PWRAP_EINT_STA1_ADR] =3D 0x34, + [PWRAP_STAUPD_MAN_TRIG] =3D 0x40, + [PWRAP_STAUPD_STA] =3D 0x44, + [PWRAP_WRAP_STA] =3D 0x48, + [PWRAP_HARB_INIT] =3D 0x4c, + [PWRAP_HARB_HPRIO] =3D 0x50, + [PWRAP_HIPRIO_ARB_EN] =3D 0x54, + [PWRAP_HARB_STA0] =3D 0x58, + [PWRAP_HARB_STA1] =3D 0x5c, + [PWRAP_MAN_EN] =3D 0x60, + [PWRAP_MAN_CMD] =3D 0x64, + [PWRAP_MAN_RDATA] =3D 0x68, + [PWRAP_MAN_VLDCLR] =3D 0x6c, + [PWRAP_WACS0_EN] =3D 0x70, + [PWRAP_INIT_DONE0] =3D 0x74, + [PWRAP_WACS0_CMD] =3D 0x78, + [PWRAP_WACS0_RDATA] =3D 0x7c, + [PWRAP_WACS0_VLDCLR] =3D 0x80, + [PWRAP_WACS1_EN] =3D 0x84, + [PWRAP_INIT_DONE1] =3D 0x88, + [PWRAP_WACS1_CMD] =3D 0x8c, + [PWRAP_WACS1_RDATA] =3D 0x90, + [PWRAP_WACS1_VLDCLR] =3D 0x94, + [PWRAP_WACS2_EN] =3D 0x98, + [PWRAP_INIT_DONE2] =3D 0x9c, + [PWRAP_WACS2_CMD] =3D 0xa0, + [PWRAP_WACS2_RDATA] =3D 0xa4, + [PWRAP_WACS2_VLDCLR] =3D 0xa8, + [PWRAP_INT_EN] =3D 0xac, + [PWRAP_INT_FLG_RAW] =3D 0xb0, + [PWRAP_INT_FLG] =3D 0xb4, + [PWRAP_INT_CLR] =3D 0xb8, + [PWRAP_SIG_ADR] =3D 0xbc, + [PWRAP_SIG_MODE] =3D 0xc0, + [PWRAP_SIG_VALUE] =3D 0xc4, + [PWRAP_SIG_ERRVAL] =3D 0xc8, + [PWRAP_CRC_EN] =3D 0xcc, + [PWRAP_TIMER_EN] =3D 0xd0, + [PWRAP_TIMER_STA] =3D 0xd4, + [PWRAP_WDT_UNIT] =3D 0xd8, + [PWRAP_WDT_SRC_EN] =3D 0xdc, + [PWRAP_WDT_FLG] =3D 0xe0, + [PWRAP_DEBUG_INT_SEL] =3D 0xe4, + [PWRAP_DVFS_ADR0] =3D 0xe8, + [PWRAP_DVFS_WDATA0] =3D 0xec, + [PWRAP_DVFS_ADR1] =3D 0xf0, + [PWRAP_DVFS_WDATA1] =3D 0xf4, + [PWRAP_DVFS_ADR2] =3D 0xf8, + [PWRAP_DVFS_WDATA2] =3D 0xfc, + [PWRAP_DVFS_ADR3] =3D 0x100, + [PWRAP_DVFS_WDATA3] =3D 0x104, + [PWRAP_DVFS_ADR4] =3D 0x108, + [PWRAP_DVFS_WDATA4] =3D 0x10c, + [PWRAP_DVFS_ADR5] =3D 0x110, + [PWRAP_DVFS_WDATA5] =3D 0x114, + [PWRAP_DVFS_ADR6] =3D 0x118, + [PWRAP_DVFS_WDATA6] =3D 0x11c, + [PWRAP_DVFS_ADR7] =3D 0x120, + [PWRAP_DVFS_WDATA7] =3D 0x124, + [PWRAP_SPMINF_STA] =3D 0x128, + [PWRAP_CIPHER_KEY_SEL] =3D 0x12c, + [PWRAP_CIPHER_IV_SEL] =3D 0x130, + [PWRAP_CIPHER_EN] =3D 0x134, + [PWRAP_CIPHER_RDY] =3D 0x138, + [PWRAP_CIPHER_MODE] =3D 0x13c, + [PWRAP_CIPHER_SWRST] =3D 0x140, + [PWRAP_DCM_EN] =3D 0x144, + [PWRAP_DCM_DBC_PRD] =3D 0x148, + [PWRAP_EXT_CK] =3D 0x14c, +}; + static int mt6797_regs[] =3D { [PWRAP_MUX_SEL] =3D 0x0, [PWRAP_WRAP_EN] =3D 0x4, @@ -1168,6 +1253,7 @@ enum pwrap_type { PWRAP_MT2701, PWRAP_MT6765, PWRAP_MT6779, + PWRAP_MT6795, PWRAP_MT6797, PWRAP_MT6873, PWRAP_MT7622, @@ -1585,6 +1671,20 @@ static void pwrap_init_chip_select_ext(struct pmic_w= rapper *wrp, u8 hext_write, static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) { switch (wrp->master->type) { + case PWRAP_MT6795: + if (wrp->slave->type =3D=3D PMIC_MT6331) { + const u32 *dew_regs =3D wrp->slave->dew_regs; + + pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + + if (wrp->slave->comp_type =3D=3D PMIC_MT6332) { + dew_regs =3D wrp->slave->comp_dew_regs; + pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + } + } + pwrap_writel(wrp, 0x88, PWRAP_RDDMY); + pwrap_init_chip_select_ext(wrp, 15, 15, 15, 15); + break; case PWRAP_MT8173: pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); break; @@ -1679,6 +1779,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) case PWRAP_MT2701: case PWRAP_MT6765: case PWRAP_MT6779: + case PWRAP_MT6795: case PWRAP_MT6797: case PWRAP_MT8173: case PWRAP_MT8186: @@ -1848,6 +1949,19 @@ static int pwrap_mt2701_init_soc_specific(struct pmi= c_wrapper *wrp) return 0; } =20 +static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp) +{ + pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN); + + if (wrp->slave->type =3D=3D PMIC_MT6331) + pwrap_writel(wrp, 0x1b4, PWRAP_EINT_STA0_ADR); + + if (wrp->slave->comp_type =3D=3D PMIC_MT6332) + pwrap_writel(wrp, 0x8112, PWRAP_EINT_STA1_ADR); + + return 0; +} + static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp) { pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD); @@ -1883,7 +1997,8 @@ static int pwrap_init(struct pmic_wrapper *wrp) if (wrp->rstc_bridge) reset_control_reset(wrp->rstc_bridge); =20 - if (wrp->master->type =3D=3D PWRAP_MT8173) { + if (wrp->master->type =3D=3D PWRAP_MT8173 || + wrp->master->type =3D=3D PWRAP_MT6795) { /* Enable DCM */ pwrap_writel(wrp, 3, PWRAP_DCM_EN); pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); @@ -2119,6 +2234,19 @@ static const struct pmic_wrapper_type pwrap_mt6779 = =3D { .init_soc_specific =3D NULL, }; =20 +static const struct pmic_wrapper_type pwrap_mt6795 =3D { + .regs =3D mt6795_regs, + .type =3D PWRAP_MT6795, + .arb_en_all =3D 0x3f, + .int_en_all =3D ~(u32)(BIT(31) | BIT(2) | BIT(1)), + .int1_en_all =3D 0, + .spi_w =3D PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src =3D PWRAP_WDT_SRC_MASK_NO_STAUPD, + .caps =3D PWRAP_CAP_RESET | PWRAP_CAP_DCM, + .init_reg_clock =3D pwrap_common_init_reg_clock, + .init_soc_specific =3D pwrap_mt6795_init_soc_specific, +}; + static const struct pmic_wrapper_type pwrap_mt6797 =3D { .regs =3D mt6797_regs, .type =3D PWRAP_MT6797, @@ -2239,6 +2367,7 @@ static const struct of_device_id of_pwrap_match_tbl[]= =3D { { .compatible =3D "mediatek,mt2701-pwrap", .data =3D &pwrap_mt2701 }, { .compatible =3D "mediatek,mt6765-pwrap", .data =3D &pwrap_mt6765 }, { .compatible =3D "mediatek,mt6779-pwrap", .data =3D &pwrap_mt6779 }, + { .compatible =3D "mediatek,mt6795-pwrap", .data =3D &pwrap_mt6795 }, { .compatible =3D "mediatek,mt6797-pwrap", .data =3D &pwrap_mt6797 }, { .compatible =3D "mediatek,mt6873-pwrap", .data =3D &pwrap_mt6873 }, { .compatible =3D "mediatek,mt7622-pwrap", .data =3D &pwrap_mt7622 }, --=20 2.35.1