From nobody Sun Sep 22 02:03:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 350BBC433FE for ; Fri, 20 May 2022 12:41:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349452AbiETMlA (ORCPT ); Fri, 20 May 2022 08:41:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242225AbiETMkv (ORCPT ); Fri, 20 May 2022 08:40:51 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3B9EF2; Fri, 20 May 2022 05:40:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 39C0C1F462AB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1653050443; bh=1cI7pJdMnTRIrjJ1RulEP49MI5dUM/5mesdNO1GWVz4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L0tAkU63Gsv6F35bpHi7VC2t0gJZXQNisR3r2SkQXYnbYmOLl8m1uBpD+9P8Rn8Cg QCK0OPu9l6rX7bmbRnLWsDp+WAOjlUg+eaKbfMG9xS37+4uTNfn9nDXkosP5wiPhQj SOMb+swpYgtORdI3xg6n32hrank1MYBliryTbwtr1UtmKdp4on/oCL2ApOoo6cFTtc XexakscSvOEYUUsLtsucBJAFmkDhp0bGlCtKOn6MdpYuBq4q3AVxcnxhtEy1eEoQUh 38r3B3+12vgkLpEwEJUNK1avcv24xDWYmxvT7Rx2uq4enQJAU8sLWEmicST2fvbMtc boLckHEBkraRw== From: AngeloGioacchino Del Regno To: lee.jones@linaro.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, zhiyong.tao@mediatek.com, henryc.chen@mediatek.com, johnson.wang@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] soc: mediatek: pwrap: Move PMIC read test sequence in function Date: Fri, 20 May 2022 14:40:33 +0200 Message-Id: <20220520124039.228314-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> References: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The PMIC read test is performed in two places: pwrap_init_dual_io() and pwrap_init_sidly(). In preparation for adding support for PMICs requiring a companion part, move this sequence to a new function pwrap_pmic_read_test(). Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 32 +++++++++++++++++----------- 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index d8cb0f833645..d0c79ee4c56b 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -1390,6 +1390,18 @@ static int pwrap_regmap_write(void *context, u32 adr= , u32 wdata) return pwrap_write(context, adr, wdata); } =20 +static bool pwrap_pmic_read_test(struct pmic_wrapper *wrp, const u32 *dew_= regs, + u16 read_test_val) +{ + bool is_success; + u32 rdata; + + pwrap_read(wrp, dew_regs[PWRAP_DEW_READ_TEST], &rdata); + is_success =3D ((rdata & U16_MAX) =3D=3D read_test_val); + + return is_success; +} + static int pwrap_reset_spislave(struct pmic_wrapper *wrp) { bool tmp; @@ -1433,18 +1445,18 @@ static int pwrap_reset_spislave(struct pmic_wrapper= *wrp) */ static int pwrap_init_sidly(struct pmic_wrapper *wrp) { - u32 rdata; u32 i; u32 pass =3D 0; + bool read_ok; signed char dly[16] =3D { -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1 }; =20 for (i =3D 0; i < 4; i++) { pwrap_writel(wrp, i, PWRAP_SIDLY); - pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], - &rdata); - if (rdata =3D=3D PWRAP_DEW_READ_TEST_VAL) { + read_ok =3D pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, + PWRAP_DEW_READ_TEST_VAL); + if (read_ok) { dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=3D%x\n", i); pass |=3D 1 << i; } @@ -1464,8 +1476,7 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp) static int pwrap_init_dual_io(struct pmic_wrapper *wrp) { int ret; - bool tmp; - u32 rdata; + bool read_ok, tmp; =20 /* Enable dual IO mode */ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); @@ -1481,12 +1492,9 @@ static int pwrap_init_dual_io(struct pmic_wrapper *w= rp) pwrap_writel(wrp, 1, PWRAP_DIO_EN); =20 /* Read Test */ - pwrap_read(wrp, - wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata); - if (rdata !=3D PWRAP_DEW_READ_TEST_VAL) { - dev_err(wrp->dev, - "Read failed on DIO mode: 0x%04x!=3D0x%04x\n", - PWRAP_DEW_READ_TEST_VAL, rdata); + read_ok =3D pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_REA= D_TEST_VAL); + if (!read_ok) { + dev_err(wrp->dev, "Read failed on DIO mode.\n"); return -EFAULT; } =20 --=20 2.35.1 From nobody Sun Sep 22 02:03:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48471C433F5 for ; Fri, 20 May 2022 12:41:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349486AbiETMlG (ORCPT ); Fri, 20 May 2022 08:41:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349336AbiETMkv (ORCPT ); Fri, 20 May 2022 08:40:51 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A85382F0; Fri, 20 May 2022 05:40:45 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id E96BB1F462B0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1653050444; bh=x06V/XCPzZpmYAgHXtWkmjUfcFKK5jjJPN9DpP31Kf4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fCgpRhpqMw/ZILDXfIXuNwSGMGuhlTYvHEygdNCG1eH2qI0jLyRRDUa7Aye9np1nV KwZKc2Ot/lDUwGKswK5NfQ65IwflRg2Bpm63k3hUQYZhm3EbZdi/UtGJLeB9h/fgtX Dddji/ANIrrp6oMbS6b3tI5dubjyWLHOVkZXpcdYDcrj6UrhCPyGbRe4LvEvCK981v l6rSpENJmrUGVTZBbhoFqm3HJ3FCC8mk1yvvV6kT25IXgFxnDerQM2RrA/q6LOlSJ+ fQywzCUNb9VTAWVX5vDoLa9BvI3y7SFyLk4cwRIr86R8R3PeY2JF0UYJn4Q8DtZlYU tAenNqqD0cTzg== From: AngeloGioacchino Del Regno To: lee.jones@linaro.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, zhiyong.tao@mediatek.com, henryc.chen@mediatek.com, johnson.wang@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] soc: mediatek: pwrap: Add kerneldoc for struct pwrap_slv_type Date: Fri, 20 May 2022 14:40:34 +0200 Message-Id: <20220520124039.228314-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> References: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding new members with name abbreviations describe the struct pwrap_slv_type with kerneldoc to enhance human readability. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index d0c79ee4c56b..76b1f7bc8217 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -1155,11 +1155,17 @@ struct pwrap_slv_regops { int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata); }; =20 +/** + * struct pwrap_slv_type - PMIC device wrapper definitions + * @dew_regs: Device Wrapper (DeW) register offsets + * @type: PMIC Type (model) + * @regops: Register R/W ops + * @caps: Capability flags for the target device + */ struct pwrap_slv_type { const u32 *dew_regs; enum pmic_type type; const struct pwrap_slv_regops *regops; - /* Flags indicating the capability for the target slave */ u32 caps; }; =20 --=20 2.35.1 From nobody Sun Sep 22 02:03:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 678B0C43217 for ; Fri, 20 May 2022 12:41:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349508AbiETMlK (ORCPT ); Fri, 20 May 2022 08:41:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349332AbiETMkv (ORCPT ); Fri, 20 May 2022 08:40:51 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DCB8C5D; Fri, 20 May 2022 05:40:46 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id A26CD1F462B4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1653050445; bh=8jcIV3YZX+OFKg3u+2iMVNrP9zKOyojOdJUUR/XsVLk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lQEE/GHAcv4KipbnoenKlk+PP+KlgEfM+bhCn0KilEIbDULyU2eJNnq7v6PQhDPyU QXc7Gxum/cJfspPv+ND7ZxZukSXzC42P8+dMLkaSNwBTO/N3qQOvH//omNO+78Z4JJ eH2Ee4r74YtYR6/4B5XSfvnm5hAwG0PWJpT8tnfTwx9llKC8ovNID5FHWEnUB4Zy8q Ns98qLj3s3+vdpgORKXL9SOiWgzB4r4Qixx3OPcYtbJc1WUnP+7nQV0lccU7eL7GCn oOx8fnlaVeuknFo5L0BmvHQBJ7TMCM2HNfhcLN6ymJPtgrq1ZMglE3vZD+Nes7HfMJ vFlgrepTsNOhw== From: AngeloGioacchino Del Regno To: lee.jones@linaro.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, zhiyong.tao@mediatek.com, henryc.chen@mediatek.com, johnson.wang@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] soc: mediatek: mtk-pmic-wrap: Add support for companion PMICs Date: Fri, 20 May 2022 14:40:35 +0200 Message-Id: <20220520124039.228314-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> References: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some PMICs are designed to work with a companion part, which provides more regulators and/or companion devices such as LED controllers, display backlight controllers, battery charging, fuel gauge, etc: this kind of PMICs are usually present in smartphone platforms, where tight integration is required. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 73 ++++++++++++++++++++++------ 1 file changed, 59 insertions(+), 14 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index 76b1f7bc8217..8a4bb6392c3a 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -47,6 +47,7 @@ =20 /* macro for device wrapper default value */ #define PWRAP_DEW_READ_TEST_VAL 0x5aa5 +#define PWRAP_DEW_COMP_READ_TEST_VAL 0xa55a #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a =20 /* macro for manual command */ @@ -1159,12 +1160,16 @@ struct pwrap_slv_regops { * struct pwrap_slv_type - PMIC device wrapper definitions * @dew_regs: Device Wrapper (DeW) register offsets * @type: PMIC Type (model) + * @comp_dew_regs: Device Wrapper (DeW) register offsets for companion dev= ice + * @comp_type: Companion PMIC Type (model) * @regops: Register R/W ops * @caps: Capability flags for the target device */ struct pwrap_slv_type { const u32 *dew_regs; enum pmic_type type; + const u32 *comp_dew_regs; + enum pmic_type comp_type; const struct pwrap_slv_regops *regops; u32 caps; }; @@ -1483,9 +1488,12 @@ static int pwrap_init_dual_io(struct pmic_wrapper *w= rp) { int ret; bool read_ok, tmp; + bool comp_read_ok =3D true; =20 /* Enable dual IO mode */ pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1); + if (wrp->slave->comp_dew_regs) + pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_DIO_EN], 1); =20 /* Check IDLE & INIT_DONE in advance */ ret =3D readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp, @@ -1499,8 +1507,14 @@ static int pwrap_init_dual_io(struct pmic_wrapper *w= rp) =20 /* Read Test */ read_ok =3D pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_REA= D_TEST_VAL); - if (!read_ok) { - dev_err(wrp->dev, "Read failed on DIO mode.\n"); + if (wrp->slave->comp_dew_regs) + comp_read_ok =3D pwrap_pmic_read_test(wrp, wrp->slave->comp_dew_regs, + PWRAP_DEW_COMP_READ_TEST_VAL); + if (!read_ok || !comp_read_ok) { + dev_err(wrp->dev, "Read failed on DIO mode. Main PMIC %s%s\n", + !read_ok ? "fail" : "success", + wrp->slave->comp_dew_regs && !comp_read_ok ? + ", Companion PMIC fail" : ""); return -EFAULT; } =20 @@ -1575,19 +1589,41 @@ static bool pwrap_is_cipher_ready(struct pmic_wrapp= er *wrp) return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1; } =20 -static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) +static bool __pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp, const u= 32 *dew_regs) { u32 rdata; int ret; =20 - ret =3D pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY], - &rdata); + ret =3D pwrap_read(wrp, dew_regs[PWRAP_DEW_CIPHER_RDY], &rdata); if (ret) return false; =20 return rdata =3D=3D 1; } =20 + +static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp) +{ + bool ret =3D __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->dew_regs); + + if (!ret) + return ret; + + /* If there's any companion, wait for it to be ready too */ + if (wrp->slave->comp_dew_regs) + ret =3D __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->comp_dew_regs); + + return ret; +} + +static void pwrap_config_cipher(struct pmic_wrapper *wrp, const u32 *dew_r= egs) +{ + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1); + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); + pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); +} + static int pwrap_init_cipher(struct pmic_wrapper *wrp) { int ret; @@ -1623,10 +1659,11 @@ static int pwrap_init_cipher(struct pmic_wrapper *w= rp) } =20 /* Config cipher mode @PMIC */ - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1); - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0); - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1); - pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2); + pwrap_config_cipher(wrp, wrp->slave->dew_regs); + + /* If there is any companion PMIC, configure cipher mode there too */ + if (wrp->slave->comp_type > 0) + pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs); =20 switch (wrp->slave->type) { case PMIC_MT6397: @@ -1688,6 +1725,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) =20 static int pwrap_init_security(struct pmic_wrapper *wrp) { + u32 crc_val; int ret; =20 /* Enable encryption */ @@ -1696,14 +1734,21 @@ static int pwrap_init_security(struct pmic_wrapper = *wrp) return ret; =20 /* Signature checking - using CRC */ - if (pwrap_write(wrp, - wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1)) - return -EFAULT; + ret =3D pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1); + if (ret =3D=3D 0 && wrp->slave->comp_dew_regs) + ret =3D pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_EN], 0x= 1); =20 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN); pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE); - pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL], - PWRAP_SIG_ADR); + + /* CRC value */ + crc_val =3D wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL]; + if (wrp->slave->comp_dew_regs) + crc_val |=3D wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_VAL] << 16; + + pwrap_writel(wrp, crc_val, PWRAP_SIG_ADR); + + /* PMIC Wrapper Arbiter priority */ pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN); =20 --=20 2.35.1 From nobody Sun Sep 22 02:03:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78EFCC4332F for ; Fri, 20 May 2022 12:41:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349530AbiETMlR (ORCPT ); Fri, 20 May 2022 08:41:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349355AbiETMkv (ORCPT ); Fri, 20 May 2022 08:40:51 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19BB2D6B; Fri, 20 May 2022 05:40:47 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 58CB71F462B7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1653050445; bh=BoofczPYFKPT45RV7EHOivl9vCwrE/P2hpyIXUnhdmU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DeFRLtsJyZn3Ad8KZX20pAjUsCmKh9vxSx2ZT/ZIL0jqhSGN30Z7dNAz3Wr1Nlj6l JlFIo6U/0pZhbtC+/gaQ1hkHs/KQkrCH3fQp2iCo5VXrOUh9h+opdaIeYMyLsiPq6H rP4LYXkkNMP69XvMOSQhb7mvCF7xK5d/DyEzMQuzAo7THEKfDtBUhef1iI0AJO9W+6 U2p6Pai+t0v7/ke89D3shTX/V2WYoa1bXS2ZwrNouYCcbp/+94CdmKA1wBkE1zLCWD dUqesVHsqGEy+srs41/dVeRR3fG8ohTCfAs4vgglPU+wPryaOCaXBqIgMQullwnnkO xkIK/pjn39g3Q== From: AngeloGioacchino Del Regno To: lee.jones@linaro.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, zhiyong.tao@mediatek.com, henryc.chen@mediatek.com, johnson.wang@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] dt-bindings: mfd: Add compatible for MT6331 PMIC Date: Fri, 20 May 2022 14:40:36 +0200 Message-Id: <20220520124039.228314-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> References: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a compatible for the MT6331 PMIC MFD device. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- Documentation/devicetree/bindings/mfd/mt6397.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentati= on/devicetree/bindings/mfd/mt6397.txt index 293db2a71ef2..d59063503b0d 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -20,6 +20,7 @@ This document describes the binding for MFD device and it= s sub module. Required properties: compatible: "mediatek,mt6323" for PMIC MT6323 + "mediatek,mt6331" for PMIC MT6331 and MT6332 "mediatek,mt6358" for PMIC MT6358 and MT6366 "mediatek,mt6359" for PMIC MT6359 "mediatek,mt6397" for PMIC MT6397 --=20 2.35.1 From nobody Sun Sep 22 02:03:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 957E5C433EF for ; Fri, 20 May 2022 12:41:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244403AbiETMli (ORCPT ); Fri, 20 May 2022 08:41:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349430AbiETMk6 (ORCPT ); Fri, 20 May 2022 08:40:58 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27E46111A; Fri, 20 May 2022 05:40:51 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 11F6D1F462BB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1653050446; bh=FCqAGYG3PfDArscmLdw2+rXDVhbDbana6dJL9Ndg2RM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cz+WV2Mx1DkB5b0z6JeDfZexqx4csHtIhWbrpkSlQui0wFWR3B7ozftz4BvoJHzDC zR8i0VYE0b1wLWZqbd/xrsa/wSdJI1NU6nR7OalNi/0cgbakLC7aZe8acI0m1Obhwv suRskK41KLULIf12pDDy4vtYRN3Kb+ptfz0HQnePs7uqM01eQT00o12mEMPP9MfNjG fGrZBHY/7Tbqg5RmnZXhTPus7+VOH5vKxZFfal2wgJ3WJP6u2+XDPMCA5hv5TZQf4C XFId2BV06XAVDELwtPKlXpHKEuOhpn2jLni0HKcmBKI6NJ4k66ZGNJIe2X4MI10QfL 7XkF5tuAwsnyw== From: AngeloGioacchino Del Regno To: lee.jones@linaro.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, zhiyong.tao@mediatek.com, henryc.chen@mediatek.com, johnson.wang@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] soc: mediatek: mtk-pmic-wrap: Add support for MT6331 w/ MT6332 companion Date: Fri, 20 May 2022 14:40:37 +0200 Message-Id: <20220520124039.228314-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> References: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the MT6331 PMIC and for its companion MT6332 PMIC. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 47 ++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index 8a4bb6392c3a..f2fe51feb237 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -170,6 +170,40 @@ static const u32 mt6323_regs[] =3D { [PWRAP_DEW_RDDMY_NO] =3D 0x01a4, }; =20 +static const u32 mt6331_regs[] =3D { + [PWRAP_DEW_DIO_EN] =3D 0x018c, + [PWRAP_DEW_READ_TEST] =3D 0x018e, + [PWRAP_DEW_WRITE_TEST] =3D 0x0190, + [PWRAP_DEW_CRC_SWRST] =3D 0x0192, + [PWRAP_DEW_CRC_EN] =3D 0x0194, + [PWRAP_DEW_CRC_VAL] =3D 0x0196, + [PWRAP_DEW_MON_GRP_SEL] =3D 0x0198, + [PWRAP_DEW_CIPHER_KEY_SEL] =3D 0x019a, + [PWRAP_DEW_CIPHER_IV_SEL] =3D 0x019c, + [PWRAP_DEW_CIPHER_EN] =3D 0x019e, + [PWRAP_DEW_CIPHER_RDY] =3D 0x01a0, + [PWRAP_DEW_CIPHER_MODE] =3D 0x01a2, + [PWRAP_DEW_CIPHER_SWRST] =3D 0x01a4, + [PWRAP_DEW_RDDMY_NO] =3D 0x01a6, +}; + +static const u32 mt6332_regs[] =3D { + [PWRAP_DEW_DIO_EN] =3D 0x80f6, + [PWRAP_DEW_READ_TEST] =3D 0x80f8, + [PWRAP_DEW_WRITE_TEST] =3D 0x80fa, + [PWRAP_DEW_CRC_SWRST] =3D 0x80fc, + [PWRAP_DEW_CRC_EN] =3D 0x80fe, + [PWRAP_DEW_CRC_VAL] =3D 0x8100, + [PWRAP_DEW_MON_GRP_SEL] =3D 0x8102, + [PWRAP_DEW_CIPHER_KEY_SEL] =3D 0x8104, + [PWRAP_DEW_CIPHER_IV_SEL] =3D 0x8106, + [PWRAP_DEW_CIPHER_EN] =3D 0x8108, + [PWRAP_DEW_CIPHER_RDY] =3D 0x810a, + [PWRAP_DEW_CIPHER_MODE] =3D 0x810c, + [PWRAP_DEW_CIPHER_SWRST] =3D 0x810e, + [PWRAP_DEW_RDDMY_NO] =3D 0x8110, +}; + static const u32 mt6351_regs[] =3D { [PWRAP_DEW_DIO_EN] =3D 0x02F2, [PWRAP_DEW_READ_TEST] =3D 0x02F4, @@ -1120,6 +1154,8 @@ static int mt8186_regs[] =3D { =20 enum pmic_type { PMIC_MT6323, + PMIC_MT6331, + PMIC_MT6332, PMIC_MT6351, PMIC_MT6357, PMIC_MT6358, @@ -1975,6 +2011,16 @@ static const struct pwrap_slv_type pmic_mt6323 =3D { PWRAP_SLV_CAP_SECURITY, }; =20 +static const struct pwrap_slv_type pmic_mt6331 =3D { + .dew_regs =3D mt6331_regs, + .type =3D PMIC_MT6331, + .comp_dew_regs =3D mt6332_regs, + .comp_type =3D PMIC_MT6332, + .regops =3D &pwrap_regops16, + .caps =3D PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO | + PWRAP_SLV_CAP_SECURITY, +}; + static const struct pwrap_slv_type pmic_mt6351 =3D { .dew_regs =3D mt6351_regs, .type =3D PMIC_MT6351, @@ -2020,6 +2066,7 @@ static const struct pwrap_slv_type pmic_mt6397 =3D { =20 static const struct of_device_id of_slave_match_tbl[] =3D { { .compatible =3D "mediatek,mt6323", .data =3D &pmic_mt6323 }, + { .compatible =3D "mediatek,mt6331", .data =3D &pmic_mt6331 }, { .compatible =3D "mediatek,mt6351", .data =3D &pmic_mt6351 }, { .compatible =3D "mediatek,mt6357", .data =3D &pmic_mt6357 }, { .compatible =3D "mediatek,mt6358", .data =3D &pmic_mt6358 }, --=20 2.35.1 From nobody Sun Sep 22 02:03:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E446CC433F5 for ; Fri, 20 May 2022 12:41:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349339AbiETMld (ORCPT ); Fri, 20 May 2022 08:41:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349437AbiETMk6 (ORCPT ); Fri, 20 May 2022 08:40:58 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 282A6113F; Fri, 20 May 2022 05:40:51 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id BCAE21F462BC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1653050447; bh=L5qU1nQ2bI4UYhJq6gU4Byb4OsjwVhaJ+WdCE8eB27c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TL5S2cNOJL2dDtgaRf7qSDsTCdcJnljZCSi0GZfDAa4ANsrs/v6qYiU4irLpErJ36 CWhdXWKu5nFGXMfH+Z8Hf+0pXiPAIzm/DHHolEJiOOka7fv2e1MfCfSn/77asP04B1 OcF4MPyV8Q6vV3HlGb2apU2S2dLQgN/FZL0dhaOuqeD4rUIU/HRj7kSr5YnHvFM5GS WSZ07rbQlaKdCOa0CIPMZ5Km5ekeHC+hvUjgvJH7VBTRyMqdJ/Pqj9s2qMSnHzi7AT lVvqd80XhD0lpGC20wgUarP7DTeU72pe6j5y/DDKn7AJtgErSldS5yU5/QKexuyofk Vak+JSF/SAQvA== From: AngeloGioacchino Del Regno To: lee.jones@linaro.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, zhiyong.tao@mediatek.com, henryc.chen@mediatek.com, johnson.wang@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] dt-bindings: mediatek: pwrap: Add a compatible for MT6795 Helio X10 Date: Fri, 20 May 2022 14:40:38 +0200 Message-Id: <20220520124039.228314-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> References: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a compatible for the MT6765 Helio X10 SoC's PMIC Wrapper. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring --- Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Doc= umentation/devicetree/bindings/soc/mediatek/pwrap.txt index 0581dbda4828..b53ebebc44bf 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -21,6 +21,7 @@ Required properties in pwrap device node. "mediatek,mt2701-pwrap" for MT2701/7623 SoCs "mediatek,mt6765-pwrap" for MT6765 SoCs "mediatek,mt6779-pwrap" for MT6779 SoCs + "mediatek,mt6795-pwrap" for MT6795 SoCs "mediatek,mt6797-pwrap" for MT6797 SoCs "mediatek,mt6873-pwrap" for MT6873/8192 SoCs "mediatek,mt7622-pwrap" for MT7622 SoCs --=20 2.35.1 From nobody Sun Sep 22 02:03:53 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9313C433EF for ; Fri, 20 May 2022 12:41:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349430AbiETMln (ORCPT ); Fri, 20 May 2022 08:41:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349435AbiETMk6 (ORCPT ); Fri, 20 May 2022 08:40:58 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27E8A111F; Fri, 20 May 2022 05:40:51 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id 768931F462E1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1653050448; bh=+kbdRYsHxe7PHtaPpuxGhKRfW2O1PwuOiUr+rtEeRxY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U1ebcW7jSpjpGZ5vMRp7vlIg70ya+Mv38Al6huikRRQVbjh83elt02K4kiu7z1pZ/ zBKd6qwMu3dKUuS2r3mmRigWmMLiHUFX1WcOr4HtctPMiH+m3NAO8N8v46jW4RqIFz 264LpVSRaxVvyT/040zkeG1pBAP5nWiLeCiinhPKnw9SZ1as7D+X4RpguzBkbKJBy6 n2JQmQKGPU4oTN9/PAxvGB2fNafw86Ew6EnmjpUrWfmE4sw9asH4deouiGyOcxyzrm ylPzU8h75BInT7cVR26hoHdJYVlgphTXZholSbtrgak5LnMipWQYNVRh4h/ASh6Wxt omeN0q2TRVbFA== From: AngeloGioacchino Del Regno To: lee.jones@linaro.org Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, zhiyong.tao@mediatek.com, henryc.chen@mediatek.com, johnson.wang@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] soc: mediatek: pwrap: Add support for MT6795 Helio X10 Date: Fri, 20 May 2022 14:40:39 +0200 Message-Id: <20220520124039.228314-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> References: <20220520124039.228314-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the necessary bits to support the MT6795 Helio X10 smartphone SoC: this is always paired with a MT6331 PMIC, with MT6332 companion. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 131 ++++++++++++++++++++++++++- 1 file changed, 130 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index f2fe51feb237..200c53e2f76a 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -639,6 +639,91 @@ static int mt6779_regs[] =3D { [PWRAP_WACS2_VLDCLR] =3D 0xC28, }; =20 +static int mt6795_regs[] =3D { + [PWRAP_MUX_SEL] =3D 0x0, + [PWRAP_WRAP_EN] =3D 0x4, + [PWRAP_DIO_EN] =3D 0x8, + [PWRAP_SIDLY] =3D 0xc, + [PWRAP_RDDMY] =3D 0x10, + [PWRAP_SI_CK_CON] =3D 0x14, + [PWRAP_CSHEXT_WRITE] =3D 0x18, + [PWRAP_CSHEXT_READ] =3D 0x1c, + [PWRAP_CSLEXT_START] =3D 0x20, + [PWRAP_CSLEXT_END] =3D 0x24, + [PWRAP_STAUPD_PRD] =3D 0x28, + [PWRAP_STAUPD_GRPEN] =3D 0x2c, + [PWRAP_EINT_STA0_ADR] =3D 0x30, + [PWRAP_EINT_STA1_ADR] =3D 0x34, + [PWRAP_STAUPD_MAN_TRIG] =3D 0x40, + [PWRAP_STAUPD_STA] =3D 0x44, + [PWRAP_WRAP_STA] =3D 0x48, + [PWRAP_HARB_INIT] =3D 0x4c, + [PWRAP_HARB_HPRIO] =3D 0x50, + [PWRAP_HIPRIO_ARB_EN] =3D 0x54, + [PWRAP_HARB_STA0] =3D 0x58, + [PWRAP_HARB_STA1] =3D 0x5c, + [PWRAP_MAN_EN] =3D 0x60, + [PWRAP_MAN_CMD] =3D 0x64, + [PWRAP_MAN_RDATA] =3D 0x68, + [PWRAP_MAN_VLDCLR] =3D 0x6c, + [PWRAP_WACS0_EN] =3D 0x70, + [PWRAP_INIT_DONE0] =3D 0x74, + [PWRAP_WACS0_CMD] =3D 0x78, + [PWRAP_WACS0_RDATA] =3D 0x7c, + [PWRAP_WACS0_VLDCLR] =3D 0x80, + [PWRAP_WACS1_EN] =3D 0x84, + [PWRAP_INIT_DONE1] =3D 0x88, + [PWRAP_WACS1_CMD] =3D 0x8c, + [PWRAP_WACS1_RDATA] =3D 0x90, + [PWRAP_WACS1_VLDCLR] =3D 0x94, + [PWRAP_WACS2_EN] =3D 0x98, + [PWRAP_INIT_DONE2] =3D 0x9c, + [PWRAP_WACS2_CMD] =3D 0xa0, + [PWRAP_WACS2_RDATA] =3D 0xa4, + [PWRAP_WACS2_VLDCLR] =3D 0xa8, + [PWRAP_INT_EN] =3D 0xac, + [PWRAP_INT_FLG_RAW] =3D 0xb0, + [PWRAP_INT_FLG] =3D 0xb4, + [PWRAP_INT_CLR] =3D 0xb8, + [PWRAP_SIG_ADR] =3D 0xbc, + [PWRAP_SIG_MODE] =3D 0xc0, + [PWRAP_SIG_VALUE] =3D 0xc4, + [PWRAP_SIG_ERRVAL] =3D 0xc8, + [PWRAP_CRC_EN] =3D 0xcc, + [PWRAP_TIMER_EN] =3D 0xd0, + [PWRAP_TIMER_STA] =3D 0xd4, + [PWRAP_WDT_UNIT] =3D 0xd8, + [PWRAP_WDT_SRC_EN] =3D 0xdc, + [PWRAP_WDT_FLG] =3D 0xe0, + [PWRAP_DEBUG_INT_SEL] =3D 0xe4, + [PWRAP_DVFS_ADR0] =3D 0xe8, + [PWRAP_DVFS_WDATA0] =3D 0xec, + [PWRAP_DVFS_ADR1] =3D 0xf0, + [PWRAP_DVFS_WDATA1] =3D 0xf4, + [PWRAP_DVFS_ADR2] =3D 0xf8, + [PWRAP_DVFS_WDATA2] =3D 0xfc, + [PWRAP_DVFS_ADR3] =3D 0x100, + [PWRAP_DVFS_WDATA3] =3D 0x104, + [PWRAP_DVFS_ADR4] =3D 0x108, + [PWRAP_DVFS_WDATA4] =3D 0x10c, + [PWRAP_DVFS_ADR5] =3D 0x110, + [PWRAP_DVFS_WDATA5] =3D 0x114, + [PWRAP_DVFS_ADR6] =3D 0x118, + [PWRAP_DVFS_WDATA6] =3D 0x11c, + [PWRAP_DVFS_ADR7] =3D 0x120, + [PWRAP_DVFS_WDATA7] =3D 0x124, + [PWRAP_SPMINF_STA] =3D 0x128, + [PWRAP_CIPHER_KEY_SEL] =3D 0x12c, + [PWRAP_CIPHER_IV_SEL] =3D 0x130, + [PWRAP_CIPHER_EN] =3D 0x134, + [PWRAP_CIPHER_RDY] =3D 0x138, + [PWRAP_CIPHER_MODE] =3D 0x13c, + [PWRAP_CIPHER_SWRST] =3D 0x140, + [PWRAP_DCM_EN] =3D 0x144, + [PWRAP_DCM_DBC_PRD] =3D 0x148, + [PWRAP_EXT_CK] =3D 0x14c, +}; + static int mt6797_regs[] =3D { [PWRAP_MUX_SEL] =3D 0x0, [PWRAP_WRAP_EN] =3D 0x4, @@ -1168,6 +1253,7 @@ enum pwrap_type { PWRAP_MT2701, PWRAP_MT6765, PWRAP_MT6779, + PWRAP_MT6795, PWRAP_MT6797, PWRAP_MT6873, PWRAP_MT7622, @@ -1585,6 +1671,20 @@ static void pwrap_init_chip_select_ext(struct pmic_w= rapper *wrp, u8 hext_write, static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) { switch (wrp->master->type) { + case PWRAP_MT6795: + if (wrp->slave->type =3D=3D PMIC_MT6331) { + const u32 *dew_regs =3D wrp->slave->dew_regs; + + pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + + if (wrp->slave->comp_type =3D=3D PMIC_MT6332) { + dew_regs =3D wrp->slave->comp_dew_regs; + pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8); + } + } + pwrap_writel(wrp, 0x88, PWRAP_RDDMY); + pwrap_init_chip_select_ext(wrp, 15, 15, 15, 15); + break; case PWRAP_MT8173: pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); break; @@ -1679,6 +1779,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) case PWRAP_MT2701: case PWRAP_MT6765: case PWRAP_MT6779: + case PWRAP_MT6795: case PWRAP_MT6797: case PWRAP_MT8173: case PWRAP_MT8186: @@ -1848,6 +1949,19 @@ static int pwrap_mt2701_init_soc_specific(struct pmi= c_wrapper *wrp) return 0; } =20 +static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp) +{ + pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN); + + if (wrp->slave->type =3D=3D PMIC_MT6331) + pwrap_writel(wrp, 0x1b4, PWRAP_EINT_STA0_ADR); + + if (wrp->slave->comp_type =3D=3D PMIC_MT6332) + pwrap_writel(wrp, 0x8112, PWRAP_EINT_STA1_ADR); + + return 0; +} + static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp) { pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD); @@ -1883,7 +1997,8 @@ static int pwrap_init(struct pmic_wrapper *wrp) if (wrp->rstc_bridge) reset_control_reset(wrp->rstc_bridge); =20 - if (wrp->master->type =3D=3D PWRAP_MT8173) { + if (wrp->master->type =3D=3D PWRAP_MT8173 || + wrp->master->type =3D=3D PWRAP_MT6795) { /* Enable DCM */ pwrap_writel(wrp, 3, PWRAP_DCM_EN); pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD); @@ -2119,6 +2234,19 @@ static const struct pmic_wrapper_type pwrap_mt6779 = =3D { .init_soc_specific =3D NULL, }; =20 +static const struct pmic_wrapper_type pwrap_mt6795 =3D { + .regs =3D mt6795_regs, + .type =3D PWRAP_MT6795, + .arb_en_all =3D 0x3f, + .int_en_all =3D ~(u32)(BIT(31) | BIT(2) | BIT(1)), + .int1_en_all =3D 0, + .spi_w =3D PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src =3D PWRAP_WDT_SRC_MASK_NO_STAUPD, + .caps =3D PWRAP_CAP_RESET | PWRAP_CAP_DCM, + .init_reg_clock =3D pwrap_common_init_reg_clock, + .init_soc_specific =3D pwrap_mt6795_init_soc_specific, +}; + static const struct pmic_wrapper_type pwrap_mt6797 =3D { .regs =3D mt6797_regs, .type =3D PWRAP_MT6797, @@ -2239,6 +2367,7 @@ static const struct of_device_id of_pwrap_match_tbl[]= =3D { { .compatible =3D "mediatek,mt2701-pwrap", .data =3D &pwrap_mt2701 }, { .compatible =3D "mediatek,mt6765-pwrap", .data =3D &pwrap_mt6765 }, { .compatible =3D "mediatek,mt6779-pwrap", .data =3D &pwrap_mt6779 }, + { .compatible =3D "mediatek,mt6795-pwrap", .data =3D &pwrap_mt6795 }, { .compatible =3D "mediatek,mt6797-pwrap", .data =3D &pwrap_mt6797 }, { .compatible =3D "mediatek,mt6873-pwrap", .data =3D &pwrap_mt6873 }, { .compatible =3D "mediatek,mt7622-pwrap", .data =3D &pwrap_mt7622 }, --=20 2.35.1