From nobody Sun Sep 22 01:33:45 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BCFEC433F5 for ; Fri, 20 May 2022 09:44:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347898AbiETJoF (ORCPT ); Fri, 20 May 2022 05:44:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347761AbiETJn4 (ORCPT ); Fri, 20 May 2022 05:43:56 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC8791498DC for ; Fri, 20 May 2022 02:43:55 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id d22so6914955plr.9 for ; Fri, 20 May 2022 02:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N537kmXnIFF/B5MPYA58NfVjnsyjLkZ7UggoyVApuvw=; b=KC3c/8wyL3TWVMhL+5tSUJIk8jM4TdkimQNEt+YUcV/P3D4O9WrDmYeovQCEcsR1r5 XWSNKSVZ0WFawguQMabuNh3CoUu73KSTIFVsEoNKpo4D3eBbpFm0c9d9ubGLXmEXW5GW lQhnaIvUaUXAm8W1h0p1CQJLswQ7ZYLzUoC5w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N537kmXnIFF/B5MPYA58NfVjnsyjLkZ7UggoyVApuvw=; b=7wmaNE3brVGpz7BayH9tMxKeBmkDXOYi3k65m5V32SAumvxkEO2KIqqpqRzGwRzHaS CTFlVWEh5SJyPp/Gcv/Tn7FsHLneQmxgrQBwyNVOpuAcc4qqYE6yaHNH/W7Fsx2stQn2 xiFKaF0jxLyYmrVvvOZUKksLepqpcKpERCPx1ZXFuA9FSyhw4rtMoyIRl+wZVcWqa2on ryeI5r0286AC52ofp9ZF+yFb+sYLPlNFFYpeXlko9iD93AEoI4I9+0Bu16N1Wd3bO8Sj VN0MKEkTVKELFsrdzf92TXmf9Yy22bwlZ5hBaY0oL8Uu+HnlJpmXSgFhpqbppv1dMDQu dVpg== X-Gm-Message-State: AOAM530Y/0iE//Aeq074bdIbTGAzGruwp4cm9FukWV79CAmqpIZJuG7M SB3ueYdhoP9yU0j/4hV4OjUqVA== X-Google-Smtp-Source: ABdhPJx3Qh3cpJC+oik5Y71LHH8R8PjCzSbTcq79RW9UtXYQoOStcvHrjZaDjBr8UJjUlGm3KiM5lg== X-Received: by 2002:a17:90b:1e04:b0:1dc:9252:efbc with SMTP id pg4-20020a17090b1e0400b001dc9252efbcmr10148535pjb.39.1653039835451; Fri, 20 May 2022 02:43:55 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:ec49:9912:894:222d]) by smtp.gmail.com with ESMTPSA id 23-20020aa79217000000b0050dc76281bfsm1290597pfo.153.2022.05.20.02.43.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 02:43:55 -0700 (PDT) From: Chen-Yu Tsai To: Michael Turquette , Stephen Boyd , Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Chun-Jie Chen , Miles Chen , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] arm64: dts: mt8183: Fix Mali GPU clock Date: Fri, 20 May 2022 17:43:20 +0800 Message-Id: <20220520094323.754971-2-wenst@chromium.org> X-Mailer: git-send-email 2.36.1.124.g0e6072fb45-goog In-Reply-To: <20220520094323.754971-1-wenst@chromium.org> References: <20220520094323.754971-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The actual clock feeding into the Mali GPU on the MT8183 is from the clock gate in the MFGCFG block, not CLK_TOP_MFGPLL_CK from the TOPCKGEN block, which itself is simply a pass-through placeholder for the MFGPLL in the APMIXEDSYS block. Fix the hardware description with the correct clock reference. Fixes: a8168cebf1bc ("arm64: dts: mt8183: Add node for the Mali GPU") Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index 01e650251928..6ced76a60aab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1368,7 +1368,7 @@ gpu: gpu@13040000 { ; interrupt-names =3D "job", "mmu", "gpu"; =20 - clocks =3D <&topckgen CLK_TOP_MFGPLL_CK>; + clocks =3D <&mfgcfg CLK_MFG_BG3D>; =20 power-domains =3D <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, --=20 2.36.1.124.g0e6072fb45-goog From nobody Sun Sep 22 01:33:45 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18AFCC433F5 for ; Fri, 20 May 2022 09:44:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347904AbiETJoH (ORCPT ); Fri, 20 May 2022 05:44:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346078AbiETJn7 (ORCPT ); Fri, 20 May 2022 05:43:59 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC8B5149AAF for ; Fri, 20 May 2022 02:43:58 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id q18so6919406pln.12 for ; Fri, 20 May 2022 02:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b4toybDv1M53GirTn8tpXa0Kt2GdamhkRh4OIAgDtc4=; b=WWvNjRlc9R3ylkT71F/0tYY4edxwlaAQp+Dvd7vVK/bnjQvRih4OUAVVzo1biCrAmn YkhIzbWoHtuygjdR112SzgAHPZOxtb/tDDeieVB2abJW58imdO1Eo9vL3NtIFG2nqgbw b1p6Sn1k7r4GowNho+ENI+EsKo91JVoN3LK/E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b4toybDv1M53GirTn8tpXa0Kt2GdamhkRh4OIAgDtc4=; b=q/L4jCHh2VwnS9bREzR/qE9nft9ahnA+we/tRKaFw3ZnCQUPYIhnZdgp5dYPq+FSMC qyHWky/qkdweZL5tPZ5Tuj0FSCqrGRjUpOtDUWrYgOBViEcHA+vyaAri0TMkJpPLmlEN GL1nr6B/DlBbGGKbT5TB42QigYoyoA0iOTwY1/ro1BfC0ZRGjbpL92aUZzIJHBC0BdDL olUYxserS/9cmhcleCoFoZ2gjMPFBxNNcXcYtwBUfUShXZOFNhq3sBbdwbxnMCevdYU8 lhPcvGcbA9EVQcG0q4XrqYC5RdJSEZwiq8XNIyo+YO5yAkz5AHBPBqA8TBHrk119KpsV spRg== X-Gm-Message-State: AOAM530eFQy2T9NxBppWan0cR5rzrTjnxQfZchjhOqFzLV5616yvzl6H oK5w/5pVTingaUMdkZpYUxzApg== X-Google-Smtp-Source: ABdhPJwnbKiL/9EFkMezmfR/RGWpPtvvom3H3Yyp6HcfhsLZSqErmLrIH1CjIf5RMqWmmYanZhLuQA== X-Received: by 2002:a17:903:22c7:b0:161:cf2e:2ce2 with SMTP id y7-20020a17090322c700b00161cf2e2ce2mr8793814plg.59.1653039838197; Fri, 20 May 2022 02:43:58 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:ec49:9912:894:222d]) by smtp.gmail.com with ESMTPSA id 23-20020aa79217000000b0050dc76281bfsm1290597pfo.153.2022.05.20.02.43.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 02:43:57 -0700 (PDT) From: Chen-Yu Tsai To: Michael Turquette , Stephen Boyd , Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Chun-Jie Chen , Miles Chen , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent Date: Fri, 20 May 2022 17:43:21 +0800 Message-Id: <20220520094323.754971-3-wenst@chromium.org> X-Mailer: git-send-email 2.36.1.124.g0e6072fb45-goog In-Reply-To: <20220520094323.754971-1-wenst@chromium.org> References: <20220520094323.754971-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The only clock in the MT8183 MFGCFG block feeds the GPU. Propagate its rate change requests to its parent, so that DVFS for the GPU can work properly. Fixes: acddfc2c261b ("clk: mediatek: Add MT8183 clock support") Signed-off-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8183-mfgcfg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediate= k/clk-mt8183-mfgcfg.c index d774edaf760b..230299728859 100644 --- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c @@ -18,9 +18,9 @@ static const struct mtk_gate_regs mfg_cg_regs =3D { .sta_ofs =3D 0x0, }; =20 -#define GATE_MFG(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \ - &mtk_clk_gate_ops_setclr) +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_SET_RATE_PARENT) =20 static const struct mtk_gate mfg_clks[] =3D { GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0) --=20 2.36.1.124.g0e6072fb45-goog From nobody Sun Sep 22 01:33:45 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1B41C433F5 for ; Fri, 20 May 2022 09:44:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347915AbiETJoT (ORCPT ); Fri, 20 May 2022 05:44:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347771AbiETJoD (ORCPT ); Fri, 20 May 2022 05:44:03 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 838C914ACBA for ; Fri, 20 May 2022 02:44:01 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id bo5so7333317pfb.4 for ; Fri, 20 May 2022 02:44:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wYj0gPoFTJBwWJLt1P9KNSn0ODKjU0wkvs8hBSjSO3U=; b=ld8ZB0W0CyuE942AiXu7m9Pc6o1IzPm43tHOkNtsI9ja3+ZXuaz5Fsly3T/TPHc0qC yK669VzcVQuMW9FLnv0lGgD5gHPf1ru3oq88/XJN0uNcvMK8LxHYFhB6djP6naTFGtHJ JGWj6AJghQtC93LhJLnbHADNmKxzqBYvpUn18= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wYj0gPoFTJBwWJLt1P9KNSn0ODKjU0wkvs8hBSjSO3U=; b=o0JlTW80Ipq6IUHXlkW2khFk6EtTgyTOgOnQ9zvG1BuD8kYyjAh/1n81t+rPR6YG9D udhIjxkLNRURZma4m4ZFMjzSEVkXdnWJi4pRDmAfGxMTx/RqS+abeu0OKG1OPEo+JtAq 6cf5dr+O6sqKQo0DltYKvNDwfeP+91LZQjgCvcrwzcrJHZRas13rW5d3QTvwK+PKMNI6 GlmE24fwEHRBihYZuWHAY31xvsK8rdj1VtcZy3PuObOir3RhUv1gO3SAY4UMjLFNmpqU Tybp0lowM5+ATBD4ULwMg57kqDhYrtk+bfsII+K15tCWEQ8vBNHLpUos9zxioj/sYi9G o1rg== X-Gm-Message-State: AOAM532mhZE5RoRgYqg98HSfIa7v5FMikST8X/nIrUMuTJGZtoEXlp6Y 923hcdQeReCnyiLB7zOYm1kNGw== X-Google-Smtp-Source: ABdhPJziucUgkorNxj9E4BMmeKGpBafnohBlJChKVMYUEKtYijrw73Ok7dlvQG3idGaek2YoMaMHYw== X-Received: by 2002:a63:e655:0:b0:3c2:84a2:2ea0 with SMTP id p21-20020a63e655000000b003c284a22ea0mr7837735pgj.86.1653039841013; Fri, 20 May 2022 02:44:01 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:ec49:9912:894:222d]) by smtp.gmail.com with ESMTPSA id 23-20020aa79217000000b0050dc76281bfsm1290597pfo.153.2022.05.20.02.43.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 02:44:00 -0700 (PDT) From: Chen-Yu Tsai To: Michael Turquette , Stephen Boyd , Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Chun-Jie Chen , Miles Chen , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] clk: mediatek: mux: add clk notifier functions Date: Fri, 20 May 2022 17:43:22 +0800 Message-Id: <20220520094323.754971-4-wenst@chromium.org> X-Mailer: git-send-email 2.36.1.124.g0e6072fb45-goog In-Reply-To: <20220520094323.754971-1-wenst@chromium.org> References: <20220520094323.754971-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With device frequency scaling, the mux clock that (indirectly) feeds the device selects between a dedicated PLL, and some other stable clocks. When a clk rate change is requested, the (normally) upstream PLL is reconfigured. It's possible for the clock output of the PLL to become unstable during this process. To avoid causing the device to glitch, the mux should temporarily be switched over to another "stable" clock during the PLL rate change. This is done with clk notifiers. This patch adds common functions for notifiers to temporarily and transparently reparent mux clocks. This was loosely based on commit 8adfb08605a9 ("clk: sunxi-ng: mux: Add clk notifier functions"). Signed-off-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mux.c | 42 ++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-mux.h | 15 ++++++++++++ 2 files changed, 57 insertions(+) diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index cd5f9fd8cb98..f84a5a753c09 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -4,6 +4,7 @@ * Author: Owen Chen */ =20 +#include #include #include #include @@ -259,4 +260,45 @@ void mtk_clk_unregister_muxes(const struct mtk_mux *mu= xes, int num, } EXPORT_SYMBOL_GPL(mtk_clk_unregister_muxes); =20 +/* + * This clock notifier is called when the frequency of the of the parent + * PLL clock is to be changed. The idea is to switch the parent to a + * stable clock, such as the main oscillator, while the PLL frequency + * stabilizes. + */ +static int mtk_clk_mux_notifier_cb(struct notifier_block *nb, + unsigned long event, void *_data) +{ + struct clk_notifier_data *data =3D _data; + struct mtk_mux_nb *mux_nb =3D to_mtk_mux_nb(nb); + const struct mtk_mux *mux =3D mux_nb->mux; + struct clk_hw *hw; + int ret =3D 0; + + hw =3D __clk_get_hw(data->clk); + + switch (event) { + case PRE_RATE_CHANGE: + mux_nb->original_index =3D mux->ops->get_parent(hw); + ret =3D mux->ops->set_parent(hw, mux_nb->bypass_index); + break; + + case POST_RATE_CHANGE: + case ABORT_RATE_CHANGE: + ret =3D mux->ops->set_parent(hw, mux_nb->original_index); + break; + } + + return notifier_from_errno(ret); +} + +int devm_mtk_clk_mux_notifier_register(struct device *dev, struct clk *clk, + struct mtk_mux_nb *mux_nb) +{ + mux_nb->nb.notifier_call =3D mtk_clk_mux_notifier_cb; + + return devm_clk_notifier_register(dev, clk, &mux_nb->nb); +} +EXPORT_SYMBOL_GPL(devm_mtk_clk_mux_notifier_register); + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h index 6539c58f5d7d..506e91125a3d 100644 --- a/drivers/clk/mediatek/clk-mux.h +++ b/drivers/clk/mediatek/clk-mux.h @@ -7,12 +7,14 @@ #ifndef __DRV_CLK_MTK_MUX_H #define __DRV_CLK_MTK_MUX_H =20 +#include #include #include =20 struct clk; struct clk_hw_onecell_data; struct clk_ops; +struct device; struct device_node; =20 struct mtk_mux { @@ -89,4 +91,17 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes, void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num, struct clk_hw_onecell_data *clk_data); =20 +struct mtk_mux_nb { + struct notifier_block nb; + const struct mtk_mux *mux; + + u8 bypass_index; /* Which parent to temporarily use */ + u8 original_index; /* Set by notifier callback */ +}; + +#define to_mtk_mux_nb(_nb) container_of(_nb, struct mtk_mux_nb, nb) + +int devm_mtk_clk_mux_notifier_register(struct device *dev, struct clk *clk, + struct mtk_mux_nb *mux_nb); + #endif /* __DRV_CLK_MTK_MUX_H */ --=20 2.36.1.124.g0e6072fb45-goog From nobody Sun Sep 22 01:33:45 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6182DC433EF for ; Fri, 20 May 2022 09:44:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235921AbiETJoa (ORCPT ); Fri, 20 May 2022 05:44:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36164 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347911AbiETJoN (ORCPT ); Fri, 20 May 2022 05:44:13 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3ABA814ACB7 for ; Fri, 20 May 2022 02:44:04 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id v11so7323167pff.6 for ; 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Fri, 20 May 2022 02:44:03 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:ec49:9912:894:222d]) by smtp.gmail.com with ESMTPSA id 23-20020aa79217000000b0050dc76281bfsm1290597pfo.153.2022.05.20.02.44.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 02:44:03 -0700 (PDT) From: Chen-Yu Tsai To: Michael Turquette , Stephen Boyd , Matthias Brugger Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Chun-Jie Chen , Miles Chen , AngeloGioacchino Del Regno , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] clk: mediatek: mt8183: Add clk mux notifier for MFG mux Date: Fri, 20 May 2022 17:43:23 +0800 Message-Id: <20220520094323.754971-5-wenst@chromium.org> X-Mailer: git-send-email 2.36.1.124.g0e6072fb45-goog In-Reply-To: <20220520094323.754971-1-wenst@chromium.org> References: <20220520094323.754971-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When the MFG PLL clock, which is upstream of the MFG clock, is changed, the downstream clock and consumers need to be switched away from the PLL over to a stable clock to avoid glitches. This is done through the use of the newly added clk mux notifier. The notifier is set on the mux itself instead of the upstream PLL, but in practice this works, as the rate change notifitcations are propogated throughout the sub-tree hanging off the PLL. Just before rate changes, the MFG mux is temporarily and transparently switched to the 26 MHz main crystal. After the rate change, the mux is switched back. Signed-off-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8183.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 8a755fadebb5..afef3738396e 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1192,6 +1192,8 @@ static int clk_mt8183_top_probe(struct platform_devic= e *pdev) { void __iomem *base; struct device_node *node =3D pdev->dev.of_node; + struct mtk_mux_nb *mfg_mux_nb; + int i, ret; =20 base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) @@ -1217,6 +1219,25 @@ static int clk_mt8183_top_probe(struct platform_devi= ce *pdev) mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data); =20 + /* Register mux notifier for MFG mux */ + mfg_mux_nb =3D devm_kzalloc(&pdev->dev, sizeof(*mfg_mux_nb), GFP_KERNEL); + if (!mfg_mux_nb) + return -ENOMEM; + + for (i =3D 0; i < ARRAY_SIZE(top_muxes); i++) + if (top_muxes[i].id =3D=3D CLK_TOP_MUX_MFG) + break; + if (i =3D=3D ARRAY_SIZE(top_muxes)) + return -EINVAL; + + mfg_mux_nb->mux =3D &top_muxes[i]; + mfg_mux_nb->bypass_index =3D 0; // Bypass to 26M crystal + ret =3D devm_mtk_clk_mux_notifier_register(&pdev->dev, + top_clk_data->hws[CLK_TOP_MUX_MFG]->clk, + mfg_mux_nb); + if (ret) + return ret; + return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); } --=20 2.36.1.124.g0e6072fb45-goog