From nobody Sun Sep 22 04:37:41 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26F0DC433FE for ; Fri, 20 May 2022 08:31:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347150AbiETIbA (ORCPT ); Fri, 20 May 2022 04:31:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347154AbiETIao (ORCPT ); Fri, 20 May 2022 04:30:44 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A887158940; Fri, 20 May 2022 01:30:12 -0700 (PDT) X-UUID: 964866f1dd8e4b9e9395ce76b12d73ca-20220520 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:6bafdaf3-8e8d-45b6-b40e-7d85d9a05af8,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:7076ede2-edbf-4bd4-8a34-dfc5f7bb086d,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 964866f1dd8e4b9e9395ce76b12d73ca-20220520 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1466797144; Fri, 20 May 2022 16:30:09 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 20 May 2022 16:30:08 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 20 May 2022 16:30:08 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , "Krzysztof Kozlowski" , Hans Verkuil CC: Chun-Kuang Hu , Rob Landley , Laurent Pinchart , , , , , , Alexandre Courbot , , , , , Benjamin Gaignard , AngeloGioacchino Del Regno , daoyuan huang , Ping-Hsun Wu , , , , , , , , , Subject: [PATCH v16 3/4] dts: arm64: mt8183: add Mediatek MDP3 nodes Date: Fri, 20 May 2022 16:30:05 +0800 Message-ID: <20220520083006.27789-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220520083006.27789-1-moudy.ho@mediatek.com> References: <20220520083006.27789-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device nodes for Media Data Path 3 (MDP3) modules. Signed-off-by: Moudy Ho --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79 +++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts= /mediatek/mt8183.dtsi index fc6ac2a46324..5b6c18f51787 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1389,6 +1389,50 @@ mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0 0x1000>; }; =20 + mdp3_rdma0: mdp3-rdma0@14001000 { + compatible =3D "mediatek,mt8183-mdp3-rdma"; + reg =3D <0 0x14001000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x1000 0x1000>; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>; + iommus =3D <&iommu M4U_PORT_MDP_RDMA0>; + mboxes =3D <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; + }; + + mdp3_rsz0: mdp3-rsz0@14003000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + clocks =3D <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp3_rsz1: mdp3-rsz1@14004000 { + compatible =3D "mediatek,mt8183-mdp3-rsz"; + reg =3D <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x4000 0x1000>; + clocks =3D <&mmsys CLK_MM_MDP_RSZ1>; + }; + + mdp3_wrot0: mdp3-wrot0@14005000 { + compatible =3D "mediatek,mt8183-mdp3-wrot"; + reg =3D <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_MDP_WROT0>; + iommus =3D <&iommu M4U_PORT_MDP_WROT0>; + }; + + mdp3_wdma: mdp3-wdma@14006000 { + compatible =3D "mediatek,mt8183-mdp3-wdma"; + reg =3D <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_MDP_WDMA0>; + iommus =3D <&iommu M4U_PORT_MDP_WDMA0>; + }; + ovl0: ovl@14008000 { compatible =3D "mediatek,mt8183-disp-ovl"; reg =3D <0 0x14008000 0 0x1000>; @@ -1513,7 +1557,33 @@ interrupts =3D ; power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; mediatek,gce-events =3D , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0x6000 0x1000>; }; =20 @@ -1538,6 +1608,13 @@ power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; }; =20 + mdp3_ccorr: mdp3-ccorr@1401c000 { + compatible =3D "mediatek,mt8183-mdp3-ccorr"; + reg =3D <0 0x1401c000 0 0x1000>; + mediatek,gce-client-reg =3D <&gce SUBSYS_1401XXXX 0xc000 0x1000>; + clocks =3D <&mmsys CLK_MM_MDP_CCORR>; + }; + imgsys: syscon@15020000 { compatible =3D "mediatek,mt8183-imgsys", "syscon"; reg =3D <0 0x15020000 0 0x1000>; --=20 2.18.0