From nobody Sun Sep 22 03:31:58 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E72D5C433F5 for ; Thu, 19 May 2022 14:24:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239536AbiESOYn (ORCPT ); Thu, 19 May 2022 10:24:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239651AbiESOYk (ORCPT ); Thu, 19 May 2022 10:24:40 -0400 Received: from mail-qt1-x831.google.com (mail-qt1-x831.google.com [IPv6:2607:f8b0:4864:20::831]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28E70CC152; Thu, 19 May 2022 07:24:35 -0700 (PDT) Received: by mail-qt1-x831.google.com with SMTP id u35so4870027qtc.13; Thu, 19 May 2022 07:24:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v13RFBMs++l4Uo/HJueyt8iKmNbI7+Etkp5S+ELIDJg=; b=DtvsPXCb2jRPYUq1EwPsx+PLx1MKG+CkFmWqDHiaFSbWu5xu3Rg9xdPZG6WWctZr9c m0k3eTABFHjj3fjmEUAxk21Ahh2ssebdFYfqPuy2VNN3PRHMa9mLAq7Vhw96uh4aceX8 uqa68JDMUPfiW1+JX12AblHLcmHmaumHxWuGbsk13TNrb0fpv7IZtsdZj4dpoE9x2hBL r3zOGZ96JYesog4W7C+AwU1J+EgpTeA4PA5H04rNmYLJY9GsNWByUq6kpNLH2eMB/K7p UJx0aAQo4sJtwD+3uweQdNlnZ7OvtHJ7R+MKWwelQzEOamf0GUEJ/bix6gsmNFneWM1o IJrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v13RFBMs++l4Uo/HJueyt8iKmNbI7+Etkp5S+ELIDJg=; b=HUMbkFL5SbkKgB5lG0Qa2vQg1CKqCKTkbOePrm3Fxgh63D3M4skUHxR+Cpy8b38vIL 2Z4AlfqfdoL/a24shMvvJ69b9uf5EO30QicCL7BLziwMPX3VUCYCeTVpL9MSSK3Uy0nb x7Hzk6H9l8izhyJrZ6Hw1iEHil26hO06YeYWa1B5c3Bd5/tYayQyFYRtfvoK9T04B/4F /Eah6kK29knn+hroanZe1FbGsK5cvumU9itQidiuumOzg6w2QkXPup5MewP27irg+6fW 7QaNUdkXFb0F/8DbxNYeed1OQQ/6yEX1WoL0aPJo/3+VTDXXXPPEz5hTsjDKXnejE4hI Qs9Q== X-Gm-Message-State: AOAM532XTRG3MUMiH5PDbrjOihbwMH9bwmjJO5sYssu+qe6+A72/Z60m FnVzgRyNco4miahUU9Bp69I= X-Google-Smtp-Source: ABdhPJzRX0EPJPrfCEYKugxC43dOQ60RDegHvoA4xxRpq0pX8amtUO0QHqU7wXtZgU15AoeRq8CHhA== X-Received: by 2002:a05:622a:1906:b0:2f3:bbbc:f7b9 with SMTP id w6-20020a05622a190600b002f3bbbcf7b9mr4004178qtc.632.1652970274100; Thu, 19 May 2022 07:24:34 -0700 (PDT) Received: from localhost.localdomain ([217.138.206.82]) by smtp.gmail.com with ESMTPSA id c15-20020ac85a8f000000b002f39b99f697sm1539342qtc.49.2022.05.19.07.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 May 2022 07:24:33 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Michael Turquette , Stephen Boyd , Matthias Brugger , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , AngeloGioacchino Del Regno , Tinghan Shen , Chun-Jie Chen , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Chen-Yu Tsai , Bartosz Golaszewski , Yassine Oudjana , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Rob Herring Subject: [PATCH v2 3/4] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Date: Thu, 19 May 2022 18:22:10 +0400 Message-Id: <20220519142211.458336-4-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220519142211.458336-1-y.oudjana@protonmail.com> References: <20220519142211.458336-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add compatible strings for MT6735 apmixedsys, topckgen, infracfg and pericfg. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring --- .../bindings/arm/mediatek/mediatek,infracfg.yaml | 8 +++++--- .../bindings/arm/mediatek/mediatek,pericfg.yaml | 1 + .../devicetree/bindings/clock/mediatek,apmixedsys.yaml | 4 +++- .../devicetree/bindings/clock/mediatek,topckgen.yaml | 4 +++- 4 files changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infrac= fg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.= yaml index 8681b785ed6d..aa1bb13e0d67 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml @@ -11,9 +11,10 @@ maintainers: =20 description: The Mediatek infracfg controller provides various clocks and reset outpu= ts - to the system. The clock values can be found in , - and reset values in and - . + to the system. The clock values can be found in + and , and reset values in + , and + . =20 properties: compatible: @@ -22,6 +23,7 @@ properties: - enum: - mediatek,mt2701-infracfg - mediatek,mt2712-infracfg + - mediatek,mt6735-infracfg - mediatek,mt6765-infracfg - mediatek,mt6779-infracfg_ao - mediatek,mt6797-infracfg diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericf= g.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.ya= ml index 611f666f359d..94e5e003e60e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -20,6 +20,7 @@ properties: - enum: - mediatek,mt2701-pericfg - mediatek,mt2712-pericfg + - mediatek,mt6735-pericfg - mediatek,mt6765-pericfg - mediatek,mt7622-pericfg - mediatek,mt7629-pericfg diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.ya= ml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml index 770546195fb5..3a186621e7a9 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml @@ -12,7 +12,8 @@ maintainers: =20 description: The Mediatek apmixedsys controller provides PLLs to the system. - The clock values can be found in . + The clock values can be found in + and . =20 properties: compatible: @@ -32,6 +33,7 @@ properties: - enum: - mediatek,mt2701-apmixedsys - mediatek,mt2712-apmixedsys + - mediatek,mt6735-apmixedsys - mediatek,mt6765-apmixedsys - mediatek,mt6779-apmixedsys - mediatek,mt7629-apmixedsys diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml= b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml index 5b8b37a2e594..920bf0828d58 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml @@ -12,7 +12,8 @@ maintainers: =20 description: The Mediatek topckgen controller provides various clocks to the system. - The clock values can be found in . + The clock values can be found in and + . =20 properties: compatible: @@ -31,6 +32,7 @@ properties: - enum: - mediatek,mt2701-topckgen - mediatek,mt2712-topckgen + - mediatek,mt6735-topckgen - mediatek,mt6765-topckgen - mediatek,mt6779-topckgen - mediatek,mt7629-topckgen --=20 2.36.1