From nobody Sun Sep 22 01:29:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5248C433F5 for ; Thu, 19 May 2022 14:24:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239628AbiESOYP (ORCPT ); Thu, 19 May 2022 10:24:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238087AbiESOYM (ORCPT ); Thu, 19 May 2022 10:24:12 -0400 Received: from mail-qk1-x72e.google.com (mail-qk1-x72e.google.com [IPv6:2607:f8b0:4864:20::72e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D285773795; Thu, 19 May 2022 07:24:09 -0700 (PDT) Received: by mail-qk1-x72e.google.com with SMTP id j6so4818434qkp.9; Thu, 19 May 2022 07:24:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AoC9q7cvfnd7EIJadA1kEw/o8A7aPnNrZiatZkduF8M=; b=W2c8prILdEbbbVv9PLjE1Lr42AbeD7zvhQVZfzqttwrWO4tIXnFiddS4Z1SUC8utkf 3aowIUXgl22vr8eOMVw642BGCDDS+OzljTFEXw7gigyIe1DLTNXxMxqz1cUuVQm4Uuij WYlHb4R9SyjqddO9oBpiNP7S46UmiEyXVBCH4BBVx+m7bhLRzONoLcB+pEBMLKa/zLHQ NfvdZcRsYXRb4VJqAx5Xn+A9phoLzkcaBT2ZnvBwjYHFO1VMj0KJj2bL0BQIDfqW/w+9 Y/qA5AcIVvtRAJWKXyy8CHOY5SrNnJoW//tqYL3zWzCcSt5592yeIxzQBBqdrGnAS+R2 n2/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AoC9q7cvfnd7EIJadA1kEw/o8A7aPnNrZiatZkduF8M=; b=n69EizcJiBxXt/tiI2jySbhJ5dLCce7R47OLg8SRaqNguWIXWbsdv5wkv52MPiryP5 gTmXkv12av/Ew49P0y0ytIeVq3pM5EIxhPsXjwGsc+q8zYA6fBWTveHYIVaUQpAOeVe0 cp1vqAhpz0xceeTN+AAg3K5xRa9651hGLigzRv/EPKgG1juUcQfUH/E8fhGtjYaPdS0J ZJfKRhpGnT1NMEAe2oVltWDXuTVAhdZ9BJnDR79wawL/Dpe+ynxJ1Uy4cmvF10AzQPvb aI7kPeDnQJBykT9Qut9fVDkoWKyw28G0MqjVWOG08Gh7mm6QmUD5cInVIjUhOa13eWb1 DLJQ== X-Gm-Message-State: AOAM533+/IDv46hT/ukg9pc7pot3/HG7VbdUuJAwzZj5D9U0MvYL3Ick tF/OWESfYP4sbS+q0VS2Ebc= X-Google-Smtp-Source: ABdhPJyY2Jlww0kNaOXMHCPJbz7OaTbwMLNHERG4ccYfF60NPojhO4W5NyBfkEbYnlotM9w1NNVIEQ== X-Received: by 2002:a05:620a:3724:b0:6a0:162e:48c0 with SMTP id de36-20020a05620a372400b006a0162e48c0mr3188348qkb.720.1652970248835; Thu, 19 May 2022 07:24:08 -0700 (PDT) Received: from localhost.localdomain ([217.138.206.82]) by smtp.gmail.com with ESMTPSA id c15-20020ac85a8f000000b002f39b99f697sm1539342qtc.49.2022.05.19.07.24.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 May 2022 07:24:08 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Michael Turquette , Stephen Boyd , Matthias Brugger , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , AngeloGioacchino Del Regno , Tinghan Shen , Chun-Jie Chen , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Chen-Yu Tsai , Bartosz Golaszewski , Yassine Oudjana , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Rob Herring Subject: [PATCH v2 1/4] dt-bindings: clock: Add Mediatek MT6735 clock bindings Date: Thu, 19 May 2022 18:22:08 +0400 Message-Id: <20220519142211.458336-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220519142211.458336-1-y.oudjana@protonmail.com> References: <20220519142211.458336-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add clock definitions for Mediatek MT6735 clocks provided by apmixedsys, topckgen, infracfg and pericfg. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring --- MAINTAINERS | 10 +++ .../clock/mediatek,mt6735-apmixedsys.h | 16 ++++ .../clock/mediatek,mt6735-infracfg.h | 25 ++++++ .../clock/mediatek,mt6735-pericfg.h | 37 +++++++++ .../clock/mediatek,mt6735-topckgen.h | 79 +++++++++++++++++++ 5 files changed, 167 insertions(+) create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h diff --git a/MAINTAINERS b/MAINTAINERS index 6516f9c6d28e..a59069263cfb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12494,6 +12494,16 @@ S: Maintained F: Documentation/devicetree/bindings/mmc/mtk-sd.yaml F: drivers/mmc/host/mtk-sd.c =20 +MEDIATEK MT6735 CLOCK DRIVERS +M: Yassine Oudjana +L: linux-clk@vger.kernel.org +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h +F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h +F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h +F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h + MEDIATEK MT76 WIRELESS LAN DRIVER M: Felix Fietkau M: Lorenzo Bianconi diff --git a/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h b/inclu= de/dt-bindings/clock/mediatek,mt6735-apmixedsys.h new file mode 100644 index 000000000000..3dda719fd5d5 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H +#define _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H + +#define ARMPLL 0 +#define MAINPLL 1 +#define UNIVPLL 2 +#define MMPLL 3 +#define MSDCPLL 4 +#define VENCPLL 5 +#define TVDPLL 6 +#define APLL1 7 +#define APLL2 8 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-infracfg.h b/include= /dt-bindings/clock/mediatek,mt6735-infracfg.h new file mode 100644 index 000000000000..979a174ff8b6 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H +#define _DT_BINDINGS_CLK_MT6735_INFRACFG_H + +#define DBGCLK 0 +#define GCE 1 +#define TRBG 2 +#define CPUM 3 +#define DEVAPC 4 +#define AUDIO 5 +#define GCPU 6 +#define L2C_SRAM 7 +#define M4U 8 +#define CLDMA 9 +#define CONNMCU_BUS 10 +#define KP 11 +#define APXGPT 12 +#define SEJ 13 +#define CCIF0_AP 14 +#define CCIF1_AP 15 +#define PMIC_SPI 16 +#define PMIC_WRAP 17 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-pericfg.h b/include/= dt-bindings/clock/mediatek,mt6735-pericfg.h new file mode 100644 index 000000000000..16f3c6a9a772 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_PERICFG_H +#define _DT_BINDINGS_CLK_MT6735_PERICFG_H + +#define DISP_PWM 0 +#define THERM 1 +#define PWM1 2 +#define PWM2 3 +#define PWM3 4 +#define PWM4 5 +#define PWM5 6 +#define PWM6 7 +#define PWM7 8 +#define PWM 9 +#define USB0 10 +#define IRDA 11 +#define APDMA 12 +#define MSDC30_0 13 +#define MSDC30_1 14 +#define MSDC30_2 15 +#define MSDC30_3 16 +#define UART0 17 +#define UART1 18 +#define UART2 19 +#define UART3 20 +#define UART4 21 +#define BTIF 22 +#define I2C0 23 +#define I2C1 24 +#define I2C2 25 +#define I2C3 26 +#define AUXADC 27 +#define SPI0 28 +#define IRTX 29 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-topckgen.h b/include= /dt-bindings/clock/mediatek,mt6735-topckgen.h new file mode 100644 index 000000000000..a771910a4b8a --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H +#define _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H + +#define AD_SYS_26M_CK 0 +#define CLKPH_MCK_O 1 +#define DMPLL 2 +#define DPI_CK 3 +#define WHPLL_AUDIO_CK 4 + +#define SYSPLL_D2 5 +#define SYSPLL_D3 6 +#define SYSPLL_D5 7 +#define SYSPLL1_D2 8 +#define SYSPLL1_D4 9 +#define SYSPLL1_D8 10 +#define SYSPLL1_D16 11 +#define SYSPLL2_D2 12 +#define SYSPLL2_D4 13 +#define SYSPLL3_D2 14 +#define SYSPLL3_D4 15 +#define SYSPLL4_D2 16 +#define SYSPLL4_D4 17 +#define UNIVPLL_D2 18 +#define UNIVPLL_D3 19 +#define UNIVPLL_D5 20 +#define UNIVPLL_D26 21 +#define UNIVPLL1_D2 22 +#define UNIVPLL1_D4 23 +#define UNIVPLL1_D8 24 +#define UNIVPLL2_D2 25 +#define UNIVPLL2_D4 26 +#define UNIVPLL2_D8 27 +#define UNIVPLL3_D2 28 +#define UNIVPLL3_D4 29 +#define MSDCPLL_D2 30 +#define MSDCPLL_D4 31 +#define MSDCPLL_D8 32 +#define MSDCPLL_D16 33 +#define VENCPLL_D3 34 +#define TVDPLL_D2 35 +#define TVDPLL_D4 36 +#define DMPLL_D2 37 +#define DMPLL_D4 38 +#define DMPLL_D8 39 +#define AD_SYS_26M_D2 40 + +#define AXI_SEL 41 +#define MEM_SEL 42 +#define DDRPHY_SEL 43 +#define MM_SEL 44 +#define PWM_SEL 45 +#define VDEC_SEL 46 +#define MFG_SEL 47 +#define CAMTG_SEL 48 +#define UART_SEL 49 +#define SPI_SEL 50 +#define USB20_SEL 51 +#define MSDC50_0_SEL 52 +#define MSDC30_0_SEL 53 +#define MSDC30_1_SEL 54 +#define MSDC30_2_SEL 55 +#define MSDC30_3_SEL 56 +#define AUDIO_SEL 57 +#define AUDINTBUS_SEL 58 +#define PMICSPI_SEL 59 +#define SCP_SEL 60 +#define ATB_SEL 61 +#define DPI0_SEL 62 +#define SCAM_SEL 63 +#define MFG13M_SEL 64 +#define AUD1_SEL 65 +#define AUD2_SEL 66 +#define IRDA_SEL 67 +#define IRTX_SEL 68 +#define DISPPWM_SEL 69 + +#endif --=20 2.36.1 From nobody Sun Sep 22 01:29:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 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linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Rob Herring Subject: [PATCH v2 2/4] dt-bindings: reset: Add MT6735 reset bindings Date: Thu, 19 May 2022 18:22:09 +0400 Message-Id: <20220519142211.458336-3-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220519142211.458336-1-y.oudjana@protonmail.com> References: <20220519142211.458336-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add reset definitions for Mediatek MT6735 resets provided by infracfg and pericfg. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring --- MAINTAINERS | 2 ++ .../reset/mediatek,mt6735-infracfg.h | 31 +++++++++++++++++++ .../reset/mediatek,mt6735-pericfg.h | 31 +++++++++++++++++++ 3 files changed, 64 insertions(+) create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h diff --git a/MAINTAINERS b/MAINTAINERS index a59069263cfb..1c0af554a7b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12503,6 +12503,8 @@ F: include/dt-bindings/clock/mediatek,mt6735-apmixe= dsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h +F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h +F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h =20 MEDIATEK MT76 WIRELESS LAN DRIVER M: Felix Fietkau diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include= /dt-bindings/reset/mediatek,mt6735-infracfg.h new file mode 100644 index 000000000000..86448f946568 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RST_MT6735_INFRACFG_H +#define _DT_BINDINGS_RST_MT6735_INFRACFG_H + +#define EMI_REG_RST 0 +#define DRAMC0_AO_RST 1 +#define AP_CIRQ_EINT_RST 3 +#define APXGPT_RST 4 +#define SCPSYS_RST 5 +#define KP_RST 6 +#define PMIC_WRAP_RST 7 +#define CLDMA_AO_TOP_RST 8 +#define EMI_RST 16 +#define CCIF_RST 17 +#define DRAMC0_RST 18 +#define EMI_AO_REG_RST 19 +#define CCIF_AO_RST 20 +#define TRNG_RST 21 +#define SYS_CIRQ_RST 22 +#define GCE_RST 23 +#define MM_IOMMU_RST 24 +#define CCIF1_RST 25 +#define CLDMA_TOP_PD_RST 26 +#define CBIP_P2P_MFG 27 +#define CBIP_P2P_APMIXED 28 +#define CBIP_P2P_CKSYS 29 +#define CBIP_P2P_MIPI 30 +#define CBIP_P2P_DDRPHY 31 + +#endif diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/= dt-bindings/reset/mediatek,mt6735-pericfg.h new file mode 100644 index 000000000000..6cdfaa7ddadf --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RST_MT6735_PERICFG_H +#define _DT_BINDINGS_RST_MT6735_PERICFG_H + +#define UART0_SW_RST 0 +#define UART1_SW_RST 1 +#define UART2_SW_RST 2 +#define UART3_SW_RST 3 +#define UART4_SW_RST 4 +#define BTIF_SW_RST 6 +#define DISP_PWM_SW_RST 7 +#define PWM_SW_RST 8 +#define AUXADC_SW_RST 10 +#define DMA_SW_RST 11 +#define IRDA_SW_RST 12 +#define IRTX_SW_RST 13 +#define THERM_SW_RST 16 +#define MSDC2_SW_RST 17 +#define MSDC3_SW_RST 17 +#define MSDC0_SW_RST 19 +#define MSDC1_SW_RST 20 +#define I2C0_SW_RST 22 +#define I2C1_SW_RST 23 +#define I2C2_SW_RST 24 +#define I2C3_SW_RST 25 +#define USB_SW_RST 28 + +#define SPI0_SW_RST 33 + +#endif --=20 2.36.1 From nobody Sun Sep 22 01:29:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E72D5C433F5 for ; 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Thu, 19 May 2022 07:24:33 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Michael Turquette , Stephen Boyd , Matthias Brugger , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , AngeloGioacchino Del Regno , Tinghan Shen , Chun-Jie Chen , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Chen-Yu Tsai , Bartosz Golaszewski , Yassine Oudjana , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Rob Herring Subject: [PATCH v2 3/4] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Date: Thu, 19 May 2022 18:22:10 +0400 Message-Id: <20220519142211.458336-4-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220519142211.458336-1-y.oudjana@protonmail.com> References: <20220519142211.458336-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add compatible strings for MT6735 apmixedsys, topckgen, infracfg and pericfg. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring --- .../bindings/arm/mediatek/mediatek,infracfg.yaml | 8 +++++--- .../bindings/arm/mediatek/mediatek,pericfg.yaml | 1 + .../devicetree/bindings/clock/mediatek,apmixedsys.yaml | 4 +++- .../devicetree/bindings/clock/mediatek,topckgen.yaml | 4 +++- 4 files changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infrac= fg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.= yaml index 8681b785ed6d..aa1bb13e0d67 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml @@ -11,9 +11,10 @@ maintainers: =20 description: The Mediatek infracfg controller provides various clocks and reset outpu= ts - to the system. The clock values can be found in , - and reset values in and - . + to the system. The clock values can be found in + and , and reset values in + , and + . =20 properties: compatible: @@ -22,6 +23,7 @@ properties: - enum: - mediatek,mt2701-infracfg - mediatek,mt2712-infracfg + - mediatek,mt6735-infracfg - mediatek,mt6765-infracfg - mediatek,mt6779-infracfg_ao - mediatek,mt6797-infracfg diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericf= g.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.ya= ml index 611f666f359d..94e5e003e60e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -20,6 +20,7 @@ properties: - enum: - mediatek,mt2701-pericfg - mediatek,mt2712-pericfg + - mediatek,mt6735-pericfg - mediatek,mt6765-pericfg - mediatek,mt7622-pericfg - mediatek,mt7629-pericfg diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.ya= ml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml index 770546195fb5..3a186621e7a9 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml @@ -12,7 +12,8 @@ maintainers: =20 description: The Mediatek apmixedsys controller provides PLLs to the system. - The clock values can be found in . + The clock values can be found in + and . =20 properties: compatible: @@ -32,6 +33,7 @@ properties: - enum: - mediatek,mt2701-apmixedsys - mediatek,mt2712-apmixedsys + - mediatek,mt6735-apmixedsys - mediatek,mt6765-apmixedsys - mediatek,mt6779-apmixedsys - mediatek,mt7629-apmixedsys diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml= b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml index 5b8b37a2e594..920bf0828d58 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml @@ -12,7 +12,8 @@ maintainers: =20 description: The Mediatek topckgen controller provides various clocks to the system. - The clock values can be found in . + The clock values can be found in and + . =20 properties: compatible: @@ -31,6 +32,7 @@ properties: - enum: - mediatek,mt2701-topckgen - mediatek,mt2712-topckgen + - mediatek,mt6735-topckgen - mediatek,mt6765-topckgen - mediatek,mt6779-topckgen - mediatek,mt7629-topckgen --=20 2.36.1 From nobody Sun Sep 22 01:29:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 133F8C433F5 for ; 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Thu, 19 May 2022 07:24:52 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Michael Turquette , Stephen Boyd , Matthias Brugger , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , AngeloGioacchino Del Regno , Tinghan Shen , Chun-Jie Chen , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Chen-Yu Tsai , Bartosz Golaszewski , Yassine Oudjana , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht Subject: [PATCH v2 4/4] clk: mediatek: Add drivers for MediaTek MT6735 main clock drivers Date: Thu, 19 May 2022 18:22:11 +0400 Message-Id: <20220519142211.458336-5-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220519142211.458336-1-y.oudjana@protonmail.com> References: <20220519142211.458336-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add drivers for MT6735 apmixedsys, topckgen, infracfg and pericfg clock and reset controllers. These provide the base clocks on the platform, and should be enough to bring up all essential blocks including PWRAP, MSDC and peripherals (UART, I2C, SPI). Signed-off-by: Yassine Oudjana --- Dependencies: - clk: mediatek: Move to struct clk_hw provider APIs (series) https://patchwork.kernel.org/project/linux-mediatek/cover/20220510104804.= 544597-1-wenst@chromium.org/=20 - Cleanup MediaTek clk reset drivers and support MT8192/MT8195 (series) https://patchwork.kernel.org/project/linux-mediatek/cover/20220503093856.= 22250-1-rex-bc.chen@mediatek.com/ - Export required symbols to compile clk drivers as module (single patch) https://patchwork.kernel.org/project/linux-mediatek/patch/20220518111652.= 223727-7-angelogioacchino.delregno@collabora.com/ - clk: mediatek: Improvements to simple probe/remove and reset controller u= nregistration https://patchwork.kernel.org/project/linux-clk/cover/20220519134728.45664= 3-1-y.oudjana@protonmail.com/ MAINTAINERS | 4 + drivers/clk/mediatek/Kconfig | 9 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-apmixedsys.c | 235 ++++ drivers/clk/mediatek/clk-mt6735-infracfg.c | 205 ++++ drivers/clk/mediatek/clk-mt6735-pericfg.c | 301 +++++ drivers/clk/mediatek/clk-mt6735-topckgen.c | 1087 ++++++++++++++++++ 7 files changed, 1842 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixedsys.c create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c diff --git a/MAINTAINERS b/MAINTAINERS index 1c0af554a7b6..65f7c95bba9a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12499,6 +12499,10 @@ M: Yassine Oudjana L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: drivers/clk/mediatek/clk-mt6735-apmixedsys.c +F: drivers/clk/mediatek/clk-mt6735-infracfg.c +F: drivers/clk/mediatek/clk-mt6735-pericfg.c +F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index d5936cfb3bee..2d2d51c9829e 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -117,6 +117,15 @@ config COMMON_CLK_MT2712_VENCSYS help This driver supports MediaTek MT2712 vencsys clocks. =20 +config COMMON_CLK_MT6735 + tristate "Main clock drivers for MediaTek MT6735" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This enables drivers for clocks and resets provided + by apmixedsys, topckgen, infracfg and pericfg on the + MediaTek MT6735 SoC. + config COMMON_CLK_MT6765 bool "Clock driver for MediaTek MT6765" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index caf2ce93d666..45530dae64a2 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mtk.o clk-pll.o clk-gate.o clk-= apmixed.o clk-cpumux.o reset.o clk-mux.o =20 +obj-$(CONFIG_COMMON_CLK_MT6735) +=3D clk-mt6735-apmixedsys.o clk-mt6735-in= fracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6765) +=3D clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) +=3D clk-mt6765-audio.o obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) +=3D clk-mt6765-cam.o diff --git a/drivers/clk/mediatek/clk-mt6735-apmixedsys.c b/drivers/clk/med= iatek/clk-mt6735-apmixedsys.c new file mode 100644 index 000000000000..65afbe8d38fa --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-apmixedsys.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-mtk.h" +#include "clk-pll.h" + +#include + +#define AP_PLL_CON_5 0x014 +#define ARMPLL_CON0 0x200 +#define ARMPLL_CON1 0x204 +#define ARMPLL_PWR_CON0 0x20c +#define MAINPLL_CON0 0x210 +#define MAINPLL_CON1 0x214 +#define MAINPLL_PWR_CON0 0x21c +#define UNIVPLL_CON0 0x220 +#define UNIVPLL_CON1 0x224 +#define UNIVPLL_PWR_CON0 0x22c +#define MMPLL_CON0 0x230 +#define MMPLL_CON1 0x234 +#define MMPLL_PWR_CON0 0x23c +#define MSDCPLL_CON0 0x240 +#define MSDCPLL_CON1 0x244 +#define MSDCPLL_PWR_CON0 0x24c +#define VENCPLL_CON0 0x250 +#define VENCPLL_CON1 0x254 +#define VENCPLL_PWR_CON0 0x25c +#define TVDPLL_CON0 0x260 +#define TVDPLL_CON1 0x264 +#define TVDPLL_PWR_CON0 0x26c +#define APLL1_CON0 0x270 +#define APLL1_CON1 0x274 +#define APLL1_CON2 0x278 +#define APLL1_PWR_CON0 0x280 +#define APLL2_CON0 0x284 +#define APLL2_CON1 0x288 +#define APLL2_CON2 0x28c +#define APLL2_PWR_CON0 0x294 + +#define CON0_RST_BAR BIT(24) + +static const struct mtk_pll_data apmixedsys_plls[] =3D { + { + .id =3D ARMPLL, + .name =3D "armpll", + .parent_name =3D "clk26m", + + .reg =3D ARMPLL_CON0, + .pwr_reg =3D ARMPLL_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D ARMPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D ARMPLL_CON1, + .pcw_chg_reg =3D ARMPLL_CON1, + .pcwbits =3D 21, + + .flags =3D PLL_AO + }, + { + .id =3D MAINPLL, + .name =3D "mainpll", + .parent_name =3D "clk26m", + + .reg =3D MAINPLL_CON0, + .pwr_reg =3D MAINPLL_PWR_CON0, + .en_mask =3D 0xf0000101, + + .pd_reg =3D MAINPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D MAINPLL_CON1, + .pcw_chg_reg =3D MAINPLL_CON1, + .pcwbits =3D 21, + + .flags =3D HAVE_RST_BAR, + .rst_bar_mask =3D CON0_RST_BAR + }, + { + .id =3D UNIVPLL, + .name =3D "univpll", + .parent_name =3D "clk26m", + + .reg =3D UNIVPLL_CON0, + .pwr_reg =3D UNIVPLL_PWR_CON0, + .en_mask =3D 0xfc000001, + + .pd_reg =3D UNIVPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D UNIVPLL_CON1, + .pcw_chg_reg =3D UNIVPLL_CON1, + .pcwbits =3D 21, + + .flags =3D HAVE_RST_BAR, + .rst_bar_mask =3D CON0_RST_BAR + }, + { + .id =3D MMPLL, + .name =3D "mmpll", + .parent_name =3D "clk26m", + + .reg =3D MMPLL_CON0, + .pwr_reg =3D MMPLL_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D MMPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D MMPLL_CON1, + .pcw_chg_reg =3D MMPLL_CON1, + .pcwbits =3D 21 + }, + { + .id =3D MSDCPLL, + .name =3D "msdcpll", + .parent_name =3D "clk26m", + + .reg =3D MSDCPLL_CON0, + .pwr_reg =3D MSDCPLL_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D MSDCPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D MSDCPLL_CON1, + .pcw_chg_reg =3D MSDCPLL_CON1, + .pcwbits =3D 21, + }, + { + .id =3D VENCPLL, + .name =3D "vencpll", + .parent_name =3D "clk26m", + + .reg =3D VENCPLL_CON0, + .pwr_reg =3D VENCPLL_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D VENCPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D VENCPLL_CON1, + .pcw_chg_reg =3D VENCPLL_CON1, + .pcwbits =3D 21, + + .flags =3D HAVE_RST_BAR, + .rst_bar_mask =3D CON0_RST_BAR + }, + { + .id =3D TVDPLL, + .name =3D "tvdpll", + .parent_name =3D "clk26m", + + .reg =3D TVDPLL_CON0, + .pwr_reg =3D TVDPLL_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D TVDPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D TVDPLL_CON1, + .pcw_chg_reg =3D TVDPLL_CON1, + .pcwbits =3D 21 + }, + { + .id =3D APLL1, + .name =3D "apll1", + .parent_name =3D "clk26m", + + .reg =3D APLL1_CON0, + .pwr_reg =3D APLL1_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D APLL1_CON0, + .pd_shift =3D 4, + + .pcw_reg =3D APLL1_CON1, + .pcw_chg_reg =3D APLL1_CON1, + .pcwbits =3D 31, + + .tuner_reg =3D APLL1_CON2, + .tuner_en_reg =3D AP_PLL_CON_5, + .tuner_en_bit =3D 0 + }, + { + .id =3D APLL2, + .name =3D "apll2", + .parent_name =3D "clk26m", + + .reg =3D APLL2_CON0, + .pwr_reg =3D APLL2_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D APLL2_CON0, + .pd_shift =3D 4, + + .pcw_reg =3D APLL2_CON1, + .pcw_chg_reg =3D APLL2_CON1, + .pcwbits =3D 31, + + .tuner_reg =3D APLL1_CON2, + .tuner_en_reg =3D AP_PLL_CON_5, + .tuner_en_bit =3D 1 + } +}; + +static const struct mtk_clk_desc apmixedsys_clks =3D { + .plls =3D apmixedsys_plls, + .num_plls =3D ARRAY_SIZE(apmixedsys_plls) +}; + +static const struct of_device_id of_match_mt6735_apmixedsys[] =3D { + { .compatible =3D "mediatek,mt6735-apmixedsys", .data =3D &apmixedsys_clk= s }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_apmixedsys =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-apmixedsys", + .of_match_table =3D of_match_mt6735_apmixedsys, + }, +}; +module_platform_driver(clk_mt6735_apmixedsys); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 apmixedsys clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-infracfg.c b/drivers/clk/media= tek/clk-mt6735-infracfg.c new file mode 100644 index 000000000000..37cf64a192ab --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-infracfg.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define INFRA_RST0 0x30 +#define INFRA_GLOBALCON_PDN0 0x40 +#define INFRA_PDN1 0x44 +#define INFRA_PDN_STA 0x48 + +static struct mtk_gate_regs infra_cg_regs =3D { + .set_ofs =3D INFRA_GLOBALCON_PDN0, + .clr_ofs =3D INFRA_PDN1, + .sta_ofs =3D INFRA_PDN_STA, +}; + +static const struct mtk_gate infracfg_gates[] =3D { + { + .id =3D DBGCLK, + .name =3D "dbgclk", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 0, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D GCE, + .name =3D "gce", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 1, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D TRBG, + .name =3D "trbg", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 2, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CPUM, + .name =3D "cpum", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 3, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D DEVAPC, + .name =3D "devapc", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 4, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D AUDIO, + .name =3D "audio", + .parent_name =3D "aud_intbus_sel", + .regs =3D &infra_cg_regs, + .shift =3D 5, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D GCPU, + .name =3D "gcpu", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 6, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D L2C_SRAM, + .name =3D "l2csram", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 7, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D M4U, + .name =3D "m4u", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 8, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CLDMA, + .name =3D "cldma", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 12, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CONNMCU_BUS, + .name =3D "connmcu_bus", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 15, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D KP, + .name =3D "kp", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 16, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D APXGPT, + .name =3D "apxgpt", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 18, + .ops =3D &mtk_clk_gate_ops_setclr, + .flags =3D CLK_IS_CRITICAL + }, + { + .id =3D SEJ, + .name =3D "sej", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 19, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CCIF0_AP, + .name =3D "ccif0ap", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 20, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CCIF1_AP, + .name =3D "ccif1ap", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 21, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PMIC_SPI, + .name =3D "pmicspi", + .parent_name =3D "pmicspi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 22, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PMIC_WRAP, + .name =3D "pmicwrap", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 23, + .ops =3D &mtk_clk_gate_ops_setclr + }, +}; + +static u16 infracfg_rst_ofs[] =3D { INFRA_RST0 }; + +static const struct mtk_clk_rst_desc infracfg_resets =3D { + .version =3D MTK_RST_SET_CLR, + .rst_bank_ofs =3D infracfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infracfg_rst_ofs) +}; + +static const struct mtk_clk_desc infracfg_clks =3D { + .gates =3D infracfg_gates, + .num_gates =3D ARRAY_SIZE(infracfg_gates), + + .rst_desc =3D &infracfg_resets +}; + +static const struct of_device_id of_match_mt6735_infracfg[] =3D { + { .compatible =3D "mediatek,mt6735-infracfg", .data =3D &infracfg_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_infracfg =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-infracfg", + .of_match_table =3D of_match_mt6735_infracfg, + }, +}; +module_platform_driver(clk_mt6735_infracfg); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 infracfg clock and reset driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-pericfg.c b/drivers/clk/mediat= ek/clk-mt6735-pericfg.c new file mode 100644 index 000000000000..6ec987197a22 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-pericfg.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define PERI_GLOBALCON_RST0 0x00 +#define PERI_GLOBALCON_RST1 0x04 +#define PERI_GLOBALCON_PDN0_SET 0x08 +#define PERI_GLOBALCON_PDN0_CLR 0x10 +#define PERI_GLOBALCON_PDN0_STA 0x18 + +static struct mtk_gate_regs peri_cg_regs =3D { + .set_ofs =3D PERI_GLOBALCON_PDN0_SET, + .clr_ofs =3D PERI_GLOBALCON_PDN0_CLR, + .sta_ofs =3D PERI_GLOBALCON_PDN0_STA, +}; + +static const struct mtk_gate pericfg_gates[] =3D { + { + .id =3D DISP_PWM, + .name =3D "disp_pwm", + .parent_name =3D "disppwm_sel", + .regs =3D &peri_cg_regs, + .shift =3D 0, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D THERM, + .name =3D "therm", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 1, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM1, + .name =3D "pwm1", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 2, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM2, + .name =3D "pwm2", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 3, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM3, + .name =3D "pwm3", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 4, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM4, + .name =3D "pwm4", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 5, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM5, + .name =3D "pwm5", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 6, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM6, + .name =3D "pwm6", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 7, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM7, + .name =3D "pwm7", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 8, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM, + .name =3D "pwm", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 9, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D USB0, + .name =3D "usb0", + .parent_name =3D "usb20_sel", + .regs =3D &peri_cg_regs, + .shift =3D 10, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D IRDA, + .name =3D "irda", + .parent_name =3D "irda_sel", + .regs =3D &peri_cg_regs, + .shift =3D 11, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D APDMA, + .name =3D "apdma", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 12, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_0, + .name =3D "msdc30_0", + .parent_name =3D "msdc30_0_sel", + .regs =3D &peri_cg_regs, + .shift =3D 13, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_1, + .name =3D "msdc30_1", + .parent_name =3D "msdc30_1_sel", + .regs =3D &peri_cg_regs, + .shift =3D 14, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_2, + .name =3D "msdc30_2", + .parent_name =3D "msdc30_2_sel", + .regs =3D &peri_cg_regs, + .shift =3D 15, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_3, + .name =3D "msdc30_3", + .parent_name =3D "msdc30_3_sel", + .regs =3D &peri_cg_regs, + .shift =3D 16, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART0, + .name =3D "uart0", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 17, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART1, + .name =3D "uart1", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 18, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART2, + .name =3D "uart2", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 19, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART3, + .name =3D "uart3", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 20, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART4, + .name =3D "uart4", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 21, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D BTIF, + .name =3D "btif", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 22, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C0, + .name =3D "i2c0", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 23, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C1, + .name =3D "i2c1", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 24, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C2, + .name =3D "i2c2", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 25, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C3, + .name =3D "i2c3", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 26, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D AUXADC, + .name =3D "auxadc", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 27, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D SPI0, + .name =3D "spi0", + .parent_name =3D "spi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 28, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D IRTX, + .name =3D "irtx", + .parent_name =3D "irtx_sel", + .regs =3D &peri_cg_regs, + .shift =3D 29, + .ops =3D &mtk_clk_gate_ops_setclr + }, +}; + +static u16 pericfg_rst_ofs[] =3D { PERI_GLOBALCON_RST0, PERI_GLOBALCON_RST= 1 }; + +static const struct mtk_clk_rst_desc pericfg_resets =3D { + .version =3D MTK_RST_SIMPLE, + .rst_bank_ofs =3D pericfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs) +}; + +static const struct mtk_clk_desc pericfg_clks =3D { + .gates =3D pericfg_gates, + .num_gates =3D ARRAY_SIZE(pericfg_gates), + + .rst_desc =3D &pericfg_resets +}; + +static const struct of_device_id of_match_mt6735_pericfg[] =3D { + { .compatible =3D "mediatek,mt6735-pericfg", .data =3D &pericfg_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_pericfg =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-pericfg", + .of_match_table =3D of_match_mt6735_pericfg, + }, +}; +module_platform_driver(clk_mt6735_pericfg); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 pericfg clock driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6735-topckgen.c b/drivers/clk/media= tek/clk-mt6735-topckgen.c new file mode 100644 index 000000000000..4540bbd2cfcd --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-topckgen.c @@ -0,0 +1,1087 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-mtk.h" +#include "clk-mux.h" + +#include + +#define CLK_CFG_0 0x40 +#define CLK_CFG_0_SET 0x44 +#define CLK_CFG_0_CLR 0x48 +#define CLK_CFG_1 0x50 +#define CLK_CFG_1_SET 0x54 +#define CLK_CFG_1_CLR 0x58 +#define CLK_CFG_2 0x60 +#define CLK_CFG_2_SET 0x64 +#define CLK_CFG_2_CLR 0x68 +#define CLK_CFG_3 0x70 +#define CLK_CFG_3_SET 0x74 +#define CLK_CFG_3_CLR 0x78 +#define CLK_CFG_4 0x80 +#define CLK_CFG_4_SET 0x84 +#define CLK_CFG_4_CLR 0x88 +#define CLK_CFG_5 0x90 +#define CLK_CFG_5_SET 0x94 +#define CLK_CFG_5_CLR 0x98 +#define CLK_CFG_6 0xa0 +#define CLK_CFG_6_SET 0xa4 +#define CLK_CFG_6_CLR 0xa8 +#define CLK_CFG_7 0xb0 +#define CLK_CFG_7_SET 0xb4 +#define CLK_CFG_7_CLR 0xb8 + +/* Some clocks with unknown details are modeled as fixed clocks */ +static const struct mtk_fixed_clk topckgen_fixed_clks[] =3D { + { + /* + * This clock is available as a parent option for multiple + * muxes and seems like an alternative name for clk26m at first, + * but it appears alongside it in several muxes which should + * mean it is a separate clock. + */ + .id =3D AD_SYS_26M_CK, + .name =3D "ad_sys_26m_ck", + .parent =3D "clk26m", + .rate =3D 26 * MHZ, + }, + { + /* + * This clock is the parent of DMPLL divisors. It might be MEMPLL + * or its parent, as DMPLL appears to be an alternative name for + * MEMPLL. + */ + .id =3D CLKPH_MCK_O, + .name =3D "clkph_mck_o", + .parent =3D NULL + }, + { + /* + * DMPLL clock (dmpll_ck), controlled by DDRPHY. + */ + .id =3D DMPLL, + .name =3D "dmpll", + .parent =3D "clkph_mck_o" + }, + { + /* + * MIPI DPI clock. Parent option for dpi0_sel. Unknown parent. + */ + .id =3D DPI_CK, + .name =3D "dpi_ck", + .parent =3D NULL + }, + { + /* + * This clock is a child of WHPLL which is controlled by + * the modem. + */ + .id =3D WHPLL_AUDIO_CK, + .name =3D "whpll_audio_ck", + .parent =3D NULL + }, +}; + +static const struct mtk_fixed_factor topckgen_factors[] =3D { + { + .id =3D SYSPLL_D2, + .name =3D "syspll_d2", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D SYSPLL_D3, + .name =3D "syspll_d3", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 3 + }, + { + .id =3D SYSPLL_D5, + .name =3D "syspll_d5", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 5 + }, + { + .id =3D SYSPLL1_D2, + .name =3D "syspll1_d2", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D SYSPLL1_D4, + .name =3D "syspll1_d4", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D SYSPLL1_D8, + .name =3D "syspll1_d8", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 8 + }, + { + .id =3D SYSPLL1_D16, + .name =3D "syspll1_d16", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 16 + }, + { + .id =3D SYSPLL2_D2, + .name =3D "syspll2_d2", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D SYSPLL2_D4, + .name =3D "syspll2_d4", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D SYSPLL3_D2, + .name =3D "syspll3_d2", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D SYSPLL3_D4, + .name =3D "syspll3_d4", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D SYSPLL4_D2, + .name =3D "syspll4_d2", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D SYSPLL4_D4, + .name =3D "syspll4_d4", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D UNIVPLL_D2, + .name =3D "univpll_d2", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D UNIVPLL_D3, + .name =3D "univpll_d3", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 3 + }, + { + .id =3D UNIVPLL_D5, + .name =3D "univpll_d5", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 5 + }, + { + .id =3D UNIVPLL_D26, + .name =3D "univpll_d26", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 26 + }, + { + .id =3D UNIVPLL1_D2, + .name =3D "univpll1_d2", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D UNIVPLL1_D4, + .name =3D "univpll1_d4", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D UNIVPLL1_D8, + .name =3D "univpll1_d8", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 8 + }, + { + .id =3D UNIVPLL2_D2, + .name =3D "univpll2_d2", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D UNIVPLL2_D4, + .name =3D "univpll2_d4", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D UNIVPLL2_D8, + .name =3D "univpll2_d8", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 8 + }, + { + .id =3D UNIVPLL3_D2, + .name =3D "univpll3_d2", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D UNIVPLL3_D4, + .name =3D "univpll3_d4", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D MSDCPLL_D2, + .name =3D "msdcpll_d2", + .parent_name =3D "msdcpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D MSDCPLL_D4, + .name =3D "msdcpll_d4", + .parent_name =3D "msdcpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D MSDCPLL_D8, + .name =3D "msdcpll_d8", + .parent_name =3D "msdcpll", + .mult =3D 1, + .div =3D 8 + }, + { + .id =3D MSDCPLL_D16, + .name =3D "msdcpll_d16", + .parent_name =3D "msdcpll", + .mult =3D 1, + .div =3D 16 + }, + { + .id =3D VENCPLL_D3, + .name =3D "vencpll_d3", + .parent_name =3D "vencpll", + .mult =3D 1, + .div =3D 3 + }, + { + .id =3D TVDPLL_D2, + .name =3D "tvdpll_d2", + .parent_name =3D "tvdpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D TVDPLL_D4, + .name =3D "tvdpll_d4", + .parent_name =3D "tvdpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D DMPLL_D2, + .name =3D "dmpll_d2", + .parent_name =3D "clkph_mck_o", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D DMPLL_D4, + .name =3D "dmpll_d4", + .parent_name =3D "clkph_mck_o", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D DMPLL_D8, + .name =3D "dmpll_d8", + .parent_name =3D "clkph_mck_o", + .mult =3D 1, + .div =3D 8 + }, + { + .id =3D AD_SYS_26M_D2, + .name =3D "ad_sys_26m_d2", + .parent_name =3D "clk26m", + .mult =3D 1, + .div =3D 2 + }, +}; + +static const char * const axi_sel_parents[] =3D { + "clk26m", + "syspll1_d2", + "syspll_d5", + "syspll1_d4", + "univpll_d5", + "univpll2_d2", + "dmpll", + "dmpll_d2" +}; + +static const char * const mem_sel_parents[] =3D { + "clk26m", + "dmpll" +}; + +static const char * const ddrphycfg_parents[] =3D { + "clk26m", + "syspll1_d8" +}; + +static const char * const mm_sel_parents[] =3D { + "clk26m", + "vencpll", + "syspll1_d2", + "syspll_d5", + "syspll1_d4", + "univpll_d5", + "univpll2_d2", + "dmpll" +}; + +static const char * const pwm_sel_parents[] =3D { + "clk26m", + "univpll2_d4", + "univpll3_d2", + "univpll1_d4" +}; + +static const char * const vdec_sel_parents[] =3D { + "clk26m", + "syspll1_d2", + "syspll_d5", + "syspll1_d4", + "univpll_d5", + "syspll_d2", + "syspll2_d2", + "msdcpll_d2" +}; + +static const char * const mfg_sel_parents[] =3D { + "clk26m", + "mmpll", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "syspll_d3", + "syspll1_d2", + "syspll_d5", + "univpll_d3", + "univpll1_d2" +}; + +static const char * const camtg_sel_parents[] =3D { + "clk26m", + "univpll_d26", + "univpll2_d2", + "syspll3_d2", + "syspll3_d4", + "msdcpll_d4" +}; + +static const char * const uart_sel_parents[] =3D { + "clk26m", + "univpll2_d8" +}; + +static const char * const spi_sel_parents[] =3D { + "clk26m", + "syspll3_d2", + "msdcpll_d8", + "syspll2_d4", + "syspll4_d2", + "univpll2_d4", + "univpll1_d8" +}; + +static const char * const usb20_sel_parents[] =3D { + "clk26m", + "univpll1_d8", + "univpll3_d4" +}; + +static const char * const msdc50_0_sel_parents[] =3D { + "clk26m", + "syspll1_d2", + "syspll2_d2", + "syspll4_d2", + "univpll_d5", + "univpll1_d4" +}; + +static const char * const msdc30_0_sel_parents[] =3D { + "clk26m", + "msdcpll", + "msdcpll_d2", + "msdcpll_d4", + "syspll2_d2", + "syspll1_d4", + "univpll1_d4", + "univpll_d3", + "univpll_d26", + "syspll2_d4", + "univpll_d2" +}; + +static const char * const msdc30_1_2_sel_parents[] =3D { + "clk26m", + "univpll2_d2", + "msdcpll_d4", + "syspll2_d2", + "syspll1_d4", + "univpll1_d4", + "univpll_d26", + "syspll2_d4" +}; + +static const char * const msdc30_3_sel_parents[] =3D { + "clk26m", + "univpll2_d2", + "msdcpll_d4", + "syspll2_d2", + "syspll1_d4", + "univpll1_d4", + "univpll_d26", + "msdcpll_d16", + "syspll2_d4" +}; + +static const char * const audio_sel_parents[] =3D { + "clk26m", + "syspll3_d4", + "syspll4_d4", + "syspll1_d16" +}; + +static const char * const aud_intbus_sel_parents[] =3D { + "clk26m", + "syspll1_d4", + "syspll4_d2", + "dmpll_d4" +}; + +static const char * const pmicspi_sel_parents[] =3D { + "clk26m", + "syspll1_d8", + "syspll3_d4", + "syspll1_d16", + "univpll3_d4", + "univpll_d26", + "dmpll_d4", + "dmpll_d8" +}; + +static const char * const scp_sel_parents[] =3D { + "clk26m", + "syspll1_d8", + "dmpll_d2", + "dmpll_d4" +}; + +static const char * const atb_sel_parents[] =3D { + "clk26m", + "syspll1_d2", + "syspll_d5", + "dmpll" +}; + +static const char * const dpi0_sel_parents[] =3D { + "clk26m", + "tvdpll", + "tvdpll_d2", + "tvdpll_d4", + "dpi_ck" +}; + +static const char * const scam_sel_parents[] =3D { + "clk26m", + "syspll3_d2", + "univpll2_d4", + "vencpll_d3" +}; + +static const char * const mfg13m_sel_parents[] =3D { + "clk26m", + "ad_sys_26m_d2" +}; + +static const char * const aud_1_2_sel_parents[] =3D { + "clk26m", + "apll1" +}; + +static const char * const irda_sel_parents[] =3D { + "clk26m", + "univpll2_d4" +}; + +static const char * const irtx_sel_parents[] =3D { + "clk26m", + "ad_sys_26m_ck" +}; + +static const char * const disppwm_sel_parents[] =3D { + "clk26m", + "univpll2_d4", + "syspll4_d2_d8", + "ad_sys_26m_ck" +}; + +static const struct mtk_mux topckgen_muxes[] =3D { + { + .id =3D AXI_SEL, + .name =3D "axi_sel", + .parent_names =3D axi_sel_parents, + .num_parents =3D ARRAY_SIZE(axi_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_0, + .set_ofs =3D CLK_CFG_0_SET, + .clr_ofs =3D CLK_CFG_0_CLR, + + .mux_shift =3D 0, + .mux_width =3D 3, + + .ops =3D &mtk_mux_clr_set_upd_ops, + }, + { + .id =3D MEM_SEL, + .name =3D "mem_sel", + .parent_names =3D mem_sel_parents, + .num_parents =3D ARRAY_SIZE(mem_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_0, + .set_ofs =3D CLK_CFG_0_SET, + .clr_ofs =3D CLK_CFG_0_CLR, + + .mux_shift =3D 8, + .mux_width =3D 1, + + .ops =3D &mtk_mux_clr_set_upd_ops, + }, + { + .id =3D DDRPHY_SEL, + .name =3D "ddrphycfg_sel", + .parent_names =3D ddrphycfg_parents, + .num_parents =3D ARRAY_SIZE(ddrphycfg_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_0, + .set_ofs =3D CLK_CFG_0_SET, + .clr_ofs =3D CLK_CFG_0_CLR, + + .mux_shift =3D 16, + .mux_width =3D 1, + + .ops =3D &mtk_mux_clr_set_upd_ops, + }, + { + .id =3D MM_SEL, + .name =3D "mm_sel", + .parent_names =3D mm_sel_parents, + .num_parents =3D ARRAY_SIZE(mm_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_0, + .set_ofs =3D CLK_CFG_0_SET, + .clr_ofs =3D CLK_CFG_0_CLR, + + .mux_shift =3D 24, + .mux_width =3D 3, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D PWM_SEL, + .name =3D "pwm_sel", + .parent_names =3D pwm_sel_parents, + .num_parents =3D ARRAY_SIZE(pwm_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_1, + .set_ofs =3D CLK_CFG_1_SET, + .clr_ofs =3D CLK_CFG_1_CLR, + + .mux_shift =3D 0, + .mux_width =3D 2, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D VDEC_SEL, + .name =3D "vdec_sel", + .parent_names =3D vdec_sel_parents, + .num_parents =3D ARRAY_SIZE(vdec_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_1, + .set_ofs =3D CLK_CFG_1_SET, + .clr_ofs =3D CLK_CFG_1_CLR, + + .mux_shift =3D 8, + .mux_width =3D 3, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MFG_SEL, + .name =3D "mfg_sel", + .parent_names =3D mfg_sel_parents, + .num_parents =3D ARRAY_SIZE(mfg_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_1, + .set_ofs =3D CLK_CFG_1_SET, + .clr_ofs =3D CLK_CFG_1_CLR, + + .mux_shift =3D 16, + .mux_width =3D 4, + .gate_shift =3D 23, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D CAMTG_SEL, + .name =3D "camtg_sel", + .parent_names =3D camtg_sel_parents, + .num_parents =3D ARRAY_SIZE(camtg_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_1, + .set_ofs =3D CLK_CFG_1_SET, + .clr_ofs =3D CLK_CFG_1_CLR, + + .mux_shift =3D 24, + .mux_width =3D 3, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D UART_SEL, + .name =3D "uart_sel", + .parent_names =3D uart_sel_parents, + .num_parents =3D ARRAY_SIZE(uart_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_2, + .set_ofs =3D CLK_CFG_2_SET, + .clr_ofs =3D CLK_CFG_2_CLR, + + .mux_shift =3D 0, + .mux_width =3D 1, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D SPI_SEL, + .name =3D "spi_sel", + .parent_names =3D spi_sel_parents, + .num_parents =3D ARRAY_SIZE(spi_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_2, + .set_ofs =3D CLK_CFG_2_SET, + .clr_ofs =3D CLK_CFG_2_CLR, + + .mux_shift =3D 8, + .mux_width =3D 3, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D USB20_SEL, + .name =3D "usb20_sel", + .parent_names =3D usb20_sel_parents, + .num_parents =3D ARRAY_SIZE(usb20_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_2, + .set_ofs =3D CLK_CFG_2_SET, + .clr_ofs =3D CLK_CFG_2_CLR, + + .mux_shift =3D 16, + .mux_width =3D 2, + .gate_shift =3D 23, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MSDC50_0_SEL, + .name =3D "msdc50_0_sel", + .parent_names =3D msdc50_0_sel_parents, + .num_parents =3D ARRAY_SIZE(msdc50_0_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_2, + .set_ofs =3D CLK_CFG_2_SET, + .clr_ofs =3D CLK_CFG_2_CLR, + + .mux_shift =3D 24, + .mux_width =3D 3, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MSDC30_0_SEL, + .name =3D "msdc30_0_sel", + .parent_names =3D msdc30_0_sel_parents, + .num_parents =3D ARRAY_SIZE(msdc30_0_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_3, + .set_ofs =3D CLK_CFG_3_SET, + .clr_ofs =3D CLK_CFG_3_CLR, + + .mux_shift =3D 0, + .mux_width =3D 4, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MSDC30_1_SEL, + .name =3D "msdc30_1_sel", + .parent_names =3D msdc30_1_2_sel_parents, + .num_parents =3D ARRAY_SIZE(msdc30_1_2_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_3, + .set_ofs =3D CLK_CFG_3_SET, + .clr_ofs =3D CLK_CFG_3_CLR, + + .mux_shift =3D 8, + .mux_width =3D 3, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MSDC30_2_SEL, + .name =3D "msdc30_2_sel", + .parent_names =3D msdc30_1_2_sel_parents, + .num_parents =3D ARRAY_SIZE(msdc30_1_2_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_3, + .set_ofs =3D CLK_CFG_3_SET, + .clr_ofs =3D CLK_CFG_3_CLR, + + .mux_shift =3D 16, + .mux_width =3D 3, + .gate_shift =3D 23, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MSDC30_3_SEL, + .name =3D "msdc30_3_sel", + .parent_names =3D msdc30_3_sel_parents, + .num_parents =3D ARRAY_SIZE(msdc30_3_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_3, + .set_ofs =3D CLK_CFG_3_SET, + .clr_ofs =3D CLK_CFG_3_CLR, + + .mux_shift =3D 24, + .mux_width =3D 4, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D AUDIO_SEL, + .name =3D "audio_sel", + .parent_names =3D audio_sel_parents, + .num_parents =3D ARRAY_SIZE(audio_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_4, + .set_ofs =3D CLK_CFG_4_SET, + .clr_ofs =3D CLK_CFG_4_CLR, + + .mux_shift =3D 0, + .mux_width =3D 2, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D AUDINTBUS_SEL, + .name =3D "aud_intbus_sel", + .parent_names =3D aud_intbus_sel_parents, + .num_parents =3D ARRAY_SIZE(aud_intbus_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_4, + .set_ofs =3D CLK_CFG_4_SET, + .clr_ofs =3D CLK_CFG_4_CLR, + + .mux_shift =3D 8, + .mux_width =3D 2, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D PMICSPI_SEL, + .name =3D "pmicspi_sel", + .parent_names =3D pmicspi_sel_parents, + .num_parents =3D ARRAY_SIZE(pmicspi_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_4, + .set_ofs =3D CLK_CFG_4_SET, + .clr_ofs =3D CLK_CFG_4_CLR, + + .mux_shift =3D 16, + .mux_width =3D 3, + + .ops =3D &mtk_mux_clr_set_upd_ops, + }, + { + .id =3D SCP_SEL, + .name =3D "scp_sel", + .parent_names =3D scp_sel_parents, + .num_parents =3D ARRAY_SIZE(scp_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_4, + .set_ofs =3D CLK_CFG_4_SET, + .clr_ofs =3D CLK_CFG_4_CLR, + + .mux_shift =3D 24, + .mux_width =3D 2, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D ATB_SEL, + .name =3D "atb_sel", + .parent_names =3D atb_sel_parents, + .num_parents =3D ARRAY_SIZE(atb_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_5, + .set_ofs =3D CLK_CFG_5_SET, + .clr_ofs =3D CLK_CFG_5_CLR, + + .mux_shift =3D 0, + .mux_width =3D 2, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D DPI0_SEL, + .name =3D "dpi0_sel", + .parent_names =3D dpi0_sel_parents, + .num_parents =3D ARRAY_SIZE(dpi0_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_5, + .set_ofs =3D CLK_CFG_5_SET, + .clr_ofs =3D CLK_CFG_5_CLR, + + .mux_shift =3D 8, + .mux_width =3D 3, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D SCAM_SEL, + .name =3D "scam_sel", + .parent_names =3D scam_sel_parents, + .num_parents =3D ARRAY_SIZE(scam_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_5, + .set_ofs =3D CLK_CFG_5_SET, + .clr_ofs =3D CLK_CFG_5_CLR, + + .mux_shift =3D 16, + .mux_width =3D 2, + .gate_shift =3D 23, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MFG13M_SEL, + .name =3D "mfg13m_sel", + .parent_names =3D mfg13m_sel_parents, + .num_parents =3D ARRAY_SIZE(mfg13m_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_5, + .set_ofs =3D CLK_CFG_5_SET, + .clr_ofs =3D CLK_CFG_5_CLR, + + .mux_shift =3D 24, + .mux_width =3D 1, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D AUD1_SEL, + .name =3D "aud_1_sel", + .parent_names =3D aud_1_2_sel_parents, + .num_parents =3D ARRAY_SIZE(aud_1_2_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_6, + .set_ofs =3D CLK_CFG_6_SET, + .clr_ofs =3D CLK_CFG_6_CLR, + + .mux_shift =3D 0, + .mux_width =3D 1, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D AUD2_SEL, + .name =3D "aud_2_sel", + .parent_names =3D aud_1_2_sel_parents, + .num_parents =3D ARRAY_SIZE(aud_1_2_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_6, + .set_ofs =3D CLK_CFG_6_SET, + .clr_ofs =3D CLK_CFG_6_CLR, + + .mux_shift =3D 8, + .mux_width =3D 1, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D IRDA_SEL, + .name =3D "irda_sel", + .parent_names =3D irda_sel_parents, + .num_parents =3D ARRAY_SIZE(irda_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_6, + .set_ofs =3D CLK_CFG_6_SET, + .clr_ofs =3D CLK_CFG_6_CLR, + + .mux_shift =3D 16, + .mux_width =3D 1, + .gate_shift =3D 23, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D IRTX_SEL, + .name =3D "irtx_sel", + .parent_names =3D irtx_sel_parents, + .num_parents =3D ARRAY_SIZE(irtx_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_6, + .set_ofs =3D CLK_CFG_6_SET, + .clr_ofs =3D CLK_CFG_6_CLR, + + .mux_shift =3D 24, + .mux_width =3D 1, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D DISPPWM_SEL, + .name =3D "disppwm_sel", + .parent_names =3D disppwm_sel_parents, + .num_parents =3D ARRAY_SIZE(disppwm_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_7, + .set_ofs =3D CLK_CFG_7_SET, + .clr_ofs =3D CLK_CFG_7_CLR, + + .mux_shift =3D 0, + .mux_width =3D 2, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, +}; + +static const struct mtk_clk_desc topckgen_clks =3D { + .fixed_clks =3D topckgen_fixed_clks, + .num_fixed_clks =3D ARRAY_SIZE(topckgen_fixed_clks), + .factors =3D topckgen_factors, + .num_factors =3D ARRAY_SIZE(topckgen_factors), + .muxes =3D topckgen_muxes, + .num_muxes =3D ARRAY_SIZE(topckgen_muxes) +}; + +static const struct of_device_id of_match_mt6735_topckgen[] =3D { + { .compatible =3D "mediatek,mt6735-topckgen", .data =3D &topckgen_clks }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_topckgen =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt6735-topckgen", + .of_match_table =3D of_match_mt6735_topckgen, + }, +}; +module_platform_driver(clk_mt6735_topckgen); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 topckgen clock driver"); +MODULE_LICENSE("GPL"); --=20 2.36.1