From nobody Sun Sep 22 03:41:59 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59CCEC433FE for ; Thu, 19 May 2022 12:56:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238226AbiESM4s (ORCPT ); Thu, 19 May 2022 08:56:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238249AbiESMzn (ORCPT ); Thu, 19 May 2022 08:55:43 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EE1C2BDA24; Thu, 19 May 2022 05:55:39 -0700 (PDT) X-UUID: 74886e7366764e3b89bab67b2b5b6045-20220519 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:08a3c755-0ef7-439c-8fe9-6605d7510f46,OB:10,L OB:10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham, ACTION:release,TS:90 X-CID-INFO: VERSION:1.1.5,REQID:08a3c755-0ef7-439c-8fe9-6605d7510f46,OB:10,LOB :10,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:90 X-CID-META: VersionHash:2a19b09,CLOUDID:0490df79-5ef6-470b-96c9-bdb8ced32786,C OID:19d607bb3d72,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 74886e7366764e3b89bab67b2b5b6045-20220519 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1374838580; Thu, 19 May 2022 20:55:31 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 19 May 2022 20:55:29 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 May 2022 20:55:29 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v7 07/19] clk: mediatek: reset: Support nonsequence base offsets of reset registers Date: Thu, 19 May 2022 20:55:15 +0800 Message-ID: <20220519125527.18544-8-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220519125527.18544-1-rex-bc.chen@mediatek.com> References: <20220519125527.18544-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The bank offsets are not serial for all reset registers. For example, there are five infra reset banks for MT8192: 0x120, 0x130, 0x140, 0x150 and 0x730. To support this, - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of the reset register. - Add a new define RST_NR_PER_BANK to define reset number for each reset bank. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt2701-eth.c | 6 ++++-- drivers/clk/mediatek/clk-mt2701-g3d.c | 6 ++++-- drivers/clk/mediatek/clk-mt2701-hif.c | 6 ++++-- drivers/clk/mediatek/clk-mt2701.c | 11 +++++++---- drivers/clk/mediatek/clk-mt2712.c | 11 +++++++---- drivers/clk/mediatek/clk-mt7622-eth.c | 6 ++++-- drivers/clk/mediatek/clk-mt7622-hif.c | 6 ++++-- drivers/clk/mediatek/clk-mt7622.c | 11 +++++++---- drivers/clk/mediatek/clk-mt7629-eth.c | 6 ++++-- drivers/clk/mediatek/clk-mt7629-hif.c | 6 ++++-- drivers/clk/mediatek/clk-mt8135.c | 11 +++++++---- drivers/clk/mediatek/clk-mt8173.c | 11 +++++++---- drivers/clk/mediatek/clk-mt8183.c | 14 ++++++++++++-- drivers/clk/mediatek/reset.c | 11 ++++++----- drivers/clk/mediatek/reset.h | 6 ++++-- 15 files changed, 85 insertions(+), 43 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/c= lk-mt2701-eth.c index 270d15ce58bf..b4e7f38860d0 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -36,10 +36,12 @@ static const struct mtk_gate eth_clks[] =3D { GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29), }; =20 +static u16 rst_ofs[] =3D { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc =3D { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 1, - .reg_ofs =3D 0x34, + .rst_bank_ofs =3D rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 static const struct of_device_id of_match_clk_mt2701_eth[] =3D { diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/c= lk-mt2701-g3d.c index 9cfd589939e5..5cbc5c42204d 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -35,10 +35,12 @@ static const struct mtk_gate g3d_clks[] =3D { GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), }; =20 +static u16 rst_ofs[] =3D { 0xC, }; + static const struct mtk_clk_rst_desc clk_rst_desc =3D { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 1, - .reg_ofs =3D 0xc, + .rst_bank_ofs =3D rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 static int clk_mt2701_g3dsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/c= lk-mt2701-hif.c index a6b812fcc922..60bda56a102c 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -33,10 +33,12 @@ static const struct mtk_gate hif_clks[] =3D { GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26), }; =20 +static u16 rst_ofs[] =3D { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc =3D { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 1, - .reg_ofs =3D 0x34, + .rst_bank_ofs =3D rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 static const struct of_device_id of_match_clk_mt2701_hif[] =3D { diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index 4c0e25ab033b..413c9d8dd752 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -735,18 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs= [] =3D { FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), }; =20 +static u16 infrasys_rst_ofs[] =3D { 0x30, 0x34, }; +static u16 pericfg_rst_ofs[] =3D { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] =3D { /* infrasys */ { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 2, - .reg_ofs =3D 0x30, + .rst_bank_ofs =3D infrasys_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 2, - .reg_ofs =3D 0x0, + .rst_bank_ofs =3D pericfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), }, }; =20 diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index 036a2baaaf92..fcb4bef974d9 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1258,18 +1258,21 @@ static const struct mtk_pll_data plls[] =3D { 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0), }; =20 +static u16 infrasys_rst_ofs[] =3D { 0x30, 0x34, }; +static u16 pericfg_rst_ofs[] =3D { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] =3D { /* infra */ { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 2, - .reg_ofs =3D 0x30, + .rst_bank_ofs =3D infrasys_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), }, /* peri */ { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 2, - .reg_ofs =3D 0x0, + .rst_bank_ofs =3D pericfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), }, }; =20 diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/c= lk-mt7622-eth.c index 40eefed3d12b..90d55f882215 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -65,10 +65,12 @@ static const struct mtk_gate sgmii_clks[] =3D { "ssusb_cdr_fb", 5), }; =20 +static u16 rst_ofs[] =3D { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc =3D { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 1, - .reg_ofs =3D 0x34, + .rst_bank_ofs =3D rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 static int clk_mt7622_ethsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/c= lk-mt7622-hif.c index ca29d93ce2d0..489b64725b22 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -76,10 +76,12 @@ static const struct mtk_gate pcie_clks[] =3D { GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30), }; =20 +static u16 rst_ofs[] =3D { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc =3D { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 1, - .reg_ofs =3D 0x34, + .rst_bank_ofs =3D rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index 7e62630b5840..6df709ca2860 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -610,18 +610,21 @@ static struct mtk_composite peri_muxes[] =3D { MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1), }; =20 +static u16 infrasys_rst_ofs[] =3D { 0x30, }; +static u16 pericfg_rst_ofs[] =3D { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] =3D { /* infrasys */ { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 1, - .reg_ofs =3D 0x30, + .rst_bank_ofs =3D infrasys_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 2, - .reg_ofs =3D 0x0, + .rst_bank_ofs =3D pericfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), }, }; =20 diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/c= lk-mt7629-eth.c index c20c7853500d..11b346c9d916 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -76,10 +76,12 @@ static const struct mtk_gate sgmii_clks[2][4] =3D { } }; =20 +static u16 rst_ofs[] =3D { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc =3D { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 1, - .reg_ofs =3D 0x34, + .rst_bank_ofs =3D rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 static int clk_mt7629_ethsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/c= lk-mt7629-hif.c index 5d7ec861afab..c0583043710f 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -71,10 +71,12 @@ static const struct mtk_gate pcie_clks[] =3D { GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), }; =20 +static u16 rst_ofs[] =3D { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc =3D { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 1, - .reg_ofs =3D 0x34, + .rst_bank_ofs =3D rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(rst_ofs), }; =20 static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-m= t8135.c index 0ce26c6a8063..f975922cb99b 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -514,18 +514,21 @@ static const struct mtk_composite peri_clks[] __initc= onst =3D { MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), }; =20 +static u16 infrasys_rst_ofs[] =3D { 0x30, 0x34, }; +static u16 pericfg_rst_ofs[] =3D { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] =3D { /* infrasys */ { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 2, - .reg_ofs =3D 0x30, + .rst_bank_ofs =3D infrasys_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 2, - .reg_ofs =3D 0x0, + .rst_bank_ofs =3D pericfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), } }; =20 diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-m= t8173.c index 10c2d14dd8c9..b76eb3e5623e 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -819,18 +819,21 @@ static const struct mtk_gate venclt_clks[] __initcons= t =3D { GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4), }; =20 +static u16 infrasys_rst_ofs[] =3D { 0x30, 0x34, }; +static u16 pericfg_rst_ofs[] =3D { 0x0, 0x4, }; + static const struct mtk_clk_rst_desc clk_rst_desc[] =3D { /* infrasys */ { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 2, - .reg_ofs =3D 0x30, + .rst_bank_ofs =3D infrasys_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infrasys_rst_ofs), }, /* pericfg */ { .version =3D MTK_RST_SIMPLE, - .rst_bank_nr =3D 2, - .reg_ofs =3D 0x0, + .rst_bank_ofs =3D pericfg_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(pericfg_rst_ofs), } }; =20 diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index 000029a0559e..cc51fff7f3d9 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -20,6 +20,9 @@ =20 /* Infra global controller reset set register */ #define INFRA_RST0_SET_OFFSET 0x120 +#define INFRA_RST1_SET_OFFSET 0x130 +#define INFRA_RST2_SET_OFFSET 0x140 +#define INFRA_RST3_SET_OFFSET 0x150 =20 static DEFINE_SPINLOCK(mt8183_clk_lock); =20 @@ -1153,10 +1156,17 @@ static const struct mtk_pll_data plls[] =3D { 0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4), }; =20 +static u16 infra_rst_ofs[] =3D { + INFRA_RST0_SET_OFFSET, + INFRA_RST1_SET_OFFSET, + INFRA_RST2_SET_OFFSET, + INFRA_RST3_SET_OFFSET, +}; + static const struct mtk_clk_rst_desc clk_rst_desc =3D { .version =3D MTK_RST_SET_CLR, - .rst_bank_nr =3D 4, - .reg_ofs =3D INFRA_RST0_SET_OFFSET, + .rst_bank_ofs =3D infra_rst_ofs, + .rst_bank_nr =3D ARRAY_SIZE(infra_rst_ofs), }; =20 static int clk_mt8183_apmixed_probe(struct platform_device *pdev) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 47bc6b1842fd..11b2f74f121d 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -24,8 +24,8 @@ static int mtk_reset_update(struct reset_controller_dev *= rcdev, unsigned int val =3D deassert ? 0 : ~0; =20 return regmap_update_bits(data->regmap, - data->desc->reg_ofs + ((id / 32) << 2), - BIT(id % 32), val); + data->desc->rst_bank_ofs[id / RST_NR_PER_BANK], + BIT(id % RST_NR_PER_BANK), val); } =20 static int mtk_reset_assert(struct reset_controller_dev *rcdev, @@ -58,8 +58,9 @@ static int mtk_reset_update_set_clr(struct reset_controll= er_dev *rcdev, unsigned int deassert_ofs =3D deassert ? 0x4 : 0; =20 return regmap_write(data->regmap, - data->desc->reg_ofs + ((id / 32) << 4) + deassert_ofs, - BIT(id % 32)); + data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] + + deassert_ofs, + BIT(id % RST_NR_PER_BANK)); } =20 static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev, @@ -135,7 +136,7 @@ void mtk_register_reset_controller(struct device_node *= np, data->desc =3D desc; data->regmap =3D regmap; data->rcdev.owner =3D THIS_MODULE; - data->rcdev.nr_resets =3D desc->rst_bank_nr * 32; + data->rcdev.nr_resets =3D desc->rst_bank_nr * RST_NR_PER_BANK; data->rcdev.ops =3D rcops; data->rcdev.of_node =3D np; =20 diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index 91358e8cb851..482df8012c5c 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -9,6 +9,8 @@ #include #include =20 +#define RST_NR_PER_BANK 32 + /** * enum mtk_reset_version - Version of MediaTek clock reset controller. * @MTK_RST_SIMPLE: Use the same registers for bit set and clear. @@ -24,12 +26,12 @@ enum mtk_reset_version { /** * struct mtk_clk_rst_desc - Description of MediaTek clock reset. * @version: Reset version which is defined in enum mtk_reset_version. - * @reg_ofs: Base offset of the reset register. + * @rst_bank_ofs: Pointer to an array containing base offsets of the reset= register. * @rst_bank_nr: Quantity of reset bank. */ struct mtk_clk_rst_desc { u8 version; - u16 reg_ofs; + u16 *rst_bank_ofs; u32 rst_bank_nr; }; =20 --=20 2.18.0