From nobody Sun Sep 22 03:27:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EC3BC4332F for ; Thu, 19 May 2022 12:56:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238290AbiESMz5 (ORCPT ); Thu, 19 May 2022 08:55:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238219AbiESMzh (ORCPT ); Thu, 19 May 2022 08:55:37 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1365A7E3E; Thu, 19 May 2022 05:55:35 -0700 (PDT) X-UUID: acafba0125014a5f82f69495b6c3e7e7-20220519 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:899716f1-2ef7-4690-9b69-747491b599a4,OB:30,L OB:10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.5,REQID:899716f1-2ef7-4690-9b69-747491b599a4,OB:30,LOB :10,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:2a19b09,CLOUDID:3c90df79-5ef6-470b-96c9-bdb8ced32786,C OID:63ae97993cc8,Recheck:0,SF:28|17|19|48,TC:nil,Content:1,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: acafba0125014a5f82f69495b6c3e7e7-20220519 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2060391974; Thu, 19 May 2022 20:55:32 +0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 19 May 2022 20:55:31 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 May 2022 20:55:31 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 May 2022 20:55:30 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v7 16/19] arm64: dts: mediatek: Add infra #reset-cells property for MT8195 Date: Thu, 19 May 2022 20:55:24 +0800 Message-ID: <20220519125527.18544-17-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220519125527.18544-1-rex-bc.chen@mediatek.com> References: <20220519125527.18544-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We will use mediatek clock reset as infracfg_ao reset instead of ti-syscon. To support this, remove property of ti reset and add property of #reset-cells for mediatek clock reset. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index b57e620c2c72..8e5ac11b19f1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -10,7 +10,6 @@ #include #include #include -#include =20 / { compatible =3D "mediatek,mt8195"; @@ -295,17 +294,7 @@ compatible =3D "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; reg =3D <0 0x10001000 0 0x1000>; #clock-cells =3D <1>; - - infracfg_rst: reset-controller { - compatible =3D "ti,syscon-reset"; - #reset-cells =3D <1>; - ti,reset-bits =3D < - 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pc= ie */ - 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* th= ermal */ - 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* th= ermal */ - 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* sv= s gpu */ - >; - }; + #reset-cells =3D <1>; }; =20 pericfg: syscon@10003000 { --=20 2.18.0