From nobody Sun Sep 22 04:32:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6794BC47080 for ; Thu, 19 May 2022 12:56:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238553AbiESM40 (ORCPT ); Thu, 19 May 2022 08:56:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238235AbiESMzm (ORCPT ); Thu, 19 May 2022 08:55:42 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0F1BBA9B9; Thu, 19 May 2022 05:55:38 -0700 (PDT) X-UUID: 79472e3fdf334250ba65f973ae3862b2-20220519 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:64b77f1e-f33f-469d-9136-85d15bbecac1,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:f18fdf79-5ef6-470b-96c9-bdb8ced32786,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:0,BEC:nil X-UUID: 79472e3fdf334250ba65f973ae3862b2-20220519 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2025551149; Thu, 19 May 2022 20:55:30 +0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 19 May 2022 20:55:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 May 2022 20:55:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 May 2022 20:55:30 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v7 10/19] clk: mediatek: reset: Add new register reset function with device Date: Thu, 19 May 2022 20:55:18 +0800 Message-ID: <20220519125527.18544-11-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220519125527.18544-1-rex-bc.chen@mediatek.com> References: <20220519125527.18544-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Using device to register reset controller is a better implementation in current drivers. Howerver, some clock drviers of MediaTek only provide device_node. Therefore, we still remain the register reset function with device_node and add a new function with device to register reset controller. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt2701-eth.c | 2 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- drivers/clk/mediatek/clk-mt2701-hif.c | 2 +- drivers/clk/mediatek/clk-mt2701.c | 4 +- drivers/clk/mediatek/clk-mt2712.c | 4 +- drivers/clk/mediatek/clk-mt7622-eth.c | 2 +- drivers/clk/mediatek/clk-mt7622-hif.c | 4 +- drivers/clk/mediatek/clk-mt7622.c | 4 +- drivers/clk/mediatek/clk-mt7629-eth.c | 2 +- drivers/clk/mediatek/clk-mt7629-hif.c | 4 +- drivers/clk/mediatek/clk-mt8183.c | 2 +- drivers/clk/mediatek/reset.c | 60 +++++++++++++++++++++++++++ drivers/clk/mediatek/reset.h | 10 +++++ 13 files changed, 86 insertions(+), 16 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/c= lk-mt2701-eth.c index b4e7f38860d0..edf1e2ed2b59 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -66,7 +66,7 @@ static int clk_mt2701_eth_probe(struct platform_device *p= dev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/c= lk-mt2701-g3d.c index 5cbc5c42204d..c1f7d8e30b6a 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -60,7 +60,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device = *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/c= lk-mt2701-hif.c index 60bda56a102c..434cbbe8c037 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -65,7 +65,7 @@ static int clk_mt2701_hif_probe(struct platform_device *p= dev) return r; } =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return 0; } diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-m= t2701.c index 413c9d8dd752..b4bd0af1d3cf 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -805,7 +805,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) if (r) return r; =20 - mtk_register_reset_controller(node, &clk_rst_desc[0]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); =20 return 0; } @@ -928,7 +928,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) if (r) return r; =20 - mtk_register_reset_controller(node, &clk_rst_desc[1]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); =20 return 0; } diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-m= t2712.c index fcb4bef974d9..c09a97908c62 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1379,7 +1379,7 @@ static int clk_mt2712_infra_probe(struct platform_dev= ice *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc[0]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); =20 return r; } @@ -1401,7 +1401,7 @@ static int clk_mt2712_peri_probe(struct platform_devi= ce *pdev) pr_err("%s(): could not register clock provider: %d\n", __func__, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc[1]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/c= lk-mt7622-eth.c index 90d55f882215..43de0477d5d9 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -90,7 +90,7 @@ static int clk_mt7622_ethsys_init(struct platform_device = *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/c= lk-mt7622-hif.c index 489b64725b22..67e96231dd25 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -101,7 +101,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_dev= ice *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } @@ -123,7 +123,7 @@ static int clk_mt7622_pciesys_init(struct platform_devi= ce *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-m= t7622.c index 6df709ca2860..31da74e1830e 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -681,7 +681,7 @@ static int mtk_infrasys_init(struct platform_device *pd= ev) if (r) return r; =20 - mtk_register_reset_controller(node, &clk_rst_desc[0]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); =20 return 0; } @@ -732,7 +732,7 @@ static int mtk_pericfg_init(struct platform_device *pde= v) =20 clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk); =20 - mtk_register_reset_controller(node, &clk_rst_desc[1]); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); =20 return 0; } diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/c= lk-mt7629-eth.c index 11b346c9d916..282dd6559465 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -100,7 +100,7 @@ static int clk_mt7629_ethsys_init(struct platform_devic= e *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/c= lk-mt7629-hif.c index c0583043710f..0c8b9e139789 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -96,7 +96,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_devic= e *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } @@ -118,7 +118,7 @@ static int clk_mt7629_pciesys_init(struct platform_devi= ce *pdev) "could not register clock provider: %s: %d\n", pdev->name, r); =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-m= t8183.c index cc51fff7f3d9..b5e90a0f700c 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1256,7 +1256,7 @@ static int clk_mt8183_infra_probe(struct platform_dev= ice *pdev) return r; } =20 - mtk_register_reset_controller(node, &clk_rst_desc); + mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); =20 return r; } diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index b9718f0f9d16..179505549a7c 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -169,4 +169,64 @@ int mtk_register_reset_controller(struct device_node *= np, return 0; } =20 +int mtk_register_reset_controller_with_dev(struct device *dev, + const struct mtk_clk_rst_desc *desc) +{ + struct device_node *np =3D dev->of_node; + struct regmap *regmap; + const struct reset_control_ops *rcops =3D NULL; + struct mtk_clk_rst_data *data; + int ret; + + if (!desc) { + dev_err(dev, "mtk clock reset desc is NULL\n"); + return -EINVAL; + } + + switch (desc->version) { + case MTK_RST_SIMPLE: + rcops =3D &mtk_reset_ops; + break; + case MTK_RST_SET_CLR: + rcops =3D &mtk_reset_ops_set_clr; + break; + default: + dev_err(dev, "Unknown reset version %d\n", desc->version); + return -EINVAL; + } + + regmap =3D device_node_to_regmap(np); + if (IS_ERR(regmap)) { + dev_err(dev, "Cannot find regmap %pe\n", regmap); + return -EINVAL; + } + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->desc =3D desc; + data->regmap =3D regmap; + data->rcdev.owner =3D THIS_MODULE; + data->rcdev.ops =3D rcops; + data->rcdev.of_node =3D np; + data->rcdev.dev =3D dev; + + if (data->desc->rst_idx_map_nr > 0) { + data->rcdev.of_reset_n_cells =3D 1; + data->rcdev.nr_resets =3D desc->rst_idx_map_nr; + data->rcdev.of_xlate =3D reset_xlate; + } else { + data->rcdev.nr_resets =3D desc->rst_bank_nr * RST_NR_PER_BANK; + } + + ret =3D devm_reset_controller_register(dev, &data->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller: %d\n", ret); + return ret; + } + + return 0; +} + MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h index cc67934c69e2..34772ef74ec7 100644 --- a/drivers/clk/mediatek/reset.h +++ b/drivers/clk/mediatek/reset.h @@ -62,4 +62,14 @@ struct mtk_clk_rst_data { int mtk_register_reset_controller(struct device_node *np, const struct mtk_clk_rst_desc *desc); =20 +/** + * mtk_register_reset_controller - Register mediatek clock reset controlle= r with device + * @np: Pointer to device. + * @desc: Constant pointer to description of clock reset. + * + * Return: 0 on success and errorno otherwise. + */ +int mtk_register_reset_controller_with_dev(struct device *dev, + const struct mtk_clk_rst_desc *desc); + #endif /* __DRV_CLK_MTK_RESET_H */ --=20 2.18.0