From nobody Sun Sep 22 04:41:17 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 485ABC433F5 for ; Thu, 19 May 2022 11:13:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237320AbiESLNm (ORCPT ); Thu, 19 May 2022 07:13:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232763AbiESLNi (ORCPT ); Thu, 19 May 2022 07:13:38 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84B64939DE; Thu, 19 May 2022 04:13:33 -0700 (PDT) X-UUID: f906369b7a5249bcb47ddf82c20c2f30-20220519 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:63248947-df7e-4f9f-a162-28f486a8d83d,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:90 X-CID-INFO: VERSION:1.1.5,REQID:63248947-df7e-4f9f-a162-28f486a8d83d,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:90 X-CID-META: VersionHash:2a19b09,CLOUDID:e864dd79-5ef6-470b-96c9-bdb8ced32786,C OID:8a55a99be6e7,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: f906369b7a5249bcb47ddf82c20c2f30-20220519 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 118451; Thu, 19 May 2022 19:13:29 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 19 May 2022 19:13:28 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 May 2022 19:13:27 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 May 2022 19:13:26 +0800 From: Axe Yang To: Ulf Hansson , Rob Herring , Chaotian Jing , Matthias Brugger , Adrian Hunter CC: Yoshihiro Shimoda , Satya Tangirala , Andy Shevchenko , Wolfram Sang , Axe Yang , Lucas Stach , Eric Biggers , Andrew Jeffery , Stephen Boyd , Kiwoong Kim , Yue Hu , Tian Tao , , , , , , , Subject: [PATCH v10 1/3] dt-bindings: mmc: mtk-sd: extend interrupts and pinctrls properties Date: Thu, 19 May 2022 19:13:21 +0800 Message-ID: <20220519111323.14586-2-axe.yang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220519111323.14586-1-axe.yang@mediatek.com> References: <20220519111323.14586-1-axe.yang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Extend interrupts and pinctrls for SDIO wakeup interrupt feature. This feature allow SDIO devices alarm asynchronous interrupt to host even when host stop providing clock to SDIO card. An extra wakeup interrupt and pinctrl states for SDIO DAT1 pin state switching are required in this scenario. Signed-off-by: Axe Yang --- .../devicetree/bindings/mmc/mtk-sd.yaml | 53 ++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentat= ion/devicetree/bindings/mmc/mtk-sd.yaml index 2a2e9fa8c188..b068ab67a054 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -72,12 +72,26 @@ properties: - const: ahb_cg =20 interrupts: - maxItems: 1 + description: + Should at least contain MSDC GIC interrupt. To support SDIO in-band = wakeup, an extended + interrupt is required and be configured as wakeup source irq. + minItems: 1 + maxItems: 2 + + interrupt-names: + items: + - const: msdc_irq =20 pinctrl-names: + description: + Should at least contain default and state_uhs. To support SDIO in-ba= nd wakeup, dat1 pin + will be switched between GPIO mode and SDIO DAT1 mode, state_eint an= d state_dat1 are + mandatory in this scenarios. + minItems: 2 items: - const: default - const: state_uhs + - const: state_eint =20 pinctrl-0: description: @@ -89,6 +103,11 @@ properties: should contain uhs mode pin ctrl. maxItems: 1 =20 + pinctrl-2: + description: + should switch dat1 pin to GPIO mode. + maxItems: 1 + assigned-clocks: description: PLL of the source clock. @@ -208,4 +227,36 @@ examples: mediatek,hs400-cmd-resp-sel-rising; }; =20 + mmc2: mmc@11250000 { + compatible =3D "mediatek,mt8195-mmc"; + reg =3D <0x11250000 0x1000>, + <0x11e60000 0x1000>; + clock-names =3D "source", "hclk", "source_cg"; + clocks =3D <&topckgen CLK_TOP_MSDC30_2_SEL>, + <&infracfg_ao CLK_INFRA_AO_MSDC2>, + <&infracfg_ao CLK_INFRA_AO_MSDC30_2>; + interrupt-names =3D "msdc_irq", "sdio_wakeup_irq"; + interrupts =3D <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 172 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default", "state_uhs", "state_eint"; + pinctrl-0 =3D <&mmc2_pins_default>; + pinctrl-1 =3D <&mmc2_pins_uhs>; + pinctrl-2 =3D <&mmc2_pins_eint>; + assigned-clocks =3D <&topckgen CLK_TOP_MSDC30_2_SEL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MSDCPLL_D2>; + bus-width =3D <4>; + max-frequency =3D <200000000>; + cap-sd-highspeed; + sd-uhs-sdr104; + keep-power-in-suspend; + wakeup-source; + cap-sdio-irq; + no-mmc; + no-sd; + non-removable; + vmmc-supply =3D <&sdio_fixed_3v3>; + vqmmc-supply =3D <&sdio_fixed_1v8>; + mmc-pwrseq =3D <&wifi_pwrseq>; + }; + ... --=20 2.25.1