From nobody Sun Sep 22 04:50:42 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80DE8C433EF for ; Thu, 19 May 2022 06:10:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234350AbiESGKH (ORCPT ); Thu, 19 May 2022 02:10:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234351AbiESGJy (ORCPT ); Thu, 19 May 2022 02:09:54 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D86AB819B8; Wed, 18 May 2022 23:09:52 -0700 (PDT) X-UUID: 9ba28cab7c924802835b32dfd15a037b-20220519 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:6d510757-2d8c-4851-a206-8bb9821fef8c,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:1de5d079-5ef6-470b-96c9-bdb8ced32786,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 9ba28cab7c924802835b32dfd15a037b-20220519 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 221176302; Thu, 19 May 2022 14:09:50 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 19 May 2022 14:09:49 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 May 2022 14:09:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 May 2022 14:09:48 +0800 From: Tim Chang To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Roger Lu , Kevin Hilman , Jia-Wei Chang CC: , , , , , , AngeloGioacchino Del Regno Subject: [PATCH v2 4/4] soc: mediatek: svs: add support for mt8195 Date: Thu, 19 May 2022 14:09:24 +0800 Message-ID: <20220519060924.13493-5-jia-wei.chang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220519060924.13493-1-jia-wei.chang@mediatek.com> References: <20220519060924.13493-1-jia-wei.chang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jia-Wei Chang To support svs on MT8195, add corresponding bank information, platform data, probe and parsing function. Signed-off-by: Jia-Wei Chang --- drivers/soc/mediatek/mtk-svs.c | 193 +++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 656d0361ff7d..919226faee6d 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1680,6 +1680,92 @@ static int svs_bank_resource_setup(struct svs_platfo= rm *svsp) return 0; } =20 +static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + struct nvmem_cell *cell; + u32 idx, i, ft_pgm, vmin, golden_temp; + + for (i =3D 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[10]) { + dev_notice(svsp->dev, "svs_efuse[10] =3D 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + ft_pgm =3D svsp->efuse[0] & GENMASK(7, 0); + vmin =3D (svsp->efuse[19] >> 4) & GENMASK(1, 0); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + + if (svsb->sw_id !=3D SVSB_GPU) + return false; + + if (vmin =3D=3D 0x1) + svsb->vmin =3D 0x1e; + + if (ft_pgm =3D=3D 0) + svsb->volt_flags |=3D SVSB_INIT01_VOLT_IGNORE; + + if (svsb->type =3D=3D SVSB_LOW) { + svsb->mtdes =3D svsp->efuse[10] & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[10] >> 16) & GENMASK(7, 0); + svsb->mdes =3D (svsp->efuse[10] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } else if (svsb->type =3D=3D SVSB_HIGH) { + svsb->mtdes =3D svsp->efuse[9] & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[9] >> 16) & GENMASK(7, 0); + svsb->mdes =3D (svsp->efuse[9] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } + + svsb->vmax +=3D svsb->dvt_fixed; + } + + /* Thermal efuse parsing */ + cell =3D nvmem_cell_get(svsp->dev, "t-calibration-data"); + if (IS_ERR_OR_NULL(cell)) { + dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", + PTR_ERR(cell)); + return false; + } + + svsp->tefuse =3D nvmem_cell_read(cell, &svsp->tefuse_max); + if (IS_ERR(svsp->tefuse)) { + dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", + PTR_ERR(svsp->tefuse)); + nvmem_cell_put(cell); + return false; + } + + svsp->tefuse_max /=3D sizeof(u32); + nvmem_cell_put(cell); + + for (i =3D 0; i < svsp->tefuse_max; i++) + if (svsp->tefuse[i] !=3D 0) + break; + + if (i =3D=3D svsp->tefuse_max) + golden_temp =3D 50; /* All thermal efuse data are 0 */ + else + golden_temp =3D (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + svsb->mts =3D 500; + svsb->bts =3D (((500 * golden_temp + 250460) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2141,6 +2227,39 @@ static struct device *svs_add_device_link(struct svs= _platform *svsp, return dev; } =20 +static int svs_mt8195_platform_probe(struct svs_platform *svsp) +{ + struct device *dev; + struct svs_bank *svsb; + u32 idx; + + svsp->rst =3D devm_reset_control_get_optional(svsp->dev, "svs_rst"); + if (IS_ERR(svsp->rst)) + return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), + "cannot get svs reset control\n"); + + dev =3D svs_add_device_link(svsp, "lvts"); + if (IS_ERR(dev)) + return dev_err_probe(svsp->dev, PTR_ERR(dev), + "failed to get lvts device\n"); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + + if (svsb->type =3D=3D SVSB_HIGH) + svsb->opp_dev =3D svs_add_device_link(svsp, "mali"); + else if (svsb->type =3D=3D SVSB_LOW) + svsb->opp_dev =3D svs_get_subsys_device(svsp, "mali"); + + if (IS_ERR(svsb->opp_dev)) + return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), + "failed to get OPP device for bank %d\n", + idx); + } + + return 0; +} + static int svs_mt8192_platform_probe(struct svs_platform *svsp) { struct device *dev; @@ -2257,6 +2376,67 @@ static int svs_mt8183_platform_probe(struct svs_plat= form *svsp) return 0; } =20 +static struct svs_bank svs_mt8195_banks[] =3D { + { + .sw_id =3D SVSB_GPU, + .type =3D SVSB_LOW, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .tzone_name =3D "gpu1", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support =3D SVSB_MODE_INIT02, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 640000000, + .turn_freq_base =3D 640000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x38, + .vmin =3D 0x14, + .age_config =3D 0x555555, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x1, + .vco =3D 0x18, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0100, + .int_st =3D BIT(0), + .ctl0 =3D 0x00540003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 0, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 7, + }, + { + .sw_id =3D SVSB_GPU, + .type =3D SVSB_HIGH, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .tzone_name =3D "gpu1", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 880000000, + .turn_freq_base =3D 640000000, + .vboot =3D 0x38, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x38, + .vmin =3D 0x14, + .age_config =3D 0x555555, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x6, + .vco =3D 0x18, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0101, + .int_st =3D BIT(1), + .ctl0 =3D 0x00540003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 0, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 7, + }, +}; + static struct svs_bank svs_mt8192_banks[] =3D { { .sw_id =3D SVSB_GPU, @@ -2559,6 +2739,16 @@ static struct svs_bank svs_mt8183_banks[] =3D { }, }; =20 +static const struct svs_platform_data svs_mt8195_platform_data =3D { + .name =3D "mt8195-svs", + .banks =3D svs_mt8195_banks, + .efuse_parsing =3D svs_mt8195_efuse_parsing, + .probe =3D svs_mt8195_platform_probe, + .irqflags =3D IRQF_TRIGGER_HIGH, + .regs =3D svs_regs_v2, + .bank_max =3D ARRAY_SIZE(svs_mt8195_banks), +}; + static const struct svs_platform_data svs_mt8192_platform_data =3D { .name =3D "mt8192-svs", .banks =3D svs_mt8192_banks, @@ -2591,6 +2781,9 @@ static const struct svs_platform_data svs_mt8183_plat= form_data =3D { =20 static const struct of_device_id svs_of_match[] =3D { { + .compatible =3D "mediatek,mt8195-svs", + .data =3D &svs_mt8195_platform_data, + }, { .compatible =3D "mediatek,mt8192-svs", .data =3D &svs_mt8192_platform_data, }, { --=20 2.18.0