From nobody Sun Sep 22 01:47:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA879C433F5 for ; Thu, 19 May 2022 06:09:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234342AbiESGJt (ORCPT ); Thu, 19 May 2022 02:09:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233809AbiESGJp (ORCPT ); Thu, 19 May 2022 02:09:45 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4719819AA; Wed, 18 May 2022 23:09:43 -0700 (PDT) X-UUID: b037002723354aa3b0ccebee42b8cbdd-20220519 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:effee4cc-656d-4a2c-8f5f-1fb2d7799f6d,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:5 X-CID-META: VersionHash:2a19b09,CLOUDID:b8d1c0e2-edbf-4bd4-8a34-dfc5f7bb086d,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:0,BEC:nil X-UUID: b037002723354aa3b0ccebee42b8cbdd-20220519 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 289844685; Thu, 19 May 2022 14:09:37 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 19 May 2022 14:09:35 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 May 2022 14:09:35 +0800 From: Tim Chang To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Roger Lu , Kevin Hilman , Jia-Wei Chang CC: , , , , , , AngeloGioacchino Del Regno Subject: [PATCH v2 1/4] dt-bindings: soc: mediatek: add mt8186 svs dt-bindings Date: Thu, 19 May 2022 14:09:21 +0800 Message-ID: <20220519060924.13493-2-jia-wei.chang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220519060924.13493-1-jia-wei.chang@mediatek.com> References: <20220519060924.13493-1-jia-wei.chang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jia-Wei Chang Add mt8186 svs compatible in dt-bindings and add myself as a co-maintainer. Signed-off-by: Jia-Wei Chang Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/= Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml index d911fa2d40ef..c86a5430641f 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -10,6 +10,7 @@ maintainers: - Roger Lu - Matthias Brugger - Kevin Hilman + - Jia-Wei Chang =20 description: |+ The SVS engine is a piece of hardware which has several @@ -22,6 +23,7 @@ properties: compatible: enum: - mediatek,mt8183-svs + - mediatek,mt8186-svs - mediatek,mt8192-svs =20 reg: --=20 2.18.0 From nobody Sun Sep 22 01:47:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98A36C433F5 for ; Thu, 19 May 2022 06:09:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234347AbiESGJw (ORCPT ); Thu, 19 May 2022 02:09:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234327AbiESGJr (ORCPT ); Thu, 19 May 2022 02:09:47 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13BCC819AE; Wed, 18 May 2022 23:09:44 -0700 (PDT) X-UUID: 2330a0af9a97487b80b8a587d53ee866-20220519 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:6a5eb0ec-9c92-4e6b-aa87-351b2763d63c,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:bdd2c0e2-edbf-4bd4-8a34-dfc5f7bb086d,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 2330a0af9a97487b80b8a587d53ee866-20220519 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 820952658; Thu, 19 May 2022 14:09:41 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 19 May 2022 14:09:40 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 May 2022 14:09:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 May 2022 14:09:39 +0800 From: Tim Chang To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Roger Lu , Kevin Hilman , Jia-Wei Chang CC: , , , , , , AngeloGioacchino Del Regno Subject: [PATCH v2 2/4] soc: mediatek: svs: add support for mt8186 Date: Thu, 19 May 2022 14:09:22 +0800 Message-ID: <20220519060924.13493-3-jia-wei.chang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220519060924.13493-1-jia-wei.chang@mediatek.com> References: <20220519060924.13493-1-jia-wei.chang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jia-Wei Chang MT8186 svs has a number of banks which used as optimization of opp voltage table for corresponding dvfs drivers. MT8186 svs big core uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Jia-Wei Chang Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 351 ++++++++++++++++++++++++++++++++- 1 file changed, 344 insertions(+), 7 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 606a00a2e57d..656d0361ff7d 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -355,6 +355,7 @@ struct svs_platform_data { * @dcbdet: svs efuse data * @dcmdet: svs efuse data * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low= bank + * @vbin_turn_pt: voltage bin turn point helps know which svsb_volt should= be overridden * @type: bank type to represent it is 2-line (high/low) bank or 1-line ba= nk * * Svs bank will generate suitalbe voltages by below general math equation @@ -417,6 +418,7 @@ struct svs_bank { u32 dcbdet; u32 dcmdet; u32 turn_pt; + u32 vbin_turn_pt; u32 type; }; =20 @@ -692,11 +694,12 @@ static int svs_status_debug_show(struct seq_file *m, = void *v) =20 ret =3D thermal_zone_get_temp(svsb->tzd, &tzone_temp); if (ret) - seq_printf(m, "%s: temperature ignore, turn_pt =3D %u\n", - svsb->name, svsb->turn_pt); + seq_printf(m, "%s: temperature ignore, vbin_turn_pt =3D %u, turn_pt =3D = %u\n", + svsb->name, svsb->vbin_turn_pt, svsb->turn_pt); else - seq_printf(m, "%s: temperature =3D %d, turn_pt =3D %u\n", - svsb->name, tzone_temp, svsb->turn_pt); + seq_printf(m, "%s: temperature =3D %d, vbin_turn_pt =3D %u, turn_pt =3D = %u\n", + svsb->name, tzone_temp, svsb->vbin_turn_pt, + svsb->turn_pt); =20 for (i =3D 0; i < svsb->opp_count; i++) { opp =3D dev_pm_opp_find_freq_exact(svsb->opp_dev, @@ -889,9 +892,11 @@ static void svs_get_bank_volts_v3(struct svs_platform = *svsp) opp_stop =3D svsb->opp_count; } =20 - for (i =3D opp_start; i < opp_stop; i++) + for (i =3D opp_start; i < opp_stop; i++) { if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) svsb->volt[i] -=3D svsb->dvt_fixed; + svsb->volt[i] +=3D svsb->volt_od; + } } =20 static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp) @@ -982,6 +987,10 @@ static void svs_get_bank_volts_v2(struct svs_platform = *svsp) struct svs_bank *svsb =3D svsp->pbank; u32 temp, i; =20 + if (svsb->phase =3D=3D SVSB_PHASE_MON && + svsb->volt_flags & SVSB_MON_VOLT_IGNORE) + return; + temp =3D svs_readl_relaxed(svsp, VOP74); svsb->volt[14] =3D (temp >> 24) & GENMASK(7, 0); svsb->volt[12] =3D (temp >> 16) & GENMASK(7, 0); @@ -1007,8 +1016,34 @@ static void svs_get_bank_volts_v2(struct svs_platfor= m *svsp) svsb->volt[14], svsb->freq_pct[15]); =20 - for (i =3D 0; i < svsb->opp_count; i++) + for (i =3D 0; i < svsb->opp_count; i++) { + if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT) + svsb->volt[i] -=3D svsb->dvt_fixed; svsb->volt[i] +=3D svsb->volt_od; + } + + /* For voltage bin support */ + if (svsb->opp_dfreq[0] > svsb->freq_base) { + svsb->volt[0] =3D svs_opp_volt_to_bank_volt(svsb->opp_dvolt[0], + svsb->volt_step, + svsb->volt_base); + + /* Find voltage bin turn point */ + for (i =3D 0; i < svsb->opp_count; i++) { + if (svsb->opp_dfreq[i] <=3D svsb->freq_base) { + svsb->vbin_turn_pt =3D i; + break; + } + } + + /* Override svs bank voltages */ + for (i =3D 1; i < svsb->vbin_turn_pt; i++) + svsb->volt[i] =3D interpolate(svsb->freq_pct[0], + svsb->freq_pct[svsb->vbin_turn_pt], + svsb->volt[0], + svsb->volt[svsb->vbin_turn_pt], + svsb->freq_pct[i]); + } } =20 static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp) @@ -1556,7 +1591,12 @@ static int svs_bank_resource_setup(struct svs_platfo= rm *svsp) svsb->name =3D "SVSB_CPU_LITTLE"; break; case SVSB_CPU_BIG: - svsb->name =3D "SVSB_CPU_BIG"; + if (svsb->type =3D=3D SVSB_HIGH) + svsb->name =3D "SVSB_CPU_BIG_HIGH"; + else if (svsb->type =3D=3D SVSB_LOW) + svsb->name =3D "SVSB_CPU_BIG_LOW"; + else + svsb->name =3D "SVSB_CPU_BIG"; break; case SVSB_CCI: svsb->name =3D "SVSB_CCI"; @@ -1719,6 +1759,103 @@ static bool svs_mt8192_efuse_parsing(struct svs_pla= tform *svsp) return true; } =20 +static bool svs_mt8186_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + struct nvmem_cell *cell; + u32 idx, i, golden_temp; + + for (i =3D 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[0]) { + dev_notice(svsp->dev, "svs_efuse[0] =3D 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + + switch (svsb->sw_id) { + case SVSB_CPU_BIG: + if (svsb->type =3D=3D SVSB_HIGH) { + svsb->mdes =3D (svsp->efuse[2] >> 24) & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[2] >> 16) & GENMASK(7, 0); + svsb->mtdes =3D svsp->efuse[2] & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[13] >> 8) & GENMASK(7, 0); + svsb->dcbdet =3D svsp->efuse[13] & GENMASK(7, 0); + } else if (svsb->type =3D=3D SVSB_LOW) { + svsb->mdes =3D (svsp->efuse[3] >> 24) & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[3] >> 16) & GENMASK(7, 0); + svsb->mtdes =3D svsp->efuse[3] & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[14] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[14] >> 16) & GENMASK(7, 0); + } + break; + case SVSB_CPU_LITTLE: + svsb->mdes =3D (svsp->efuse[4] >> 24) & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[4] >> 16) & GENMASK(7, 0); + svsb->mtdes =3D svsp->efuse[4] & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[14] >> 8) & GENMASK(7, 0); + svsb->dcbdet =3D svsp->efuse[14] & GENMASK(7, 0); + break; + case SVSB_CCI: + svsb->mdes =3D (svsp->efuse[5] >> 24) & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[5] >> 16) & GENMASK(7, 0); + svsb->mtdes =3D svsp->efuse[5] & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[15] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[15] >> 16) & GENMASK(7, 0); + break; + case SVSB_GPU: + svsb->mdes =3D (svsp->efuse[6] >> 24) & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[6] >> 16) & GENMASK(7, 0); + svsb->mtdes =3D svsp->efuse[6] & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[15] >> 8) & GENMASK(7, 0); + svsb->dcbdet =3D svsp->efuse[15] & GENMASK(7, 0); + break; + default: + dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + return false; + } + + svsb->vmax +=3D svsb->dvt_fixed; + } + + /* Thermal efuse parsing */ + cell =3D nvmem_cell_get(svsp->dev, "t-calibration-data"); + if (IS_ERR_OR_NULL(cell)) { + dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", + PTR_ERR(cell)); + return false; + } + + svsp->tefuse =3D nvmem_cell_read(cell, &svsp->tefuse_max); + if (IS_ERR(svsp->tefuse)) { + dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", + PTR_ERR(svsp->tefuse)); + nvmem_cell_put(cell); + return false; + } + + svsp->tefuse_max /=3D sizeof(u32); + nvmem_cell_put(cell); + + golden_temp =3D (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + if (!golden_temp) + golden_temp =3D 50; + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + svsb->mts =3D 409; + svsb->bts =3D (((500 * golden_temp + 204650) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2037,6 +2174,50 @@ static int svs_mt8192_platform_probe(struct svs_plat= form *svsp) return 0; } =20 +static int svs_mt8186_platform_probe(struct svs_platform *svsp) +{ + struct device *dev; + struct svs_bank *svsb; + u32 idx; + + svsp->rst =3D devm_reset_control_get_optional(svsp->dev, "svs_rst"); + if (IS_ERR(svsp->rst)) + return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), + "cannot get svs reset control\n"); + + dev =3D svs_add_device_link(svsp, "lvts"); + if (IS_ERR(dev)) + return dev_err_probe(svsp->dev, PTR_ERR(dev), + "failed to get lvts device\n"); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + + switch (svsb->sw_id) { + case SVSB_CPU_LITTLE: + case SVSB_CPU_BIG: + svsb->opp_dev =3D get_cpu_device(svsb->cpu_id); + break; + case SVSB_CCI: + svsb->opp_dev =3D svs_add_device_link(svsp, "cci"); + break; + case SVSB_GPU: + svsb->opp_dev =3D svs_add_device_link(svsp, "mali"); + break; + default: + dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id); + return -EINVAL; + } + + if (IS_ERR(svsb->opp_dev)) + return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), + "failed to get OPP device for bank %d\n", + idx); + } + + return 0; +} + static int svs_mt8183_platform_probe(struct svs_platform *svsp) { struct device *dev; @@ -2131,6 +2312,149 @@ static struct svs_bank svs_mt8192_banks[] =3D { }, }; =20 +static struct svs_bank svs_mt8186_banks[] =3D { + { + .sw_id =3D SVSB_CPU_BIG, + .type =3D SVSB_LOW, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .cpu_id =3D 6, + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support =3D SVSB_MODE_INIT02, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 1670000000, + .turn_freq_base =3D 1670000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .volt_od =3D 4, + .vmax =3D 0x59, + .vmin =3D 0x20, + .age_config =3D 0x1, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x3, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0100, + .int_st =3D BIT(0), + .ctl0 =3D 0x00540003, + }, + { + .sw_id =3D SVSB_CPU_BIG, + .type =3D SVSB_HIGH, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .cpu_id =3D 6, + .tzone_name =3D "cpu_big0", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 2050000000, + .turn_freq_base =3D 1670000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .volt_od =3D 4, + .vmax =3D 0x73, + .vmin =3D 0x20, + .age_config =3D 0x1, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x6, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0101, + .int_st =3D BIT(1), + .ctl0 =3D 0x00540003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 8, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 8, + }, + { + .sw_id =3D SVSB_CPU_LITTLE, + .set_freq_pct =3D svs_set_bank_freq_pct_v2, + .get_volts =3D svs_get_bank_volts_v2, + .cpu_id =3D 0, + .tzone_name =3D "cpu_zone0", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 2000000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .volt_od =3D 3, + .vmax =3D 0x65, + .vmin =3D 0x20, + .age_config =3D 0x1, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x6, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0102, + .int_st =3D BIT(2), + .ctl0 =3D 0x3210000f, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 8, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 8, + }, + { + .sw_id =3D SVSB_CCI, + .set_freq_pct =3D svs_set_bank_freq_pct_v2, + .get_volts =3D svs_get_bank_volts_v2, + .tzone_name =3D "cpu_zone0", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 1400000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .volt_od =3D 3, + .vmax =3D 0x65, + .vmin =3D 0x20, + .age_config =3D 0x1, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x6, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0103, + .int_st =3D BIT(3), + .ctl0 =3D 0x3210000f, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 8, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 8, + }, + { + .sw_id =3D SVSB_GPU, + .set_freq_pct =3D svs_set_bank_freq_pct_v2, + .get_volts =3D svs_get_bank_volts_v2, + .tzone_name =3D "mfg", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 850000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x58, + .vmin =3D 0x20, + .age_config =3D 0x555555, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x4, + .vco =3D 0x10, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0104, + .int_st =3D BIT(4), + .ctl0 =3D 0x00100003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 8, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 7, + }, +}; + static struct svs_bank svs_mt8183_banks[] =3D { { .sw_id =3D SVSB_CPU_LITTLE, @@ -2245,6 +2569,16 @@ static const struct svs_platform_data svs_mt8192_pla= tform_data =3D { .bank_max =3D ARRAY_SIZE(svs_mt8192_banks), }; =20 +static const struct svs_platform_data svs_mt8186_platform_data =3D { + .name =3D "mt8186-svs", + .banks =3D svs_mt8186_banks, + .efuse_parsing =3D svs_mt8186_efuse_parsing, + .probe =3D svs_mt8186_platform_probe, + .irqflags =3D IRQF_TRIGGER_HIGH, + .regs =3D svs_regs_v2, + .bank_max =3D ARRAY_SIZE(svs_mt8186_banks), +}; + static const struct svs_platform_data svs_mt8183_platform_data =3D { .name =3D "mt8183-svs", .banks =3D svs_mt8183_banks, @@ -2259,6 +2593,9 @@ static const struct of_device_id svs_of_match[] =3D { { .compatible =3D "mediatek,mt8192-svs", .data =3D &svs_mt8192_platform_data, + }, { + .compatible =3D "mediatek,mt8186-svs", + .data =3D &svs_mt8186_platform_data, }, { .compatible =3D "mediatek,mt8183-svs", .data =3D &svs_mt8183_platform_data, --=20 2.18.0 From nobody Sun Sep 22 01:47:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E606EC433EF for ; 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Thu, 19 May 2022 14:09:45 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 19 May 2022 14:09:44 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 May 2022 14:09:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 May 2022 14:09:44 +0800 From: Tim Chang To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Roger Lu , Kevin Hilman , Jia-Wei Chang CC: , , , , , , AngeloGioacchino Del Regno Subject: [PATCH v2 3/4] dt-bindings: soc: mediatek: add mt8195 svs dt-bindings Date: Thu, 19 May 2022 14:09:23 +0800 Message-ID: <20220519060924.13493-4-jia-wei.chang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220519060924.13493-1-jia-wei.chang@mediatek.com> References: <20220519060924.13493-1-jia-wei.chang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jia-Wei Chang Add mt8195 svs compatible in dt-bindings. Signed-off-by: Jia-Wei Chang Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/= Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml index c86a5430641f..4bf26a333373 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt8183-svs - mediatek,mt8186-svs - mediatek,mt8192-svs + - mediatek,mt8195-svs =20 reg: maxItems: 1 --=20 2.18.0 From nobody Sun Sep 22 01:47:25 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80DE8C433EF for ; Thu, 19 May 2022 06:10:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234350AbiESGKH (ORCPT ); Thu, 19 May 2022 02:10:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234351AbiESGJy (ORCPT ); Thu, 19 May 2022 02:09:54 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D86AB819B8; Wed, 18 May 2022 23:09:52 -0700 (PDT) X-UUID: 9ba28cab7c924802835b32dfd15a037b-20220519 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:6d510757-2d8c-4851-a206-8bb9821fef8c,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:2a19b09,CLOUDID:1de5d079-5ef6-470b-96c9-bdb8ced32786,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 9ba28cab7c924802835b32dfd15a037b-20220519 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 221176302; Thu, 19 May 2022 14:09:50 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Thu, 19 May 2022 14:09:49 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 May 2022 14:09:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 19 May 2022 14:09:48 +0800 From: Tim Chang To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Philipp Zabel , Roger Lu , Kevin Hilman , Jia-Wei Chang CC: , , , , , , AngeloGioacchino Del Regno Subject: [PATCH v2 4/4] soc: mediatek: svs: add support for mt8195 Date: Thu, 19 May 2022 14:09:24 +0800 Message-ID: <20220519060924.13493-5-jia-wei.chang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220519060924.13493-1-jia-wei.chang@mediatek.com> References: <20220519060924.13493-1-jia-wei.chang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jia-Wei Chang To support svs on MT8195, add corresponding bank information, platform data, probe and parsing function. Signed-off-by: Jia-Wei Chang --- drivers/soc/mediatek/mtk-svs.c | 193 +++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 656d0361ff7d..919226faee6d 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1680,6 +1680,92 @@ static int svs_bank_resource_setup(struct svs_platfo= rm *svsp) return 0; } =20 +static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + struct nvmem_cell *cell; + u32 idx, i, ft_pgm, vmin, golden_temp; + + for (i =3D 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[10]) { + dev_notice(svsp->dev, "svs_efuse[10] =3D 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + ft_pgm =3D svsp->efuse[0] & GENMASK(7, 0); + vmin =3D (svsp->efuse[19] >> 4) & GENMASK(1, 0); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + + if (svsb->sw_id !=3D SVSB_GPU) + return false; + + if (vmin =3D=3D 0x1) + svsb->vmin =3D 0x1e; + + if (ft_pgm =3D=3D 0) + svsb->volt_flags |=3D SVSB_INIT01_VOLT_IGNORE; + + if (svsb->type =3D=3D SVSB_LOW) { + svsb->mtdes =3D svsp->efuse[10] & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[10] >> 16) & GENMASK(7, 0); + svsb->mdes =3D (svsp->efuse[10] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } else if (svsb->type =3D=3D SVSB_HIGH) { + svsb->mtdes =3D svsp->efuse[9] & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[9] >> 16) & GENMASK(7, 0); + svsb->mdes =3D (svsp->efuse[9] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } + + svsb->vmax +=3D svsb->dvt_fixed; + } + + /* Thermal efuse parsing */ + cell =3D nvmem_cell_get(svsp->dev, "t-calibration-data"); + if (IS_ERR_OR_NULL(cell)) { + dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", + PTR_ERR(cell)); + return false; + } + + svsp->tefuse =3D nvmem_cell_read(cell, &svsp->tefuse_max); + if (IS_ERR(svsp->tefuse)) { + dev_err(svsp->dev, "cannot read thermal efuse: %ld\n", + PTR_ERR(svsp->tefuse)); + nvmem_cell_put(cell); + return false; + } + + svsp->tefuse_max /=3D sizeof(u32); + nvmem_cell_put(cell); + + for (i =3D 0; i < svsp->tefuse_max; i++) + if (svsp->tefuse[i] !=3D 0) + break; + + if (i =3D=3D svsp->tefuse_max) + golden_temp =3D 50; /* All thermal efuse data are 0 */ + else + golden_temp =3D (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + svsb->mts =3D 500; + svsb->bts =3D (((500 * golden_temp + 250460) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2141,6 +2227,39 @@ static struct device *svs_add_device_link(struct svs= _platform *svsp, return dev; } =20 +static int svs_mt8195_platform_probe(struct svs_platform *svsp) +{ + struct device *dev; + struct svs_bank *svsb; + u32 idx; + + svsp->rst =3D devm_reset_control_get_optional(svsp->dev, "svs_rst"); + if (IS_ERR(svsp->rst)) + return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), + "cannot get svs reset control\n"); + + dev =3D svs_add_device_link(svsp, "lvts"); + if (IS_ERR(dev)) + return dev_err_probe(svsp->dev, PTR_ERR(dev), + "failed to get lvts device\n"); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + + if (svsb->type =3D=3D SVSB_HIGH) + svsb->opp_dev =3D svs_add_device_link(svsp, "mali"); + else if (svsb->type =3D=3D SVSB_LOW) + svsb->opp_dev =3D svs_get_subsys_device(svsp, "mali"); + + if (IS_ERR(svsb->opp_dev)) + return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev), + "failed to get OPP device for bank %d\n", + idx); + } + + return 0; +} + static int svs_mt8192_platform_probe(struct svs_platform *svsp) { struct device *dev; @@ -2257,6 +2376,67 @@ static int svs_mt8183_platform_probe(struct svs_plat= form *svsp) return 0; } =20 +static struct svs_bank svs_mt8195_banks[] =3D { + { + .sw_id =3D SVSB_GPU, + .type =3D SVSB_LOW, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .tzone_name =3D "gpu1", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support =3D SVSB_MODE_INIT02, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 640000000, + .turn_freq_base =3D 640000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x38, + .vmin =3D 0x14, + .age_config =3D 0x555555, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x1, + .vco =3D 0x18, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0100, + .int_st =3D BIT(0), + .ctl0 =3D 0x00540003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 0, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 7, + }, + { + .sw_id =3D SVSB_GPU, + .type =3D SVSB_HIGH, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .tzone_name =3D "gpu1", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 880000000, + .turn_freq_base =3D 640000000, + .vboot =3D 0x38, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x38, + .vmin =3D 0x14, + .age_config =3D 0x555555, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x6, + .vco =3D 0x18, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0101, + .int_st =3D BIT(1), + .ctl0 =3D 0x00540003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 0, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 7, + }, +}; + static struct svs_bank svs_mt8192_banks[] =3D { { .sw_id =3D SVSB_GPU, @@ -2559,6 +2739,16 @@ static struct svs_bank svs_mt8183_banks[] =3D { }, }; =20 +static const struct svs_platform_data svs_mt8195_platform_data =3D { + .name =3D "mt8195-svs", + .banks =3D svs_mt8195_banks, + .efuse_parsing =3D svs_mt8195_efuse_parsing, + .probe =3D svs_mt8195_platform_probe, + .irqflags =3D IRQF_TRIGGER_HIGH, + .regs =3D svs_regs_v2, + .bank_max =3D ARRAY_SIZE(svs_mt8195_banks), +}; + static const struct svs_platform_data svs_mt8192_platform_data =3D { .name =3D "mt8192-svs", .banks =3D svs_mt8192_banks, @@ -2591,6 +2781,9 @@ static const struct svs_platform_data svs_mt8183_plat= form_data =3D { =20 static const struct of_device_id svs_of_match[] =3D { { + .compatible =3D "mediatek,mt8195-svs", + .data =3D &svs_mt8195_platform_data, + }, { .compatible =3D "mediatek,mt8192-svs", .data =3D &svs_mt8192_platform_data, }, { --=20 2.18.0