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charset="utf-8" CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220518132329epcas5p307c6908621c3faa94d085b4a2cc931e1 References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Add CPU caches information so that the same is available to userspace via sysfs. This SoC has 48/32 KB I/D cache for each CPU cores and 4MB of L2 cache. Signed-off-by: Alim Akhtar --- arch/arm64/boot/dts/tesla/fsd.dtsi | 91 ++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla= /fsd.dtsi index 7ad634533104..36480a9b34c4 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -93,6 +93,13 @@ cpucl0_0: cpu@0 { enable-method =3D "psci"; clock-frequency =3D <2400000000>; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl0_1: cpu@1 { @@ -102,6 +109,13 @@ cpucl0_1: cpu@1 { enable-method =3D "psci"; clock-frequency =3D <2400000000>; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl0_2: cpu@2 { @@ -111,6 +125,13 @@ cpucl0_2: cpu@2 { enable-method =3D "psci"; clock-frequency =3D <2400000000>; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl0_3: cpu@3 { @@ -119,6 +140,13 @@ cpucl0_3: cpu@3 { reg =3D <0x0 0x003>; enable-method =3D "psci"; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 /* Cluster 1 */ @@ -129,6 +157,13 @@ cpucl1_0: cpu@100 { enable-method =3D "psci"; clock-frequency =3D <2400000000>; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl1_1: cpu@101 { @@ -138,6 +173,13 @@ cpucl1_1: cpu@101 { enable-method =3D "psci"; clock-frequency =3D <2400000000>; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl1_2: cpu@102 { @@ -147,6 +189,13 @@ cpucl1_2: cpu@102 { enable-method =3D "psci"; clock-frequency =3D <2400000000>; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl1_3: cpu@103 { @@ -156,6 +205,13 @@ cpucl1_3: cpu@103 { enable-method =3D "psci"; clock-frequency =3D <2400000000>; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 /* Cluster 2 */ @@ -166,6 +222,13 @@ cpucl2_0: cpu@200 { enable-method =3D "psci"; clock-frequency =3D <2400000000>; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl2_1: cpu@201 { @@ -175,6 +238,13 @@ cpucl2_1: cpu@201 { enable-method =3D "psci"; clock-frequency =3D <2400000000>; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl2_2: cpu@202 { @@ -184,6 +254,13 @@ cpucl2_2: cpu@202 { enable-method =3D "psci"; clock-frequency =3D <2400000000>; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; }; =20 cpucl2_3: cpu@203 { @@ -193,6 +270,20 @@ cpucl2_3: cpu@203 { enable-method =3D "psci"; clock-frequency =3D <2400000000>; cpu-idle-states =3D <&CPU_SLEEP>; + i-cache-size =3D <0xc000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; + d-cache-size =3D <0x8000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; + next-level-cache =3D <&cpucl_l2>; + }; + + cpucl_l2: l2-cache0 { + compatible =3D "cache"; + cache-size =3D <0x400000>; + cache-line-size =3D <64>; + cache-sets =3D <4096>; }; =20 idle-states { --=20 2.25.1