From nobody Fri Sep 19 12:03:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D07E4C433F5 for ; Tue, 17 May 2022 15:43:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350382AbiEQPnf (ORCPT ); Tue, 17 May 2022 11:43:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350547AbiEQPlm (ORCPT ); Tue, 17 May 2022 11:41:42 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F0843F898; Tue, 17 May 2022 08:41:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652802101; x=1684338101; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=njriNDWkJo/CGBBG2fgNO9CifzSr6dDblusxyiMLf2k=; b=hJDGAVfrUjB+wHSGg8w9wB3GWcjt9z/BGZb0bjqNT+o5gIl+gZnfJ6zV UwMYi8O2DmDpdfWErxkaE18idypLoJmQTBY6Qt9brxLoJbEauxqq0C6mF ce4i4I33s/RPvV1fQzjGd96Bs9MPebzsV+ffCSw4q/r0TLrOlEIyHucdc YiKuBwHpOXwa1JIWk29Y43Zcg5LhqjbhbaAGRZcd1SI/cWzCjyDmYVrZ3 gXVYmLn1C4VCwVYbMbfUYySnZGeNzoyp0o4KIJb5niJ+YRew4ceGonRW6 hCBk5cxsb504h4wrD+1sFnre6oZKE/Q6OGrZxZHTDDw0zZPmTmSJc2nsB A==; X-IronPort-AV: E=McAfee;i="6400,9594,10350"; a="357632117" X-IronPort-AV: E=Sophos;i="5.91,233,1647327600"; d="scan'208";a="357632117" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 08:41:36 -0700 X-IronPort-AV: E=Sophos;i="5.91,233,1647327600"; d="scan'208";a="626533610" Received: from embargo.jf.intel.com ([10.165.9.183]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 May 2022 08:41:36 -0700 From: Yang Weijiang To: pbonzini@redhat.com, jmattson@google.com, seanjc@google.com, like.xu.linux@gmail.com, vkuznets@redhat.com, kan.liang@linux.intel.com, wei.w.wang@intel.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Yang Weijiang Subject: [PATCH v12 15/16] KVM: x86: Add Arch LBR data MSR access interface Date: Tue, 17 May 2022 11:40:59 -0400 Message-Id: <20220517154100.29983-16-weijiang.yang@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220517154100.29983-1-weijiang.yang@intel.com> References: <20220517154100.29983-1-weijiang.yang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Arch LBR MSRs are xsave-supported, but they're operated as "independent" xsave feature by PMU code, i.e., during thread/process context switch, the MSRs are saved/restored with perf_event_task_sched_{in|out} instead of generic kernel fpu switch code, i.e.,save_fpregs_to_fpstate() and restore_fpregs_from_fpstate(). When vcpu guest/host fpu state swap happens, Arch LBR MSRs are retained so they can be accessed directly. Signed-off-by: Yang Weijiang Reviewed-by: Kan Liang --- arch/x86/kvm/vmx/pmu_intel.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index f5499f391a8b..c7466ba2918e 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -432,6 +432,11 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, st= ruct msr_data *msr_info) case MSR_ARCH_LBR_CTL: msr_info->data =3D vmcs_read64(GUEST_IA32_LBR_CTL); return 0; + case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31: + case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31: + case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31: + rdmsrl(msr_info->index, msr_info->data); + return 0; default: if ((pmc =3D get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || (pmc =3D get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { @@ -534,6 +539,11 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, st= ruct msr_data *msr_info) (data & ARCH_LBR_CTL_LBREN)) intel_pmu_create_guest_lbr_event(vcpu); return 0; + case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31: + case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31: + case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31: + wrmsrl(msr_info->index, msr_info->data); + return 0; default: if ((pmc =3D get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) || (pmc =3D get_gp_pmc(pmu, msr, MSR_IA32_PMC0))) { --=20 2.27.0