From nobody Thu May 7 23:18:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 126B0C433EF for ; Mon, 16 May 2022 21:15:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349266AbiEPVPn (ORCPT ); Mon, 16 May 2022 17:15:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349380AbiEPVPR (ORCPT ); Mon, 16 May 2022 17:15:17 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B92D17E05 for ; Mon, 16 May 2022 14:10:06 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id n190-20020a25d6c7000000b0064b9bf694e1so8022292ybg.3 for ; Mon, 16 May 2022 14:10:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=uR8fBj5xEbHbPpF6kOnzURYdm0/ut31Y0IfMxJWffDM=; b=k3uVMrQMx5KY7DTaJyGFyhujDhf5HLPHQg/0aCxqS5oo2mQY5FHDkhTUSQjPxxqybO kA/eQp81aO1qWo63Rh73bC+/TXjut98EQmmed89OALR85ZitiQnON9b7oc58EMGYgku1 90LqX5fl79FFgb5Zhz4DGBafUSczGI1yeesAfc5hnZJj3Jn3PKcI4vSa5lt5WLwgLO8C GyKwHTNF/HqZI4jumboVr5RUJjvtEF0wpVvrrDUqNQvOkfqS4zBnC6NfHjcpkYo/1OuH MhQXZSbmFUwBuKjuNzO+TDMalriyAofGKhozeDmkqKAjOGUdp85Vc8Xs8Qgwu1nLrcji nUuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=uR8fBj5xEbHbPpF6kOnzURYdm0/ut31Y0IfMxJWffDM=; b=xbjzdgT0e3Z0FiooGv4Xr3el6GqWcIhnwMe9XqoqKrZLSIGkCS3aqeDbMZv2Lmp03p OxqHpEzewo4g51m0dgDkTx+DaGWn/3TvMlgxBw9CSXWJFzjzFqskxSrjHHs6Qyoli/Uo gGpSdUL1RoRO+ZbJRnpk8DA4rcrnl/HHrKjW2Ark0mE5yhfF9F8nVzga8j9WSAqRggZo UddkZh0CdDSUokAItJZWSQvACXRlTle9CbKj/g+Avvm4SuvuC4WYZ9rOKWzeqdr0UkJy qNp4MFMd1AX4wUu1vgPniHfoYIPJFm/I5Htm+2P2myQnTV3EtohKfk4X+No9M+SitGrg iK9g== X-Gm-Message-State: AOAM533ZenlD0QC1L959iLrv5I5yCsQ6HhJoIZUikuUDZ8+8ZNcK67Rk yL72U5QE6loXWC953BwJqc/hUQvA6Tq2sSBN6Lc= X-Google-Smtp-Source: ABdhPJyDi6K2oWYXlyWCJ5XKcQVc/+zo2gwZ5YIL/COpbALJXAIL4i9mZKX4jcpzEcnqt2DJGWV03Fw4pOgixa+NJU8= X-Received: from ndesaulniers1.mtv.corp.google.com ([2620:15c:211:202:2ef0:b8de:b9c8:da45]) (user=ndesaulniers job=sendgmr) by 2002:a25:fe12:0:b0:64b:473f:cb79 with SMTP id k18-20020a25fe12000000b0064b473fcb79mr20805404ybe.82.1652735405447; Mon, 16 May 2022 14:10:05 -0700 (PDT) Date: Mon, 16 May 2022 14:09:51 -0700 In-Reply-To: <20220516210954.1660716-1-ndesaulniers@google.com> Message-Id: <20220516210954.1660716-2-ndesaulniers@google.com> Mime-Version: 1.0 References: <20220516210954.1660716-1-ndesaulniers@google.com> X-Developer-Key: i=ndesaulniers@google.com; a=ed25519; pk=lvO/pmg+aaCb6dPhyGC1GyOCvPueDrrc8Zeso5CaGKE= X-Developer-Signature: v=1; a=ed25519-sha256; t=1652735394; l=3985; s=20211004; h=from:subject; bh=gVoVkYKp2fU88mTtUugTh71wg9G6f/KfwhDgJ87QUd8=; b=arxbscZTEvpEke55vwBYjBhK3a5JbxBkFo8AE5K5jAu1hTI0EVf0NjdTojY3MekesE1ui17QOmUi IxK7fHIzB0nn38yIJRfegglWQwYT22lzKrGDP3dLQfSyZokvCrVV X-Mailer: git-send-email 2.36.0.550.gb090851708-goog Subject: [PATCH v3 1/4] ARM: remove lazy evaluation in Makefile From: Nick Desaulniers To: Arnd Bergmann , Ard@google.com, Biesheuvel@google.com Cc: Russell King , Masahiro Yamada , Linus Walleij , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Nick Desaulniers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" arch-y and tune-y used lazy evaluation since they used to contain cc-option checks. They don't any longer, so just eagerly evaluate these command line flags. Signed-off-by: Nick Desaulniers --- arch/arm/Makefile | 60 +++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 33 deletions(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a2391b8de5a5..99a7ed7e9f09 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -60,44 +60,38 @@ KBUILD_CFLAGS +=3D $(call cc-option,-fno-ipa-sra) # Note that GCC does not numerically define an architecture version # macro, but instead defines a whole series of macros which makes # testing for a specific architecture or later rather impossible. -arch-$(CONFIG_CPU_32v7M) =3D-D__LINUX_ARM_ARCH__=3D7 -march=3Darmv7-m -arch-$(CONFIG_CPU_32v7) =3D-D__LINUX_ARM_ARCH__=3D7 -march=3Darmv7-a -arch-$(CONFIG_CPU_32v6) =3D-D__LINUX_ARM_ARCH__=3D6 -march=3Darmv6 -# Only override the compiler option if ARMv6. The ARMv6K extensions are +arch-$(CONFIG_CPU_32v7M) :=3D-D__LINUX_ARM_ARCH__=3D7 -march=3Darmv7-m +arch-$(CONFIG_CPU_32v7) :=3D-D__LINUX_ARM_ARCH__=3D7 -march=3Darmv7-a +arch-$(CONFIG_CPU_32v6) :=3D-D__LINUX_ARM_ARCH__=3D6 -march=3Darmv6 +# Only override the compiler opt:ion if ARMv6. The ARMv6K extensions are # always available in ARMv7 ifeq ($(CONFIG_CPU_32v6),y) -arch-$(CONFIG_CPU_32v6K) =3D-D__LINUX_ARM_ARCH__=3D6 -march=3Darmv6k +arch-$(CONFIG_CPU_32v6K) :=3D-D__LINUX_ARM_ARCH__=3D6 -march=3Darmv6k endif -arch-$(CONFIG_CPU_32v5) =3D-D__LINUX_ARM_ARCH__=3D5 -march=3Darmv5te -arch-$(CONFIG_CPU_32v4T) =3D-D__LINUX_ARM_ARCH__=3D4 -march=3Darmv4t -arch-$(CONFIG_CPU_32v4) =3D-D__LINUX_ARM_ARCH__=3D4 -march=3Darmv4 -arch-$(CONFIG_CPU_32v3) =3D-D__LINUX_ARM_ARCH__=3D3 -march=3Darmv3m - -# Evaluate arch cc-option calls now -arch-y :=3D $(arch-y) +arch-$(CONFIG_CPU_32v5) :=3D-D__LINUX_ARM_ARCH__=3D5 -march=3Darmv5te +arch-$(CONFIG_CPU_32v4T) :=3D-D__LINUX_ARM_ARCH__=3D4 -march=3Darmv4t +arch-$(CONFIG_CPU_32v4) :=3D-D__LINUX_ARM_ARCH__=3D4 -march=3Darmv4 +arch-$(CONFIG_CPU_32v3) :=3D-D__LINUX_ARM_ARCH__=3D3 -march=3Darmv3m =20 # This selects how we optimise for the processor. -tune-$(CONFIG_CPU_ARM7TDMI) =3D-mtune=3Darm7tdmi -tune-$(CONFIG_CPU_ARM720T) =3D-mtune=3Darm7tdmi -tune-$(CONFIG_CPU_ARM740T) =3D-mtune=3Darm7tdmi -tune-$(CONFIG_CPU_ARM9TDMI) =3D-mtune=3Darm9tdmi -tune-$(CONFIG_CPU_ARM940T) =3D-mtune=3Darm9tdmi -tune-$(CONFIG_CPU_ARM946E) =3D-mtune=3Darm9e -tune-$(CONFIG_CPU_ARM920T) =3D-mtune=3Darm9tdmi -tune-$(CONFIG_CPU_ARM922T) =3D-mtune=3Darm9tdmi -tune-$(CONFIG_CPU_ARM925T) =3D-mtune=3Darm9tdmi -tune-$(CONFIG_CPU_ARM926T) =3D-mtune=3Darm9tdmi -tune-$(CONFIG_CPU_FA526) =3D-mtune=3Darm9tdmi -tune-$(CONFIG_CPU_SA110) =3D-mtune=3Dstrongarm110 -tune-$(CONFIG_CPU_SA1100) =3D-mtune=3Dstrongarm1100 -tune-$(CONFIG_CPU_XSCALE) =3D-mtune=3Dxscale -tune-$(CONFIG_CPU_XSC3) =3D-mtune=3Dxscale -tune-$(CONFIG_CPU_FEROCEON) =3D-mtune=3Dxscale -tune-$(CONFIG_CPU_V6) =3D-mtune=3Darm1136j-s -tune-$(CONFIG_CPU_V6K) =3D-mtune=3Darm1136j-s - -# Evaluate tune cc-option calls now -tune-y :=3D $(tune-y) +tune-$(CONFIG_CPU_ARM7TDMI) :=3D-mtune=3Darm7tdmi +tune-$(CONFIG_CPU_ARM720T) :=3D-mtune=3Darm7tdmi +tune-$(CONFIG_CPU_ARM740T) :=3D-mtune=3Darm7tdmi +tune-$(CONFIG_CPU_ARM9TDMI) :=3D-mtune=3Darm9tdmi +tune-$(CONFIG_CPU_ARM940T) :=3D-mtune=3Darm9tdmi +tune-$(CONFIG_CPU_ARM946E) :=3D-mtune=3Darm9e +tune-$(CONFIG_CPU_ARM920T) :=3D-mtune=3Darm9tdmi +tune-$(CONFIG_CPU_ARM922T) :=3D-mtune=3Darm9tdmi +tune-$(CONFIG_CPU_ARM925T) :=3D-mtune=3Darm9tdmi +tune-$(CONFIG_CPU_ARM926T) :=3D-mtune=3Darm9tdmi +tune-$(CONFIG_CPU_FA526) :=3D-mtune=3Darm9tdmi +tune-$(CONFIG_CPU_SA110) :=3D-mtune=3Dstrongarm110 +tune-$(CONFIG_CPU_SA1100) :=3D-mtune=3Dstrongarm1100 +tune-$(CONFIG_CPU_XSCALE) :=3D-mtune=3Dxscale +tune-$(CONFIG_CPU_XSC3) :=3D-mtune=3Dxscale +tune-$(CONFIG_CPU_FEROCEON) :=3D-mtune=3Dxscale +tune-$(CONFIG_CPU_V6) :=3D-mtune=3Darm1136j-s +tune-$(CONFIG_CPU_V6K) :=3D-mtune=3Darm1136j-s =20 ifeq ($(CONFIG_AEABI),y) CFLAGS_ABI :=3D-mabi=3Daapcs-linux -mfpu=3Dvfp --=20 2.36.0.550.gb090851708-goog From nobody Thu May 7 23:18:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF003C433EF for ; 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Mon, 16 May 2022 14:10:07 -0700 (PDT) Date: Mon, 16 May 2022 14:09:52 -0700 In-Reply-To: <20220516210954.1660716-1-ndesaulniers@google.com> Message-Id: <20220516210954.1660716-3-ndesaulniers@google.com> Mime-Version: 1.0 References: <20220516210954.1660716-1-ndesaulniers@google.com> X-Developer-Key: i=ndesaulniers@google.com; a=ed25519; pk=lvO/pmg+aaCb6dPhyGC1GyOCvPueDrrc8Zeso5CaGKE= X-Developer-Signature: v=1; a=ed25519-sha256; t=1652735394; l=21462; s=20211004; h=from:subject; bh=lWL9CI3d/2sCju02NOTSxZQK2cjA6Q8x5ATsTbJtBVs=; b=WQ9ecbMOrJfVUGeJAcE5xMH13aM8Mr6YhRDw7W69/GNLoL9s45Qe5Vad9X6R3kkSPLmMjLezI+32 fvy3OV8uBGI9z5Z0LVmmFIXFOmgUtYvw8OhFl+UXXWiA8gxCd5Q/ X-Mailer: git-send-email 2.36.0.550.gb090851708-goog Subject: [PATCH v3 2/4] ARM: use .arch directives instead of assembler command line flags From: Nick Desaulniers To: Arnd Bergmann , Ard@google.com, Biesheuvel@google.com Cc: Russell King , Masahiro Yamada , Linus Walleij , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Nick Desaulniers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Similar to commit a6c30873ee4a ("ARM: 8989/1: use .fpu assembler directives instead of assembler arguments"). GCC and GNU binutils support setting the "sub arch" via -march=3D, -Wa,-march, target function attribute, and .arch assembler directive. Clang was missing support for -Wa,-march=3D, but this was implemented in clang-13. The behavior of both GCC and Clang is to prefer -Wa,-march=3D over -march=3D for assembler and assembler-with-cpp sources, but Clang will warn about the -march=3D being unused. clang: warning: argument unused during compilation: '-march=3Darmv6k' [-Wunused-command-line-argument] Since most assembler is non-conditionally assembled with one sub arch (modulo arch/arm/delay-loop.S which conditionally is assembled as armv4 based on CONFIG_ARCH_RPC, and arch/arm/mach-at91/pm-suspend.S which is conditionally assembled as armv7-a based on CONFIG_CPU_V7), prefer the .arch assembler directive. Link: https://github.com/llvm/llvm-project/commit/1d51c699b9e2ebc5bcfdbe85c= 74cc871426333d4 Link: https://bugs.llvm.org/show_bug.cgi?id=3D48894 Link: https://github.com/ClangBuiltLinux/linux/issues/1195 Link: https://github.com/ClangBuiltLinux/linux/issues/1315 Suggested-by: Arnd Bergmann Signed-off-by: Nick Desaulniers [arnd] add a few more instances found in compile testing Signed-off-by: Arnd Bergmann --- arch/arm/boot/compressed/Makefile | 1 - arch/arm/common/Makefile | 2 -- arch/arm/common/mcpm_head.S | 2 ++ arch/arm/common/vlock.S | 2 ++ arch/arm/kernel/Makefile | 2 -- arch/arm/kernel/hyp-stub.S | 2 ++ arch/arm/kernel/swp_emulate.c | 1 + arch/arm/lib/Makefile | 4 ---- arch/arm/lib/delay-loop.S | 4 ++++ arch/arm/mach-at91/Makefile | 3 --- arch/arm/mach-at91/pm_suspend.S | 4 ++++ arch/arm/mach-imx/Makefile | 3 --- arch/arm/mach-imx/headsmp.S | 2 ++ arch/arm/mach-imx/resume-imx6.S | 2 ++ arch/arm/mach-imx/suspend-imx6.S | 2 ++ arch/arm/mach-mvebu/Makefile | 3 --- arch/arm/mach-mvebu/coherency_ll.S | 1 + arch/arm/mach-mvebu/pmsu.c | 1 + arch/arm/mach-npcm/Makefile | 2 -- arch/arm/mach-npcm/headsmp.S | 2 ++ arch/arm/mach-tegra/Makefile | 2 -- arch/arm/mach-tegra/reset-handler.S | 2 ++ arch/arm/mach-tegra/sleep-tegra20.S | 2 ++ arch/arm/mach-tegra/sleep-tegra30.S | 2 ++ arch/arm/mm/Makefile | 15 --------------- arch/arm/mm/abort-ev6.S | 1 + arch/arm/mm/abort-ev7.S | 1 + arch/arm/mm/cache-v6.S | 2 ++ arch/arm/mm/cache-v7.S | 2 ++ arch/arm/mm/cache-v7m.S | 2 ++ arch/arm/mm/copypage-feroceon.c | 1 + arch/arm/mm/proc-v6.S | 2 ++ arch/arm/mm/proc-v7-2level.S | 2 ++ arch/arm/mm/proc-v7.S | 2 ++ arch/arm/mm/tlb-v6.S | 2 ++ arch/arm/mm/tlb-v7.S | 2 ++ drivers/memory/Makefile | 2 -- drivers/memory/ti-emif-sram-pm.S | 1 + drivers/soc/bcm/brcmstb/pm/Makefile | 1 - drivers/soc/bcm/brcmstb/pm/s2-arm.S | 1 + 40 files changed, 52 insertions(+), 40 deletions(-) diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/M= akefile index 41bcbb460fac..e5c80ff42a4f 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -163,4 +163,3 @@ $(obj)/piggy_data: $(obj)/../Image FORCE $(obj)/piggy.o: $(obj)/piggy_data =20 CFLAGS_font.o :=3D -Dstatic=3D -AFLAGS_hyp-stub.o :=3D -Wa,-march=3Darmv7-a diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index 8cd574be94cf..6a42600fa4c5 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -14,7 +14,5 @@ obj-$(CONFIG_SHARP_SCOOP) +=3D scoop.o obj-$(CONFIG_CPU_V7) +=3D secure_cntvoff.o obj-$(CONFIG_MCPM) +=3D mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o CFLAGS_REMOVE_mcpm_entry.o =3D -pg -AFLAGS_mcpm_head.o :=3D -march=3Darmv7-a -AFLAGS_vlock.o :=3D -march=3Darmv7-a obj-$(CONFIG_BL_SWITCHER) +=3D bL_switcher.o obj-$(CONFIG_BL_SWITCHER_DUMMY_IF) +=3D bL_switcher_dummy_if.o diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S index 291d969bc719..299495c43dfd 100644 --- a/arch/arm/common/mcpm_head.S +++ b/arch/arm/common/mcpm_head.S @@ -15,6 +15,8 @@ =20 #include "vlock.h" =20 +.arch armv7-a + .if MCPM_SYNC_CLUSTER_CPUS .error "cpus must be the first member of struct mcpm_sync_struct" .endif diff --git a/arch/arm/common/vlock.S b/arch/arm/common/vlock.S index f1c7fd44f1b1..1fa09c4697ed 100644 --- a/arch/arm/common/vlock.S +++ b/arch/arm/common/vlock.S @@ -12,6 +12,8 @@ #include #include "vlock.h" =20 +.arch armv7-a + /* Select different code if voting flags can fit in a single word. */ #if VLOCK_VOTING_SIZE > 4 #define FEW(x...) diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 553866751e1a..e64ed3a82f70 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -71,7 +71,6 @@ obj-$(CONFIG_HAVE_TCM) +=3D tcm.o obj-$(CONFIG_OF) +=3D devtree.o obj-$(CONFIG_CRASH_DUMP) +=3D crash_dump.o obj-$(CONFIG_SWP_EMULATE) +=3D swp_emulate.o -CFLAGS_swp_emulate.o :=3D -Wa,-march=3Darmv7-a obj-$(CONFIG_HAVE_HW_BREAKPOINT) +=3D hw_breakpoint.o =20 obj-$(CONFIG_CPU_XSCALE) +=3D xscale-cp0.o @@ -100,7 +99,6 @@ CFLAGS_head-inflate-data.o :=3D $(call cc-option,-Wframe= -larger-than=3D10240) obj-$(CONFIG_XIP_DEFLATED_DATA) +=3D head-inflate-data.o =20 obj-$(CONFIG_ARM_VIRT_EXT) +=3D hyp-stub.o -AFLAGS_hyp-stub.o :=3D-Wa,-march=3Darmv7-a ifeq ($(CONFIG_ARM_PSCI),y) obj-$(CONFIG_SMP) +=3D psci_smp.o endif diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S index b699b22a4db1..3a506b9095a5 100644 --- a/arch/arm/kernel/hyp-stub.S +++ b/arch/arm/kernel/hyp-stub.S @@ -9,6 +9,8 @@ #include #include =20 +.arch armv7-a + #ifndef ZIMAGE /* * For the kernel proper, we need to find out the CPU boot mode long after diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c index b74bfcf94fb1..fdce83c95acb 100644 --- a/arch/arm/kernel/swp_emulate.c +++ b/arch/arm/kernel/swp_emulate.c @@ -34,6 +34,7 @@ */ #define __user_swpX_asm(data, addr, res, temp, B) \ __asm__ __volatile__( \ + ".arch armv7-a\n" \ "0: ldrex"B" %2, [%3]\n" \ "1: strex"B" %0, %1, [%3]\n" \ " cmp %0, #0\n" \ diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 6d2ba454f25b..42fb75c06647 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -36,10 +36,6 @@ else lib-y +=3D io-readsw-armv4.o io-writesw-armv4.o endif =20 -ifeq ($(CONFIG_ARCH_RPC),y) - AFLAGS_delay-loop.o +=3D -march=3Darmv4 -endif - $(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S $(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S =20 diff --git a/arch/arm/lib/delay-loop.S b/arch/arm/lib/delay-loop.S index 3ccade0f8130..3ac05177d097 100644 --- a/arch/arm/lib/delay-loop.S +++ b/arch/arm/lib/delay-loop.S @@ -8,6 +8,10 @@ #include #include =20 +#ifdef CONFIG_ARCH_RPC + .arch armv4 +#endif + .text =20 .LC0: .word loops_per_jiffy diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 522b680b6446..e7a47fa03626 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -14,9 +14,6 @@ obj-$(CONFIG_SOC_SAMV7) +=3D samv7.o # Power Management obj-$(CONFIG_ATMEL_PM) +=3D pm.o pm_suspend.o =20 -ifeq ($(CONFIG_CPU_V7),y) -AFLAGS_pm_suspend.o :=3D -march=3Darmv7-a -endif ifeq ($(CONFIG_PM_DEBUG),y) CFLAGS_pm.o +=3D -DDEBUG endif diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspen= d.S index abe4ced33eda..f0aa220d668d 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -12,6 +12,10 @@ #include "pm.h" #include "pm_data-offsets.h" =20 +#ifdef CONFIG_CPU_V7 +.arch armv7-a +#endif + #define SRAMC_SELF_FRESH_ACTIVE 0x01 #define SRAMC_SELF_FRESH_EXIT 0x00 =20 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 6fb3965b9ae6..5c650bf40e02 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -34,7 +34,6 @@ obj-$(CONFIG_HAVE_IMX_GPC) +=3D gpc.o obj-$(CONFIG_HAVE_IMX_MMDC) +=3D mmdc.o obj-$(CONFIG_HAVE_IMX_SRC) +=3D src.o ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7D_CA7)$(CONFIG_SOC_LS1021A),) -AFLAGS_headsmp.o :=3D-Wa,-march=3Darmv7-a obj-$(CONFIG_SMP) +=3D headsmp.o platsmp.o obj-$(CONFIG_HOTPLUG_CPU) +=3D hotplug.o endif @@ -48,12 +47,10 @@ obj-$(CONFIG_SOC_IMX7D_CM4) +=3D mach-imx7d-cm4.o obj-$(CONFIG_SOC_IMX7ULP) +=3D mach-imx7ulp.o pm-imx7ulp.o =20 ifeq ($(CONFIG_SUSPEND),y) -AFLAGS_suspend-imx6.o :=3D-Wa,-march=3Darmv7-a obj-$(CONFIG_SOC_IMX6) +=3D suspend-imx6.o obj-$(CONFIG_SOC_IMX53) +=3D suspend-imx53.o endif ifeq ($(CONFIG_ARM_CPU_SUSPEND),y) -AFLAGS_resume-imx6.o :=3D-Wa,-march=3Darmv7-a obj-$(CONFIG_SOC_IMX6) +=3D resume-imx6.o endif obj-$(CONFIG_SOC_IMX6) +=3D pm-imx6.o diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index fcba58be8e79..5f9c7b48ae80 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S @@ -8,6 +8,8 @@ #include #include =20 +.arch armv7-a + diag_reg_offset: .word g_diag_reg - . =20 diff --git a/arch/arm/mach-imx/resume-imx6.S b/arch/arm/mach-imx/resume-imx= 6.S index 5bd1ba7ef15b..2c0c5c771251 100644 --- a/arch/arm/mach-imx/resume-imx6.S +++ b/arch/arm/mach-imx/resume-imx6.S @@ -9,6 +9,8 @@ #include #include "hardware.h" =20 +.arch armv7-a + /* * The following code must assume it is running from physical address * where absolute virtual addresses to the data section have to be diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-i= mx6.S index e06f946b75b9..63ccc2d0e920 100644 --- a/arch/arm/mach-imx/suspend-imx6.S +++ b/arch/arm/mach-imx/suspend-imx6.S @@ -9,6 +9,8 @@ #include #include "hardware.h" =20 +.arch armv7-a + /* * =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D low level = suspend =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D * diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index cb106899dd7c..9b9fddb69958 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -1,9 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) :=3D -I$(srctree)/arch/arm/plat-orion= /include =20 -AFLAGS_coherency_ll.o :=3D -Wa,-march=3Darmv7-a -CFLAGS_pmsu.o :=3D -march=3Darmv7-a - obj-$(CONFIG_MACH_MVEBU_ANY) +=3D system-controller.o mvebu-soc-id.o =20 ifeq ($(CONFIG_MACH_MVEBU_V7),y) diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coher= ency_ll.S index a3a64bf97250..25197290632d 100644 --- a/arch/arm/mach-mvebu/coherency_ll.S +++ b/arch/arm/mach-mvebu/coherency_ll.S @@ -23,6 +23,7 @@ #include #include =20 + .arch armv7-a .text /* * Returns the coherency base address in r1 (r0 is untouched), or 0 if diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index 73d5d72dfc3e..9a77cc3a10bd 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -294,6 +294,7 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidl= e) =20 /* Test the CR_C bit and set it if it was cleared */ asm volatile( + ".arch armv7-a\n\t" "mrc p15, 0, r0, c1, c0, 0 \n\t" "tst r0, %0 \n\t" "orreq r0, r0, #(1 << 2) \n\t" diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile index 8d61fcd42fb1..ac83e1caf2ee 100644 --- a/arch/arm/mach-npcm/Makefile +++ b/arch/arm/mach-npcm/Makefile @@ -1,6 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -AFLAGS_headsmp.o +=3D -march=3Darmv7-a - obj-$(CONFIG_ARCH_WPCM450) +=3D wpcm450.o obj-$(CONFIG_ARCH_NPCM7XX) +=3D npcm7xx.o obj-$(CONFIG_SMP) +=3D platsmp.o headsmp.o diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S index c083fe09a07b..84d2b6daaf0b 100644 --- a/arch/arm/mach-npcm/headsmp.S +++ b/arch/arm/mach-npcm/headsmp.S @@ -6,6 +6,8 @@ #include #include =20 +.arch armv7-a + /* * The boot ROM does not start secondary CPUs in SVC mode, so we need to d= o that * here. diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 07572b5373b8..a2bb55bc0081 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,6 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -asflags-y +=3D -march=3Darmv7-a - obj-y +=3D io.o obj-y +=3D irq.o obj-y +=3D pm.o diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/rese= t-handler.S index 06ca44b09381..0ea456264f3e 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -19,6 +19,8 @@ =20 #define PMC_SCRATCH41 0x140 =20 +.arch armv7-a + #ifdef CONFIG_PM_SLEEP /* * tegra_resume diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/slee= p-tegra20.S index a5a36cce142a..d8cd487a8f63 100644 --- a/arch/arm/mach-tegra/sleep-tegra20.S +++ b/arch/arm/mach-tegra/sleep-tegra20.S @@ -47,6 +47,8 @@ #define PLLM_STORE_MASK (1 << 1) #define PLLP_STORE_MASK (1 << 2) =20 +.arch armv7-a + .macro test_pll_state, rd, test_mask ldr \rd, tegra_pll_state tst \rd, #\test_mask diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/slee= p-tegra30.S index 0cc40b6b2ba3..134ea5fe49b2 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S @@ -78,6 +78,8 @@ #define PLLX_STORE_MASK (1 << 4) #define PLLM_PMC_STORE_MASK (1 << 5) =20 +.arch armv7-a + .macro emc_device_mask, rd, base ldr \rd, [\base, #EMC_ADR_CFG] tst \rd, #0x1 diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 3510503bc5e6..71b858c9b10c 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile @@ -33,9 +33,6 @@ obj-$(CONFIG_CPU_ABRT_EV5TJ) +=3D abort-ev5tj.o obj-$(CONFIG_CPU_ABRT_EV6) +=3D abort-ev6.o obj-$(CONFIG_CPU_ABRT_EV7) +=3D abort-ev7.o =20 -AFLAGS_abort-ev6.o :=3D-Wa,-march=3Darmv6k -AFLAGS_abort-ev7.o :=3D-Wa,-march=3Darmv7-a - obj-$(CONFIG_CPU_PABRT_LEGACY) +=3D pabort-legacy.o obj-$(CONFIG_CPU_PABRT_V6) +=3D pabort-v6.o obj-$(CONFIG_CPU_PABRT_V7) +=3D pabort-v7.o @@ -49,10 +46,6 @@ obj-$(CONFIG_CPU_CACHE_FA) +=3D cache-fa.o obj-$(CONFIG_CPU_CACHE_NOP) +=3D cache-nop.o obj-$(CONFIG_CPU_CACHE_V7M) +=3D cache-v7m.o =20 -AFLAGS_cache-v6.o :=3D-Wa,-march=3Darmv6 -AFLAGS_cache-v7.o :=3D-Wa,-march=3Darmv7-a -AFLAGS_cache-v7m.o :=3D-Wa,-march=3Darmv7-m - obj-$(CONFIG_CPU_COPY_V4WT) +=3D copypage-v4wt.o obj-$(CONFIG_CPU_COPY_V4WB) +=3D copypage-v4wb.o obj-$(CONFIG_CPU_COPY_FEROCEON) +=3D copypage-feroceon.o @@ -62,8 +55,6 @@ obj-$(CONFIG_CPU_XSCALE) +=3D copypage-xscale.o obj-$(CONFIG_CPU_XSC3) +=3D copypage-xsc3.o obj-$(CONFIG_CPU_COPY_FA) +=3D copypage-fa.o =20 -CFLAGS_copypage-feroceon.o :=3D -march=3Darmv5te - obj-$(CONFIG_CPU_TLB_V4WT) +=3D tlb-v4.o obj-$(CONFIG_CPU_TLB_V4WB) +=3D tlb-v4wb.o obj-$(CONFIG_CPU_TLB_V4WBI) +=3D tlb-v4wbi.o @@ -72,9 +63,6 @@ obj-$(CONFIG_CPU_TLB_V6) +=3D tlb-v6.o obj-$(CONFIG_CPU_TLB_V7) +=3D tlb-v7.o obj-$(CONFIG_CPU_TLB_FA) +=3D tlb-fa.o =20 -AFLAGS_tlb-v6.o :=3D-Wa,-march=3Darmv6 -AFLAGS_tlb-v7.o :=3D-Wa,-march=3Darmv7-a - obj-$(CONFIG_CPU_ARM7TDMI) +=3D proc-arm7tdmi.o obj-$(CONFIG_CPU_ARM720T) +=3D proc-arm720.o obj-$(CONFIG_CPU_ARM740T) +=3D proc-arm740.o @@ -101,9 +89,6 @@ obj-$(CONFIG_CPU_V6K) +=3D proc-v6.o obj-$(CONFIG_CPU_V7) +=3D proc-v7.o proc-v7-bugs.o obj-$(CONFIG_CPU_V7M) +=3D proc-v7m.o =20 -AFLAGS_proc-v6.o :=3D-Wa,-march=3Darmv6 -AFLAGS_proc-v7.o :=3D-Wa,-march=3Darmv7-a - obj-$(CONFIG_OUTER_CACHE) +=3D l2c-common.o obj-$(CONFIG_CACHE_B15_RAC) +=3D cache-b15-rac.o obj-$(CONFIG_CACHE_FEROCEON_L2) +=3D cache-feroceon-l2.o diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index c58bf8b43fea..836dc1299243 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -16,6 +16,7 @@ * abort here if the I-TLB and D-TLB aren't seeing the same * picture. Unfortunately, this does happen. We live with it. */ + .arch armv6k .align 5 ENTRY(v6_early_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR diff --git a/arch/arm/mm/abort-ev7.S b/arch/arm/mm/abort-ev7.S index f81bceacc660..53fb41c24774 100644 --- a/arch/arm/mm/abort-ev7.S +++ b/arch/arm/mm/abort-ev7.S @@ -12,6 +12,7 @@ * * Purpose : obtain information about current aborted instruction. */ + .arch armv7-a .align 5 ENTRY(v7_early_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index f0f65eb073e4..250c83bf7158 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -19,6 +19,8 @@ #define D_CACHE_LINE_SIZE 32 #define BTB_FLUSH_SIZE 8 =20 +.arch armv6 + /* * v6_flush_icache_all() * diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 7c9499b728c4..127afe2096ba 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -16,6 +16,8 @@ =20 #include "proc-macros.S" =20 +.arch armv7-a + #ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND .globl icache_size .data diff --git a/arch/arm/mm/cache-v7m.S b/arch/arm/mm/cache-v7m.S index 1bc3a0a50753..eb60b5e5e2ad 100644 --- a/arch/arm/mm/cache-v7m.S +++ b/arch/arm/mm/cache-v7m.S @@ -18,6 +18,8 @@ =20 #include "proc-macros.S" =20 +.arch armv7-m + /* Generic V7M read/write macros for memory mapped cache operations */ .macro v7m_cache_read, rt, reg movw \rt, #:lower16:BASEADDR_V7M_SCB + \reg diff --git a/arch/arm/mm/copypage-feroceon.c b/arch/arm/mm/copypage-feroceo= n.c index 064b19e63571..5fc8ef1e665f 100644 --- a/arch/arm/mm/copypage-feroceon.c +++ b/arch/arm/mm/copypage-feroceon.c @@ -15,6 +15,7 @@ static void feroceon_copy_user_page(void *kto, const void= *kfrom) int tmp; =20 asm volatile ("\ +.arch armv5te \n\ 1: ldmia %1!, {r2 - r7, ip, lr} \n\ pld [%1, #0] \n\ pld [%1, #32] \n\ diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index a0618f3e6836..203dff89ab1a 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -32,6 +32,8 @@ #define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S =20 +.arch armv6 + ENTRY(cpu_v6_proc_init) ret lr =20 diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index 5db029c8f987..0a3083ad19c2 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -24,6 +24,8 @@ #define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S =20 +.arch armv7-a + /* * cpu_v7_switch_mm(pgd_phys, tsk) * diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 26d726a08a34..6b4ef9539b68 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -24,6 +24,8 @@ #include "proc-v7-2level.S" #endif =20 +.arch armv7-a + ENTRY(cpu_v7_proc_init) ret lr ENDPROC(cpu_v7_proc_init) diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S index 74f4b383afe3..1d91e49b2c2d 100644 --- a/arch/arm/mm/tlb-v6.S +++ b/arch/arm/mm/tlb-v6.S @@ -17,6 +17,8 @@ =20 #define HARVARD_TLB =20 +.arch armv6 + /* * v6wbi_flush_user_tlb_range(start, end, vma) * diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S index 87bf4ab17721..35fd6d4f0d03 100644 --- a/arch/arm/mm/tlb-v7.S +++ b/arch/arm/mm/tlb-v7.S @@ -16,6 +16,8 @@ #include #include "proc-macros.S" =20 +.arch armv7-a + /* * v7wbi_flush_user_tlb_range(start, end, vma) * diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index bc7663ed1c25..d1388a748872 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -32,8 +32,6 @@ obj-$(CONFIG_FPGA_DFL_EMIF) +=3D dfl-emif.o =20 ti-emif-sram-objs :=3D ti-emif-pm.o ti-emif-sram-pm.o =20 -AFLAGS_ti-emif-sram-pm.o :=3D-Wa,-march=3Darmv7-a - $(obj)/ti-emif-sram-pm.o: $(obj)/ti-emif-asm-offsets.h =20 $(obj)/ti-emif-asm-offsets.h: $(obj)/emif-asm-offsets.s FORCE diff --git a/drivers/memory/ti-emif-sram-pm.S b/drivers/memory/ti-emif-sram= -pm.S index d1c83bd5b98e..af2feb251303 100644 --- a/drivers/memory/ti-emif-sram-pm.S +++ b/drivers/memory/ti-emif-sram-pm.S @@ -36,6 +36,7 @@ =20 .arm .align 3 + .arch armv7-a =20 ENTRY(ti_emif_sram) =20 diff --git a/drivers/soc/bcm/brcmstb/pm/Makefile b/drivers/soc/bcm/brcmstb/= pm/Makefile index 8e10abb14f8b..f849cfa69446 100644 --- a/drivers/soc/bcm/brcmstb/pm/Makefile +++ b/drivers/soc/bcm/brcmstb/pm/Makefile @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_ARM) +=3D s2-arm.o pm-arm.o -AFLAGS_s2-arm.o :=3D -march=3Darmv7-a obj-$(CONFIG_BMIPS_GENERIC) +=3D s2-mips.o s3-mips.o pm-mips.o diff --git a/drivers/soc/bcm/brcmstb/pm/s2-arm.S b/drivers/soc/bcm/brcmstb/= pm/s2-arm.S index 5f0c4a8ae9df..0d693795de27 100644 --- a/drivers/soc/bcm/brcmstb/pm/s2-arm.S +++ b/drivers/soc/bcm/brcmstb/pm/s2-arm.S @@ -8,6 +8,7 @@ =20 #include "pm.h" =20 + .arch armv7-a .text .align 3 =20 --=20 2.36.0.550.gb090851708-goog From nobody Thu May 7 23:18:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9228C433F5 for ; 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Mon, 16 May 2022 14:10:09 -0700 (PDT) Date: Mon, 16 May 2022 14:09:53 -0700 In-Reply-To: <20220516210954.1660716-1-ndesaulniers@google.com> Message-Id: <20220516210954.1660716-4-ndesaulniers@google.com> Mime-Version: 1.0 References: <20220516210954.1660716-1-ndesaulniers@google.com> X-Developer-Key: i=ndesaulniers@google.com; a=ed25519; pk=lvO/pmg+aaCb6dPhyGC1GyOCvPueDrrc8Zeso5CaGKE= X-Developer-Signature: v=1; a=ed25519-sha256; t=1652735394; l=938; s=20211004; h=from:subject; bh=T9BSmoUTZZ/l/4cKzU/17oPppOyCGzetEds5NOZIrWQ=; b=8FrOhkyvfC7vArFsPvAnd24amfcR4JlfF0QbPfyYrJ5dNOBuwKcXRFBPcYEjIvovyC8NaU6XW8kg 0rstkQerBW6KdT7Rc+cTUyjdSir5seoBM0spKRrjhKOvZ+34H6kG X-Mailer: git-send-email 2.36.0.550.gb090851708-goog Subject: [PATCH v3 3/4] ARM: only use -mtp=cp15 for the compiler From: Nick Desaulniers To: Arnd Bergmann , Ard@google.com, Biesheuvel@google.com Cc: Russell King , Masahiro Yamada , Linus Walleij , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Nick Desaulniers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Avoids an error from the assembler for CONFIG_THUMB2 kernels: clang-15: error: hardware TLS register is not supported for the thumbv4t sub-architecture This flag only makes sense to pass to the compiler, not the assembler. Perhaps CFLAGS_ABI can be renamed to CPPFLAGS_ABI to reflect that they will be passed to both the compiler and assembler for sources that require pre-processing. Signed-off-by: Nick Desaulniers --- arch/arm/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 99a7ed7e9f09..1029c2503aef 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -108,7 +108,7 @@ CFLAGS_ABI +=3D -meabi gnu endif =20 ifeq ($(CONFIG_CURRENT_POINTER_IN_TPIDRURO),y) -CFLAGS_ABI +=3D -mtp=3Dcp15 +KBUILD_CFLAGS +=3D -mtp=3Dcp15 endif =20 # Accept old syntax despite ".syntax unified" --=20 2.36.0.550.gb090851708-goog From nobody Thu May 7 23:18:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A652EC4332F for ; Mon, 16 May 2022 21:15:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349302AbiEPVPt (ORCPT ); Mon, 16 May 2022 17:15:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349133AbiEPVPT (ORCPT ); Mon, 16 May 2022 17:15:19 -0400 Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B888317E28 for ; Mon, 16 May 2022 14:10:13 -0700 (PDT) Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-2fedfd0f5b2so44473577b3.16 for ; Mon, 16 May 2022 14:10:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc; bh=BmTyv5Df5nSkvL+7PwI+QdbCtOf+cNe9vmiXu33ntQI=; b=gptOuy544f1/kWDiF/3OwcmGk6scE1yCINr+MYB1fM6wQOI6FyysBHER/hQTOSK0b+ MaV+lyiNd6H08pwzyCgMNFopwYNwi/ySdFT99VpNmwgQEw0rEy19FI8sloRnORfz9EV4 YuA8+Csdh3kYQlEkStrZ0CpdJcbK+x+1D+bsBF5GlIIousYpIEVQAE3MkbbjAsA60HDM jP9FqLob+qAOGNb6Ycu0ImKBZ1mi+hSyanggzGdQSkDubEMBbMo3sfYBAr0LDXQzZdaR JkwFLL7wq3O3irglenxPj5cF750M8ZXPb/t3wKR9aCD4OZO67kD9v4JgQWVu/llWeVVm 8ZHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc; bh=BmTyv5Df5nSkvL+7PwI+QdbCtOf+cNe9vmiXu33ntQI=; b=A8OyU7FrjHk8I49C/AZqwoWIE96O65FM0VUmeJiMPmU4gVvmNOy0uXq1LNs9Lu7/CL mF8vM0yHQ53zlBClPb1hBaOHd3OG3D3e1KIxFbadCoP81tl9XSvpSly4DyzwcISrGXzt 1DhtfEkfT8fmUVlfcqB1c3aPN//WFhf16F4DxJmXMcmLrugkB5/0VxIB7eoHocPvRx9U 4QboJFsXqMUSkzhnLzKqBHDlMFvW1y0uESrTCCrZf0Opw8rgoqJFISU6KGPBVFJE4E9O 6ygadqm1+rwW67Gbry/5HS8gmsvgRSk/SrxW5XUNgCwQwZN+Aqr6MaI4X/bdTrJ/Iw12 uVdg== X-Gm-Message-State: AOAM5335PdL2IffJ+x5juMMqQEXsTxJ+q3tx9D8ptToRljp7mhgE2/tt sUzF52PB/LYozNcH48kiQVKsHBCJeUZ+2lkMdcM= X-Google-Smtp-Source: ABdhPJyMla5qPnmYHt216sR4ibgSN7vwxmKWbie1i9N4867KZ+Hc7TO27zSrR5W1Qkojj5JAsQSKdVVdoFJA+sTbuZw= X-Received: from ndesaulniers1.mtv.corp.google.com ([2620:15c:211:202:2ef0:b8de:b9c8:da45]) (user=ndesaulniers job=sendgmr) by 2002:a25:d116:0:b0:64d:6fe1:4dc5 with SMTP id i22-20020a25d116000000b0064d6fe14dc5mr11663959ybg.576.1652735412883; Mon, 16 May 2022 14:10:12 -0700 (PDT) Date: Mon, 16 May 2022 14:09:54 -0700 In-Reply-To: <20220516210954.1660716-1-ndesaulniers@google.com> Message-Id: <20220516210954.1660716-5-ndesaulniers@google.com> Mime-Version: 1.0 References: <20220516210954.1660716-1-ndesaulniers@google.com> X-Developer-Key: i=ndesaulniers@google.com; a=ed25519; pk=lvO/pmg+aaCb6dPhyGC1GyOCvPueDrrc8Zeso5CaGKE= X-Developer-Signature: v=1; a=ed25519-sha256; t=1652735394; l=3775; s=20211004; h=from:subject; bh=+s618NXBymdAo9VdYorCW3hWAXdQktAqz3laN51+p0c=; b=OVKnwODfYq9bHW9OJKqrl5qkJCDSXoxeW3Uqh+U1PMMqzJNX8xSLFGLaDqfYUfRMRaRK9PaeLrVs k97zmrYECFqtsXsQ5YEhv3E7FzsuxYTtWcX5oD9dXLdHurNhF4CA X-Mailer: git-send-email 2.36.0.550.gb090851708-goog Subject: [PATCH v3 4/4] ARM: pass -march= only to compiler From: Nick Desaulniers To: Arnd Bergmann , Ard@google.com, Biesheuvel@google.com Cc: Russell King , Masahiro Yamada , Linus Walleij , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev, Nick Desaulniers Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When both -march=3D and -Wa,-march=3D are specified for assembler or assembler-with-cpp sources, GCC and Clang will prefer the -Wa,-march=3D value but Clang will warn that -march=3D is unused. warning: argument unused during compilation: '-march=3Darmv6k' [-Wunused-command-line-argument] This is the top group of warnings we observe when using clang to assemble the kernel via `ARCH=3Darm make LLVM=3D1`. Split the arch-y make variable into two, so that -march=3D flags only get passed to the compiler, not the assembler. -D flags are added to KBUILD_CPPFLAGS which is used for both C and assembler-with-cpp sources. Link: https://github.com/ClangBuiltLinux/linux/issues/1315 Link: https://github.com/ClangBuiltLinux/linux/issues/1587 Link: https://lore.kernel.org/llvm/628249e8.1c69fb81.d20fd.02ea@mx.google.c= om/ Signed-off-by: Nick Desaulniers Reported-by: kernel test robot --- arch/arm/Makefile | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1029c2503aef..47a300f6f99c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -57,21 +57,34 @@ endif KBUILD_CFLAGS +=3D $(call cc-option,-fno-ipa-sra) =20 # This selects which instruction set is used. +arch-$(CONFIG_CPU_32v7M) :=3D-march=3Darmv7-m +arch-$(CONFIG_CPU_32v7) :=3D-march=3Darmv7-a +arch-$(CONFIG_CPU_32v6) :=3D-march=3Darmv6 +# Only override the compiler option if ARMv6. The ARMv6K extensions are +# always available in ARMv7 +ifeq ($(CONFIG_CPU_32v6),y) +arch-$(CONFIG_CPU_32v6K) :=3D-march=3Darmv6k +endif +arch-$(CONFIG_CPU_32v5) :=3D-march=3Darmv5te +arch-$(CONFIG_CPU_32v4T) :=3D-march=3Darmv4t +arch-$(CONFIG_CPU_32v4) :=3D-march=3Darmv4 +arch-$(CONFIG_CPU_32v3) :=3D-march=3Darmv3m + # Note that GCC does not numerically define an architecture version # macro, but instead defines a whole series of macros which makes # testing for a specific architecture or later rather impossible. -arch-$(CONFIG_CPU_32v7M) :=3D-D__LINUX_ARM_ARCH__=3D7 -march=3Darmv7-m -arch-$(CONFIG_CPU_32v7) :=3D-D__LINUX_ARM_ARCH__=3D7 -march=3Darmv7-a -arch-$(CONFIG_CPU_32v6) :=3D-D__LINUX_ARM_ARCH__=3D6 -march=3Darmv6 -# Only override the compiler opt:ion if ARMv6. The ARMv6K extensions are +cpp-$(CONFIG_CPU_32v7M) :=3D-D__LINUX_ARM_ARCH__=3D7 +cpp-$(CONFIG_CPU_32v7) :=3D-D__LINUX_ARM_ARCH__=3D7 +cpp-$(CONFIG_CPU_32v6) :=3D-D__LINUX_ARM_ARCH__=3D6 +# Only override the compiler option if ARMv6. The ARMv6K extensions are # always available in ARMv7 ifeq ($(CONFIG_CPU_32v6),y) -arch-$(CONFIG_CPU_32v6K) :=3D-D__LINUX_ARM_ARCH__=3D6 -march=3Darmv6k +cpp-$(CONFIG_CPU_32v6K) :=3D-D__LINUX_ARM_ARCH__=3D6 endif -arch-$(CONFIG_CPU_32v5) :=3D-D__LINUX_ARM_ARCH__=3D5 -march=3Darmv5te -arch-$(CONFIG_CPU_32v4T) :=3D-D__LINUX_ARM_ARCH__=3D4 -march=3Darmv4t -arch-$(CONFIG_CPU_32v4) :=3D-D__LINUX_ARM_ARCH__=3D4 -march=3Darmv4 -arch-$(CONFIG_CPU_32v3) :=3D-D__LINUX_ARM_ARCH__=3D3 -march=3Darmv3m +cpp-$(CONFIG_CPU_32v5) :=3D-D__LINUX_ARM_ARCH__=3D5 +cpp-$(CONFIG_CPU_32v4T) :=3D-D__LINUX_ARM_ARCH__=3D4 +cpp-$(CONFIG_CPU_32v4) :=3D-D__LINUX_ARM_ARCH__=3D4 +cpp-$(CONFIG_CPU_32v3) :=3D-D__LINUX_ARM_ARCH__=3D3 =20 # This selects how we optimise for the processor. tune-$(CONFIG_CPU_ARM7TDMI) :=3D-mtune=3Darm7tdmi @@ -123,8 +136,9 @@ AFLAGS_ISA :=3D$(CFLAGS_ISA) endif =20 # Need -Uarm for gcc < 3.x +KBUILD_CPPFLAGS +=3D$(cpp-y) KBUILD_CFLAGS +=3D$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call c= c-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-fl= oat -Uarm -KBUILD_AFLAGS +=3D$(CFLAGS_ABI) $(AFLAGS_ISA) $(arch-y) $(tune-y) -include= asm/unified.h -msoft-float +KBUILD_AFLAGS +=3D$(CFLAGS_ABI) $(AFLAGS_ISA) -Wa,$(arch-y) $(tune-y) -inc= lude asm/unified.h -msoft-float =20 CHECKFLAGS +=3D -D__arm__ =20 --=20 2.36.0.550.gb090851708-goog