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[70.53.205.21]) by smtp.gmail.com with ESMTPSA id k67-20020a378846000000b006a00fabde68sm6364016qkd.10.2022.05.16.13.40.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 13:40:01 -0700 (PDT) From: Yannick Brosseau To: jic23@kernel.org, lars@metafoo.de, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, fabrice.gasnier@foss.st.com, olivier.moysan@foss.st.com Cc: paul@crapouillou.net, linux-iio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yannick Brosseau Subject: [PATCH v2 1/2] iio: adc: stm32: Fix ADCs iteration in irq handler Date: Mon, 16 May 2022 16:39:38 -0400 Message-Id: <20220516203939.3498673-2-yannick.brosseau@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220516203939.3498673-1-yannick.brosseau@gmail.com> References: <20220516203939.3498673-1-yannick.brosseau@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The irq handler was only checking the mask for the first ADCs in the case o= f the F4 and H7 generation, since it was iterating up to the num_irq value. This = patch add the maximum number of ADC in the common register, which map to the number o= f entries of eoc_msk and ovr_msk in stm32_adc_common_regs. This allow the handler to che= ck all ADCs in that module. Tested on a STM32F429NIH6. Fixes: 695e2f5c289b ("iio: adc: stm32-adc: fix a regression when using dma = and irq") Signed-off-by: Yannick Brosseau Reviewed-by: Fabrice Gasnier --- drivers/iio/adc/stm32-adc-core.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-c= ore.c index 142656232157..bb04deeb7992 100644 --- a/drivers/iio/adc/stm32-adc-core.c +++ b/drivers/iio/adc/stm32-adc-core.c @@ -64,6 +64,7 @@ struct stm32_adc_priv; * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet) * @has_syscfg: SYSCFG capability flags * @num_irqs: number of interrupt lines + * @num_adcs: maximum number of ADC instances in the common registers */ struct stm32_adc_priv_cfg { const struct stm32_adc_common_regs *regs; @@ -71,6 +72,7 @@ struct stm32_adc_priv_cfg { u32 max_clk_rate_hz; unsigned int has_syscfg; unsigned int num_irqs; + unsigned int num_adcs; }; =20 /** @@ -352,7 +354,7 @@ static void stm32_adc_irq_handler(struct irq_desc *desc) * before invoking the interrupt handler (e.g. call ISR only for * IRQ-enabled ADCs). */ - for (i =3D 0; i < priv->cfg->num_irqs; i++) { + for (i =3D 0; i < priv->cfg->num_adcs; i++) { if ((status & priv->cfg->regs->eoc_msk[i] && stm32_adc_eoc_enabled(priv, i)) || (status & priv->cfg->regs->ovr_msk[i])) @@ -792,6 +794,7 @@ static const struct stm32_adc_priv_cfg stm32f4_adc_priv= _cfg =3D { .clk_sel =3D stm32f4_adc_clk_sel, .max_clk_rate_hz =3D 36000000, .num_irqs =3D 1, + .num_adcs =3D 3, }; =20 static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg =3D { @@ -800,6 +803,7 @@ static const struct stm32_adc_priv_cfg stm32h7_adc_priv= _cfg =3D { .max_clk_rate_hz =3D 36000000, .has_syscfg =3D HAS_VBOOSTER, .num_irqs =3D 1, + .num_adcs =3D 2, }; =20 static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg =3D { @@ -808,6 +812,7 @@ static const struct stm32_adc_priv_cfg stm32mp1_adc_pri= v_cfg =3D { .max_clk_rate_hz =3D 40000000, .has_syscfg =3D HAS_VBOOSTER | HAS_ANASWVDD, .num_irqs =3D 2, + .num_adcs =3D 2, }; =20 static const struct of_device_id stm32_adc_of_match[] =3D { --=20 2.36.1 From nobody Thu May 7 23:18:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B1D6C433F5 for ; Mon, 16 May 2022 21:04:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348654AbiEPVEt (ORCPT ); Mon, 16 May 2022 17:04:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349085AbiEPVEd (ORCPT ); Mon, 16 May 2022 17:04:33 -0400 Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8A405C766; Mon, 16 May 2022 13:40:09 -0700 (PDT) Received: by mail-qt1-x82e.google.com with SMTP id u3so2741715qta.8; Mon, 16 May 2022 13:40:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hKBcyX3Ppfu6XQjIjRejfr2DzYtK4WWEcAa5qty3cHg=; b=oukrXqAAZdBan6tdF/K2D/kCxUwWgPeZLEnHGfR+Ln2zBB1SI+qLLEfyNCPPXVMh22 qjUN8mwA7XKNfDNOaSMbYwhl8TJQOibuS9mVrzonAfGAO/iqdUCpyVD7K6RYYt6Ck+09 5I0enB+WW4r5ELpXeKMMneOKTFZK9+adctc1HrJ/lqyJ0JqYaBrrnZfsP4R8kybDxWNY cY+mKVgXNFoEggevYW+sqUyma+gTEVo8vb7W7f/KFatUHvASyI950xDNhsrgxw5WnpKh 2pNj5+4jAfv5YMPMByRTCn6tNxzFhWmWAonNqG+6rB5jM/Qr5rcj4nZzcbgnRhsSq9x6 tnxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hKBcyX3Ppfu6XQjIjRejfr2DzYtK4WWEcAa5qty3cHg=; b=xrEV1G3My8xR/PpbNq6g1RiYbflL9NHySwQmRtUCVTXEq0C44pl6xDFzvQ9Btrjas/ vTBOmfwSK1Ejr28HZgdl+5C1qoJX+Kk+t2bqECX7M3vYvsjLWHlXZIX5wjvkYXqlmRH2 R1jxDkfzlydGDEqB+iI3STsO+jVFRUgw3rVOqWzu8PX1gyMEV9nk6zgc6YJ5px5WxXyi sSgxGp4RxzY2LCUHbVpuzh6nwOToXBk5xLJKYzwYeuKMvBu8ew5CZknT6aYUlQpnawjU c24jslWxFmU9yCeQGrgmeJHMkWul2SS5aE1W4D6lXRgF93VtZOLIg/eyuiAHUp2XiKUF jVuw== X-Gm-Message-State: AOAM531De2ZZ1mSdncqY4isVzBiKmAE+apIFkJBnmhegIuoFHXke7Rt+ 3PGdmCX8EjJwk2CMHmI8/I7FLfxtvTfcWQ== X-Google-Smtp-Source: ABdhPJyYvbcv8J+a4WY5fmCWaSGt/mt3uew74uDkCuyrQ24GIBr26QFwVCeQkFKfAyRihFdydtDalw== X-Received: by 2002:ac8:5f06:0:b0:2f3:cbe5:1e1d with SMTP id x6-20020ac85f06000000b002f3cbe51e1dmr16773074qta.389.1652733607848; Mon, 16 May 2022 13:40:07 -0700 (PDT) Received: from grrm.lan (bras-base-mtrlpq4809w-grc-17-70-53-205-21.dsl.bell.ca. [70.53.205.21]) by smtp.gmail.com with ESMTPSA id k67-20020a378846000000b006a00fabde68sm6364016qkd.10.2022.05.16.13.40.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 13:40:07 -0700 (PDT) From: Yannick Brosseau To: jic23@kernel.org, lars@metafoo.de, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, fabrice.gasnier@foss.st.com, olivier.moysan@foss.st.com Cc: paul@crapouillou.net, linux-iio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yannick Brosseau Subject: [PATCH v2 2/2] iio: adc: stm32: Fix IRQs on STM32F4 by removing custom spurious IRQs message Date: Mon, 16 May 2022 16:39:39 -0400 Message-Id: <20220516203939.3498673-3-yannick.brosseau@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220516203939.3498673-1-yannick.brosseau@gmail.com> References: <20220516203939.3498673-1-yannick.brosseau@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The check for spurious IRQs introduced in 695e2f5c289bb assumed that the bi= ts in the control and status registers are aligned. This is true for the H7 an= d MP1 version, but not the F4. The interrupt was then never handled on the F4. Instead of increasing the complexity of the comparison and check each bit s= pecifically, we remove this check completely and rely on the generic handler for spuriou= s IRQs. Fixes: 695e2f5c289b ("iio: adc: stm32-adc: fix a regression when using dma = and irq") Signed-off-by: Yannick Brosseau Reviewed-by: Fabrice Gasnier --- drivers/iio/adc/stm32-adc.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c index a68ecbda6480..8c5f05f593ab 100644 --- a/drivers/iio/adc/stm32-adc.c +++ b/drivers/iio/adc/stm32-adc.c @@ -1407,7 +1407,6 @@ static irqreturn_t stm32_adc_threaded_isr(int irq, vo= id *data) struct stm32_adc *adc =3D iio_priv(indio_dev); const struct stm32_adc_regspec *regs =3D adc->cfg->regs; u32 status =3D stm32_adc_readl(adc, regs->isr_eoc.reg); - u32 mask =3D stm32_adc_readl(adc, regs->ier_eoc.reg); =20 /* Check ovr status right now, as ovr mask should be already disabled */ if (status & regs->isr_ovr.mask) { @@ -1422,11 +1421,6 @@ static irqreturn_t stm32_adc_threaded_isr(int irq, v= oid *data) return IRQ_HANDLED; } =20 - if (!(status & mask)) - dev_err_ratelimited(&indio_dev->dev, - "Unexpected IRQ: IER=3D0x%08x, ISR=3D0x%08x\n", - mask, status); - return IRQ_NONE; } =20 @@ -1436,10 +1430,6 @@ static irqreturn_t stm32_adc_isr(int irq, void *data) struct stm32_adc *adc =3D iio_priv(indio_dev); const struct stm32_adc_regspec *regs =3D adc->cfg->regs; u32 status =3D stm32_adc_readl(adc, regs->isr_eoc.reg); - u32 mask =3D stm32_adc_readl(adc, regs->ier_eoc.reg); - - if (!(status & mask)) - return IRQ_WAKE_THREAD; =20 if (status & regs->isr_ovr.mask) { /* --=20 2.36.1