From nobody Fri May 8 00:10:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B25EC433EF for ; Mon, 16 May 2022 15:24:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245223AbiEPPYv (ORCPT ); Mon, 16 May 2022 11:24:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235544AbiEPPYq (ORCPT ); Mon, 16 May 2022 11:24:46 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 659D93981A; Mon, 16 May 2022 08:24:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652714685; x=1684250685; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R/+6zYJkMdhw9qD4LUaNt6Hef+u3nCvlP8VmMLrkqXA=; b=EIyI7Ns8CCaIxf6qnbR4oB0V3/b/iDE8qixw2gH4iY/danFP3W8x7vHe WcfkJ/Px0z4TXTU4qQmAfw8Se4//pOqJ7Lo6ZZ8ogldB6tX//JENm/3uT crcUu5K+yvraW2KqP488ndJCVm/yRKT7BjL8ELB2h5ESJF0iBiHTB00PE ZbFCRSiNeCqRYQiCJtm+gu06pcRQ8fJvDOfXA9NKUsVHJkz7r1A5ETHGZ 0Cd1zpZShnkMoNrYGmw5udye+SmGnQlhgxrki9TVOQAWEJcDoQkQkirn1 dv6097GH9AsgIkNjqjRQRyGTIisouv/wZqVU75YvlrF4IXKydwQqU8Y+r g==; X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="270561297" X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="270561297" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 08:24:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="741290201" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga005.jf.intel.com with ESMTP; 16 May 2022 08:24:43 -0700 From: kan.liang@linux.intel.com To: acme@kernel.org, mingo@redhat.com, irogers@google.com, jolsa@kernel.org, namhyung@kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: peterz@infradead.org, zhengjun.xing@linux.intel.com, adrian.hunter@intel.com, ak@linux.intel.com, eranian@google.com, Kan Liang Subject: [PATCH V2 1/4] perf evsel: Fixes topdown events in a weak group for the hybrid platform Date: Mon, 16 May 2022 08:24:33 -0700 Message-Id: <20220516152436.1104757-2-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220516152436.1104757-1-kan.liang@linux.intel.com> References: <20220516152436.1104757-1-kan.liang@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kan Liang The patch ("perf evlist: Keep topdown counters in weak group") fixes the perf metrics topdown event issue when the topdown events are in a weak group on a non-hybrid platform. However, it doesn't work for the hybrid platform. $./perf stat -e '{cpu_core/slots/,cpu_core/topdown-bad-spec/, cpu_core/topdown-be-bound/,cpu_core/topdown-fe-bound/, cpu_core/topdown-retiring/,cpu_core/branch-instructions/, cpu_core/branch-misses/,cpu_core/bus-cycles/,cpu_core/cache-misses/, cpu_core/cache-references/,cpu_core/cpu-cycles/,cpu_core/instructions/, cpu_core/mem-loads/,cpu_core/mem-stores/,cpu_core/ref-cycles/, cpu_core/cache-misses/,cpu_core/cache-references/}:W' -a sleep 1 Performance counter stats for 'system wide': 751,765,068 cpu_core/slots/ = (84.07%) cpu_core/topdown-bad-spec/ cpu_core/topdown-be-bound/ cpu_core/topdown-fe-bound/ cpu_core/topdown-retiring/ 12,398,197 cpu_core/branch-instructions/ = (84.07%) 1,054,218 cpu_core/branch-misses/ = (84.24%) 539,764,637 cpu_core/bus-cycles/ = (84.64%) 14,683 cpu_core/cache-misses/ = (84.87%) 7,277,809 cpu_core/cache-references/ = (77.30%) 222,299,439 cpu_core/cpu-cycles/ = (77.28%) 63,661,714 cpu_core/instructions/ = (84.85%) 0 cpu_core/mem-loads/ = (77.29%) 12,271,725 cpu_core/mem-stores/ = (77.30%) 542,241,102 cpu_core/ref-cycles/ = (84.85%) 8,854 cpu_core/cache-misses/ = (76.71%) 7,179,013 cpu_core/cache-references/ = (76.31%) 1.003245250 seconds time elapsed A hybrid platform has a different PMU name for the core PMUs, while the current perf hard code the PMU name "cpu". The evsel->pmu_name can be used to replace the "cpu" to fix the issue. For a hybrid platform, the pmu_name must be non-NULL. Because there are at least two core PMUs. The PMU has to be specified. For a non-hybrid platform, the pmu_name may be NULL. Because there is only one core PMU, "cpu". For a NULL pmu_name, we can safely assume that it is a "cpu" PMU. In case other PMUs also define the "slots" event, checking the PMU type as well. With the patch, $perf stat -e '{cpu_core/slots/,cpu_core/topdown-bad-spec/, cpu_core/topdown-be-bound/,cpu_core/topdown-fe-bound/, cpu_core/topdown-retiring/,cpu_core/branch-instructions/, cpu_core/branch-misses/,cpu_core/bus-cycles/,cpu_core/cache-misses/, cpu_core/cache-references/,cpu_core/cpu-cycles/,cpu_core/instructions/, cpu_core/mem-loads/,cpu_core/mem-stores/,cpu_core/ref-cycles/, cpu_core/cache-misses/,cpu_core/cache-references/}:W' -a sleep 1 Performance counter stats for 'system wide': 766,620,266 cpu_core/slots/ = (84.06%) 73,172,129 cpu_core/topdown-bad-spec/ # 9.5% bad speculat= ion (84.06%) 193,443,341 cpu_core/topdown-be-bound/ # 25.0% backend boun= d (84.06%) 403,940,929 cpu_core/topdown-fe-bound/ # 52.3% frontend bou= nd (84.06%) 102,070,237 cpu_core/topdown-retiring/ # 13.2% retiring = (84.06%) 12,364,429 cpu_core/branch-instructions/ = (84.03%) 1,080,124 cpu_core/branch-misses/ = (84.24%) 564,120,383 cpu_core/bus-cycles/ = (84.65%) 36,979 cpu_core/cache-misses/ = (84.86%) 7,298,094 cpu_core/cache-references/ = (77.30%) 227,174,372 cpu_core/cpu-cycles/ = (77.31%) 63,886,523 cpu_core/instructions/ = (84.87%) 0 cpu_core/mem-loads/ = (77.31%) 12,208,782 cpu_core/mem-stores/ = (77.31%) 566,409,738 cpu_core/ref-cycles/ = (84.87%) 23,118 cpu_core/cache-misses/ = (76.71%) 7,212,602 cpu_core/cache-references/ = (76.29%) 1.003228667 seconds time elapsed Signed-off-by: Kan Liang --- tools/perf/arch/x86/util/evsel.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/tools/perf/arch/x86/util/evsel.c b/tools/perf/arch/x86/util/ev= sel.c index 00cb4466b4ca..6eda5a491eda 100644 --- a/tools/perf/arch/x86/util/evsel.c +++ b/tools/perf/arch/x86/util/evsel.c @@ -31,10 +31,27 @@ void arch_evsel__fixup_new_cycles(struct perf_event_att= r *attr) free(env.cpuid); } =20 +static bool evsel__sys_has_perf_metrics(const struct evsel *evsel) +{ + const char *pmu_name =3D evsel->pmu_name ? evsel->pmu_name : "cpu"; + + /* + * The PERF_TYPE_RAW type is the core PMU type. + * The slots event is only available for the core PMU, which + * supports the perf metrics feature. + * Checking both the PERF_TYPE_RAW type and the slots event + * should be good enough to detect the perf metrics feature. + */ + if ((evsel->core.attr.type =3D=3D PERF_TYPE_RAW) && + pmu_have_event(pmu_name, "slots")) + return true; + + return false; +} + bool arch_evsel__must_be_in_group(const struct evsel *evsel) { - if ((evsel->pmu_name && strcmp(evsel->pmu_name, "cpu")) || - !pmu_have_event("cpu", "slots")) + if (!evsel__sys_has_perf_metrics(evsel)) return false; =20 return evsel->name && --=20 2.35.1 From nobody Fri May 8 00:10:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAED5C433F5 for ; Mon, 16 May 2022 15:24:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245298AbiEPPYz (ORCPT ); Mon, 16 May 2022 11:24:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238688AbiEPPYq (ORCPT ); Mon, 16 May 2022 11:24:46 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5B673BF8F; Mon, 16 May 2022 08:24:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652714685; x=1684250685; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AkUng3hq2aUzIGEkrrJfWuMFjhuDTcDzFpA1oGYCNuA=; b=TiISzL1oYQzdFwKp96pC0plraTNM2Bw7ehxgB97nj+Rf3dbFA3ZUHAX9 31F6knjaeJ6hUocYhMx3xxNAzmB/BGXTi5EwZueWuOPu2rdm1FreTqt87 2kBVdd3YBZIvlOduUJDgQ8oDjxJ9BIbaRpv07EMZuy9sikPGu7R7rky4h hLn3zQOm49/Feh1pERrWzPVXKtOB+zfvVwr/QfzFXjHkZOFQ+c34DUbbe 8FlOujq2wWlAmRqw2T20DFIUF5QX/1ssFweXt72a99m6Wc20Kt0GZeziS WCbfBwWxhMO8ONPE0XFmkkyguKLtXQiyviyCL0EFwZ9yzIkGl4bgXJnkM w==; X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="270561298" X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="270561298" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 08:24:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="741290205" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga005.jf.intel.com with ESMTP; 16 May 2022 08:24:43 -0700 From: kan.liang@linux.intel.com To: acme@kernel.org, mingo@redhat.com, irogers@google.com, jolsa@kernel.org, namhyung@kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: peterz@infradead.org, zhengjun.xing@linux.intel.com, adrian.hunter@intel.com, ak@linux.intel.com, eranian@google.com, Kan Liang Subject: [PATCH V2 2/4] perf stat: Always keep perf metrics topdown events in a group Date: Mon, 16 May 2022 08:24:34 -0700 Message-Id: <20220516152436.1104757-3-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220516152436.1104757-1-kan.liang@linux.intel.com> References: <20220516152436.1104757-1-kan.liang@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kan Liang If any member in a group has a different cpu mask than the other members, the current perf stat disables group. when the perf metrics topdown events are part of the group, the below error will be triggered. $ perf stat -e "{slots,topdown-retiring,uncore_imc_free_running_0/dclk/}" -= a sleep 1 WARNING: grouped events cpus do not match, disabling group: anon group { slots, topdown-retiring, uncore_imc_free_running_0/dclk/ } Performance counter stats for 'system wide': 141,465,174 slots topdown-retiring 1,605,330,334 uncore_imc_free_running_0/dclk/ The perf metrics topdown events must always be grouped with a slots event as leader. Factor out evsel__remove_from_group() to only remove the regular events from the group. Remove evsel__must_be_in_group(), since no one use it anymore. With the patch, the topdown events aren't broken from the group for the splitting. $ perf stat -e "{slots,topdown-retiring,uncore_imc_free_running_0/dclk/}" -= a sleep 1 WARNING: grouped events cpus do not match, disabling group: anon group { slots, topdown-retiring, uncore_imc_free_running_0/dclk/ } Performance counter stats for 'system wide': 346,110,588 slots 124,608,256 topdown-retiring 1,606,869,976 uncore_imc_free_running_0/dclk/ 1.003877592 seconds time elapsed Fixes: a9a1790247bd ("perf stat: Ensure group is defined on top of the same= cpu mask") Signed-off-by: Kan Liang --- tools/perf/builtin-stat.c | 7 +++---- tools/perf/util/evlist.c | 6 +----- tools/perf/util/evsel.c | 13 +++++++++++-- tools/perf/util/evsel.h | 2 +- 4 files changed, 16 insertions(+), 12 deletions(-) diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index a96f106dc93a..75c88c7939b1 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -271,10 +271,9 @@ static void evlist__check_cpu_maps(struct evlist *evli= st) pr_warning(" %s: %s\n", evsel->name, buf); } =20 - for_each_group_evsel(pos, leader) { - evsel__set_leader(pos, pos); - pos->core.nr_members =3D 0; - } + for_each_group_evsel(pos, leader) + evsel__remove_from_group(pos, leader); + evsel->core.leader->nr_members =3D 0; } } diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index dfa65a383502..7fc544330fea 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -1795,11 +1795,7 @@ struct evsel *evlist__reset_weak_group(struct evlist= *evsel_list, struct evsel * * them. Some events, like Intel topdown, require being * in a group and so keep these in the group. */ - if (!evsel__must_be_in_group(c2) && c2 !=3D leader) { - evsel__set_leader(c2, c2); - c2->core.nr_members =3D 0; - leader->core.nr_members--; - } + evsel__remove_from_group(c2, leader); =20 /* * Set this for all former members of the group diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index b98882cbb286..deb428ee5e50 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -3083,7 +3083,16 @@ bool __weak arch_evsel__must_be_in_group(const struc= t evsel *evsel __maybe_unuse return false; } =20 -bool evsel__must_be_in_group(const struct evsel *evsel) +/* + * Remove an event from a given group (leader). + * Some events, e.g., perf metrics Topdown events, + * must always be grouped. Ignore the events. + */ +void evsel__remove_from_group(struct evsel *evsel, struct evsel *leader) { - return arch_evsel__must_be_in_group(evsel); + if (!arch_evsel__must_be_in_group(evsel) && evsel !=3D leader) { + evsel__set_leader(evsel, evsel); + evsel->core.nr_members =3D 0; + leader->core.nr_members--; + } } diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index a36172ed4cf6..47f65f8e7c74 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -483,7 +483,7 @@ bool evsel__has_leader(struct evsel *evsel, struct evse= l *leader); bool evsel__is_leader(struct evsel *evsel); void evsel__set_leader(struct evsel *evsel, struct evsel *leader); int evsel__source_count(const struct evsel *evsel); -bool evsel__must_be_in_group(const struct evsel *evsel); +void evsel__remove_from_group(struct evsel *evsel, struct evsel *leader); =20 bool arch_evsel__must_be_in_group(const struct evsel *evsel); =20 --=20 2.35.1 From nobody Fri May 8 00:10:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A76CC433EF for ; Mon, 16 May 2022 15:25:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245299AbiEPPY7 (ORCPT ); Mon, 16 May 2022 11:24:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233348AbiEPPYs (ORCPT ); Mon, 16 May 2022 11:24:48 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A3CC3BF93; Mon, 16 May 2022 08:24:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652714686; x=1684250686; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XFEeuqGOKYZbTkzW8wUdOuH8GKHFxQqzXqZIW5aoD3Q=; b=LunLe1htK/GM+8/yrWVrBsxvYEi2Hk57/jcjeCXE3kzi8Qf4TA78sD0S tTZZw3UiiGoqIxBf2nuCkZ2xFsFp9W0k8ip03tk6yx1D6XN8b8wt5XlJS 7ZARuOUERkwH3du4Nkj9JrnbDQUsfsgNCakzqkLP/9sc5T2LWDDLIFcCw O5tJhDCvtfQFWhowMUbQqh9IikGvVeDdGJ3ZKL+hw4zGkOyEQd7HVN7ig I0igvzPVeu4DngNcSG8bH+IOTVsm0zTiIsQk/GdPkqxJ8FgMsR82GFLJE zEeKcaswxMvu1x7maS51QvfLN6bqbbspoP7vb1tqsUcbRgnc0XRF0TlOx Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="270561300" X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="270561300" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 08:24:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="741290213" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga005.jf.intel.com with ESMTP; 16 May 2022 08:24:43 -0700 From: kan.liang@linux.intel.com To: acme@kernel.org, mingo@redhat.com, irogers@google.com, jolsa@kernel.org, namhyung@kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: peterz@infradead.org, zhengjun.xing@linux.intel.com, adrian.hunter@intel.com, ak@linux.intel.com, eranian@google.com, Kan Liang Subject: [PATCH V2 3/4] perf parse-events: Support different format of the topdown event name Date: Mon, 16 May 2022 08:24:35 -0700 Message-Id: <20220516152436.1104757-4-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220516152436.1104757-1-kan.liang@linux.intel.com> References: <20220516152436.1104757-1-kan.liang@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kan Liang The evsel->name may have a different format for a topdown event, a pure topdown name (e.g., topdown-fe-bound), or a PMU name + a topdown name (e.g., cpu/topdown-fe-bound/). The cpu/topdown-fe-bound/ kind format isn't supported by the arch_evlist__leader(). This format is a very common format for a hybrid platform, which requires specifying the PMU name for each event. Without the patch, $perf stat -e '{instructions,slots,cpu/topdown-fe-bound/}' -a sleep 1 Performance counter stats for 'system wide': instructions slots cpu/topdown-fe-bound/ 1.003482041 seconds time elapsed Some events weren't counted. Try disabling the NMI watchdog: echo 0 > /proc/sys/kernel/nmi_watchdog perf stat ... echo 1 > /proc/sys/kernel/nmi_watchdog The events in group usually have to be from the same PMU. Try reorganizing = the group. With the patch, perf stat -e '{instructions,slots,cpu/topdown-fe-bound/}' -a sleep 1 Performance counter stats for 'system wide': 157,383,996 slots 25,011,711 instructions 27,441,686 cpu/topdown-fe-bound/ 1.003530890 seconds time elapsed Fixes: bc355822f0d9 ("perf parse-events: Move slots only with topdown") Reviewed-by: Ian Rogers Signed-off-by: Kan Liang --- tools/perf/arch/x86/util/evlist.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/arch/x86/util/evlist.c b/tools/perf/arch/x86/util/e= vlist.c index cfc208d71f00..75564a7df15b 100644 --- a/tools/perf/arch/x86/util/evlist.c +++ b/tools/perf/arch/x86/util/evlist.c @@ -36,7 +36,7 @@ struct evsel *arch_evlist__leader(struct list_head *list) if (slots =3D=3D first) return first; } - if (!strncasecmp(evsel->name, "topdown", 7)) + if (strcasestr(evsel->name, "topdown")) has_topdown =3D true; if (slots && has_topdown) return slots; --=20 2.35.1 From nobody Fri May 8 00:10:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24C2EC433EF for ; Mon, 16 May 2022 15:25:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233348AbiEPPZF (ORCPT ); Mon, 16 May 2022 11:25:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245043AbiEPPYs (ORCPT ); Mon, 16 May 2022 11:24:48 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C38363981A; Mon, 16 May 2022 08:24:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652714686; x=1684250686; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8WYG3L+/ZLBYQzxHuNKO8Y9ASS/A40+pgEOz9qkoAFA=; b=E7H3WF7LGK9xonMU5zWDaBbLkGGq5ONOhkWDBeXMaxZmtkkNGw3ehmBS HAPNXBPQ4n5UhPbcHZHp2llR7h+dtF40ZkywScqOAr08Sn9THxhFxoAj/ Kq7t7PQtxIB1zpSvFoYwLsgCXt5TX4CmbaA86wATr3r/enkDepOwiJo3y FcjgC/oOycgBUJ6fM+CBJsFPobyO/YApkCkRhXBUz2xMz1VUT+lYRbZCJ 4toEb3X5wgWRmGCdjIDWnXjKKuFVCd7doDUNwS8jEHiREbHXEkZUUiZV+ sjrq1V1gZP3ZgiBWdkfjVqriV4IcH3Hhli00GPD4R4yHGt8WGjyn5Xbbf A==; X-IronPort-AV: E=McAfee;i="6400,9594,10349"; a="270561301" X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="270561301" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 08:24:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,230,1647327600"; d="scan'208";a="741290220" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga005.jf.intel.com with ESMTP; 16 May 2022 08:24:43 -0700 From: kan.liang@linux.intel.com To: acme@kernel.org, mingo@redhat.com, irogers@google.com, jolsa@kernel.org, namhyung@kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: peterz@infradead.org, zhengjun.xing@linux.intel.com, adrian.hunter@intel.com, ak@linux.intel.com, eranian@google.com, Kan Liang Subject: [PATCH V2 4/4] perf parse-events: Move slots event for the hybrid platform too Date: Mon, 16 May 2022 08:24:36 -0700 Message-Id: <20220516152436.1104757-5-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220516152436.1104757-1-kan.liang@linux.intel.com> References: <20220516152436.1104757-1-kan.liang@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kan Liang The commit 94dbfd6781a0 ("perf parse-events: Architecture specific leader override") introduced a feature to reorder the slots event to fulfill the restriction of the perf metrics topdown group. But the feature doesn't work on the hybrid machine. $perf stat -e "{cpu_core/instructions/,cpu_core/slots/,cpu_core/topdown-ret= iring/}" -a sleep 1 Performance counter stats for 'system wide': cpu_core/instructions/ cpu_core/slots/ cpu_core/topdown-retiring/ 1.002871801 seconds time elapsed A hybrid platform has a different PMU name for the core PMUs, while current perf hard code the PMU name "cpu". Introduce a new function to check whether the system supports the perf metrics feature. The result is cached for the future usage. For X86, the core PMU name always has "cpu" prefix. With the patch, $perf stat -e "{cpu_core/instructions/,cpu_core/slots/,cpu_core/topdown-ret= iring/}" -a sleep 1 Performance counter stats for 'system wide': 76,337,010 cpu_core/slots/ 10,416,809 cpu_core/instructions/ 11,692,372 cpu_core/topdown-retiring/ 1.002805453 seconds time elapsed Signed-off-by: Kan Liang Reviewed-by: Ian Rogers --- tools/perf/arch/x86/util/evlist.c | 5 +++-- tools/perf/arch/x86/util/topdown.c | 24 ++++++++++++++++++++++++ tools/perf/arch/x86/util/topdown.h | 7 +++++++ 3 files changed, 34 insertions(+), 2 deletions(-) create mode 100644 tools/perf/arch/x86/util/topdown.h diff --git a/tools/perf/arch/x86/util/evlist.c b/tools/perf/arch/x86/util/e= vlist.c index 75564a7df15b..68f681ad54c1 100644 --- a/tools/perf/arch/x86/util/evlist.c +++ b/tools/perf/arch/x86/util/evlist.c @@ -3,6 +3,7 @@ #include "util/pmu.h" #include "util/evlist.h" #include "util/parse-events.h" +#include "topdown.h" =20 #define TOPDOWN_L1_EVENTS "{slots,topdown-retiring,topdown-bad-spec,topdow= n-fe-bound,topdown-be-bound}" #define TOPDOWN_L2_EVENTS "{slots,topdown-retiring,topdown-bad-spec,topdow= n-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown= -fetch-lat,topdown-mem-bound}" @@ -25,12 +26,12 @@ struct evsel *arch_evlist__leader(struct list_head *lis= t) =20 first =3D list_first_entry(list, struct evsel, core.node); =20 - if (!pmu_have_event("cpu", "slots")) + if (!topdown_sys_has_perf_metrics()) return first; =20 /* If there is a slots event and a topdown event then the slots event com= es first. */ __evlist__for_each_entry(list, evsel) { - if (evsel->pmu_name && !strcmp(evsel->pmu_name, "cpu") && evsel->name) { + if (evsel->pmu_name && !strncmp(evsel->pmu_name, "cpu", 3) && evsel->nam= e) { if (strcasestr(evsel->name, "slots")) { slots =3D evsel; if (slots =3D=3D first) diff --git a/tools/perf/arch/x86/util/topdown.c b/tools/perf/arch/x86/util/= topdown.c index 2f3d96aa92a5..5e86859279e3 100644 --- a/tools/perf/arch/x86/util/topdown.c +++ b/tools/perf/arch/x86/util/topdown.c @@ -3,6 +3,30 @@ #include "api/fs/fs.h" #include "util/pmu.h" #include "util/topdown.h" +#include "topdown.h" + +bool topdown_sys_has_perf_metrics(void) +{ + static bool has_perf_metrics; + static bool cached; + struct perf_pmu *pmu; + + if (cached) + return has_perf_metrics; + + /* + * The perf metrics feature is a core PMU feature. + * The PERF_TYPE_RAW type is the type of a core PMU. + * The slots event is only available when the core PMU + * supports the perf metrics feature. + */ + pmu =3D perf_pmu__find_by_type(PERF_TYPE_RAW); + if (pmu && pmu_have_event(pmu->name, "slots")) + has_perf_metrics =3D true; + + cached =3D true; + return has_perf_metrics; +} =20 /* * Check whether we can use a group for top down. diff --git a/tools/perf/arch/x86/util/topdown.h b/tools/perf/arch/x86/util/= topdown.h new file mode 100644 index 000000000000..46bf9273e572 --- /dev/null +++ b/tools/perf/arch/x86/util/topdown.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _TOPDOWN_H +#define _TOPDOWN_H 1 + +bool topdown_sys_has_perf_metrics(void); + +#endif --=20 2.35.1