From nobody Fri May 8 00:59:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D590CC433F5 for ; Sat, 14 May 2022 21:54:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235507AbiENVyq (ORCPT ); Sat, 14 May 2022 17:54:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232773AbiENVyi (ORCPT ); Sat, 14 May 2022 17:54:38 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7882D2D1C2 for ; Sat, 14 May 2022 14:54:37 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id x52so10712042pfu.11 for ; Sat, 14 May 2022 14:54:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=C2DejTEs/G7g9L2HVWAQLqleNJVMCZ79v0p5bSTaL+I=; b=bEFJRheZ5CtaK8DaE9zGXXSJQ/B7kTpXgaQEdz3gcqwXAQX6MlqAjOAVlzUQlchnTA lb9GLi3Kz8PnLqraIkH/wW8fhTiLX8IMCCA4nMnA+01uGMaLxLGQiFf6WBMBvC+k1DFQ w5gM5s3Ojhg37ouCckXlHgp6++k0m5zekizu+ixECdk+aZ99JOtn0BCfNuWe1rDuY2MP 8LBRxjN4oRxJOyfvdSjR2MyCIKP7T4GeG04rKKpkz1v3FjDpBJf7tdxGKYI+nD5/0gfL Y8Jqli7eZ9uJy+LTqxzrR66vzbzpOIpKD/XEwa+oEDbOAJMzPGw6YWWpiuKIiaVWVxmR K0gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C2DejTEs/G7g9L2HVWAQLqleNJVMCZ79v0p5bSTaL+I=; b=1ZxOnkWXhvgXghvN9y5kyojYh0oFQOpDAVaMWIvVeJB4CJjVqhLMfIHPeFXKLbeGuF rjhESVi5PszG2CxrvETx7J38DH2nokpt0L+9+dkXelN7Cbjpgza2xB5Qlu8osPjNmkWZ nL/oOEKEs+N+YRR2K+7mWxtXnI3nifwDAvLUTVPzA4KcQYhvmneNqemwnGZqc+PIx5OJ Zt0J9q6+PR4bw1u4Hs3TEDU2lySQMEofiHW/105m5VVXTch+R7OYNL2G0g5dKZz96E5s vbFt7SWQGhqTTO3DM+YYWhK54UMnKFQLi5QsSb50GQpnEaxUodWc8NoivrCfC910HPHH ZJhg== X-Gm-Message-State: AOAM530dn5QhIFdwlsW1fSkvFeGctLl2IMomJhzqbBWwKLEht1/YiV4h JOtK9aNNYu4GJZyV5y4kW4HaIQ== X-Google-Smtp-Source: ABdhPJx+o1kUJpsunVsUYsCcgQPJ16ilKAd82HNUSU9Fc2RL1W6eMa9R7hPL/Z8oVOO+6u4Mii4lcw== X-Received: by 2002:a65:6051:0:b0:39d:1b00:e473 with SMTP id a17-20020a656051000000b0039d1b00e473mr9186783pgp.578.1652565276712; Sat, 14 May 2022 14:54:36 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c60:931c:dd30:fa99:963:d0be]) by smtp.gmail.com with ESMTPSA id m13-20020a170902db0d00b0015e8d4eb2d2sm4189522plx.284.2022.05.14.14.54.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 14:54:36 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Subject: [PATCH v2 1/6] arm64: dts: qcom: Fix sdhci node names - use 'mmc@' Date: Sun, 15 May 2022 03:24:19 +0530 Message-Id: <20220514215424.1007718-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> References: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports issues with inconsistent 'sdhci@' convention used for specifying the sdhci nodes. The generic mmc bindings expect 'mmc@' format instead. Fix the same. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++-- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8226.dtsi | 6 +++--- arch/arm/boot/dts/qcom-msm8974.dtsi | 6 +++--- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8953.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 21 files changed, 35 insertions(+), 35 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-a= pq8084.dtsi index da50a1a0197f..ca630ca2d9cd 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -419,7 +419,7 @@ blsp2_uart2: serial@f995e000 { status =3D "disabled"; }; =20 - sdhci@f9824900 { + mmc@f9824900 { compatible =3D "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names =3D "hc_mem", "core_mem"; @@ -432,7 +432,7 @@ sdhci@f9824900 { status =3D "disabled"; }; =20 - sdhci@f98a4900 { + mmc@f98a4900 { compatible =3D "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names =3D "hc_mem", "core_mem"; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-i= pq4019.dtsi index c5da723f7674..a2632349cec4 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -221,7 +221,7 @@ vqmmc: regulator@1948000 { status =3D "disabled"; }; =20 - sdhci: sdhci@7824900 { + sdhci: mmc@7824900 { compatible =3D "qcom,sdhci-msm-v4"; reg =3D <0x7824900 0x11c>, <0x7824000 0x800>; interrupts =3D , ; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-m= sm8226.dtsi index 28eca15b5712..0b5effdb269a 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -134,7 +134,7 @@ apcs: syscon@f9011000 { reg =3D <0xf9011000 0x1000>; }; =20 - sdhc_1: sdhci@f9824900 { + sdhc_1: mmc@f9824900 { compatible =3D "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names =3D "hc_mem", "core_mem"; @@ -150,7 +150,7 @@ sdhc_1: sdhci@f9824900 { status =3D "disabled"; }; =20 - sdhc_2: sdhci@f98a4900 { + sdhc_2: mmc@f98a4900 { compatible =3D "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names =3D "hc_mem", "core_mem"; @@ -166,7 +166,7 @@ sdhc_2: sdhci@f98a4900 { status =3D "disabled"; }; =20 - sdhc_3: sdhci@f9864900 { + sdhc_3: mmc@f9864900 { compatible =3D "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9864900 0x11c>, <0xf9864000 0x800>; reg-names =3D "hc_mem", "core_mem"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-m= sm8974.dtsi index 814ad0b46232..637877e5c5d8 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -436,7 +436,7 @@ acc3: clock-controller@f90b8000 { reg =3D <0xf90b8000 0x1000>, <0xf9008000 0x1000>; }; =20 - sdhc_1: sdhci@f9824900 { + sdhc_1: mmc@f9824900 { compatible =3D "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names =3D "hc_mem", "core_mem"; @@ -453,7 +453,7 @@ sdhc_1: sdhci@f9824900 { status =3D "disabled"; }; =20 - sdhc_3: sdhci@f9864900 { + sdhc_3: mmc@f9864900 { compatible =3D "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9864900 0x11c>, <0xf9864000 0x800>; reg-names =3D "hc_mem", "core_mem"; @@ -472,7 +472,7 @@ sdhc_3: sdhci@f9864900 { status =3D "disabled"; }; =20 - sdhc_2: sdhci@f98a4900 { + sdhc_2: mmc@f98a4900 { compatible =3D "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names =3D "hc_mem", "core_mem"; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx= 55.dtsi index 1c2b208a5670..4c76c7758637 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -388,7 +388,7 @@ tcsr: syscon@1fcb000 { reg =3D <0x01fc0000 0x1000>; }; =20 - sdhc_1: sdhci@8804000 { + sdhc_1: mmc@8804000 { compatible =3D "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x08804000 0x1000>; interrupts =3D , diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx= 65.dtsi index df6f9d6288fe..5b8e8620a1e1 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -143,7 +143,7 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells =3D <1>; }; =20 - sdhc_1: sdhci@8804000 { + sdhc_1: mmc@8804000 { compatible =3D "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x08804000 0x1000>; reg-names =3D "hc_mem"; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qc= om/ipq8074.dtsi index 4c38b15c6fd4..9dff30c8fc85 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -375,7 +375,7 @@ spmi_bus: spmi@200f000 { cell-index =3D <0>; }; =20 - sdhc_1: sdhci@7824900 { + sdhc_1: mmc@7824900 { compatible =3D "qcom,sdhci-msm-v4"; reg =3D <0x7824900 0x500>, <0x7824000 0x800>; reg-names =3D "hc_mem", "core_mem"; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qc= om/msm8916.dtsi index 05472510e29d..aadefb38a7cf 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1464,7 +1464,7 @@ lpass_codec: audio-codec@771c000 { #sound-dai-cells =3D <1>; }; =20 - sdhc_1: sdhci@7824000 { + sdhc_1: mmc@7824000 { compatible =3D "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x07824900 0x11c>, <0x07824000 0x800>; reg-names =3D "hc_mem", "core_mem"; @@ -1482,7 +1482,7 @@ sdhc_1: sdhci@7824000 { status =3D "disabled"; }; =20 - sdhc_2: sdhci@7864000 { + sdhc_2: mmc@7864000 { compatible =3D "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x07864900 0x11c>, <0x07864000 0x800>; reg-names =3D "hc_mem", "core_mem"; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qc= om/msm8953.dtsi index ffc3ec2cd3bc..1bc0ef476cdb 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -795,7 +795,7 @@ usb3_dwc3: usb@7000000 { }; }; =20 - sdhc_1: sdhci@7824900 { + sdhc_1: mmc@7824900 { compatible =3D "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; =20 reg =3D <0x7824900 0x500>, <0x7824000 0x800>; @@ -855,7 +855,7 @@ opp-384000000 { }; }; =20 - sdhc_2: sdhci@7864900 { + sdhc_2: mmc@7864900 { compatible =3D "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; =20 reg =3D <0x7864900 0x500>, <0x7864000 0x800>; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qc= om/msm8994.dtsi index 0318d42c5736..99230e8d643f 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -461,7 +461,7 @@ usb@f9200000 { }; }; =20 - sdhc1: sdhci@f9824900 { + sdhc1: mmc@f9824900 { compatible =3D "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf9824900 0x1a0>, <0xf9824000 0x800>; reg-names =3D "hc_mem", "core_mem"; @@ -484,7 +484,7 @@ sdhc1: sdhci@f9824900 { status =3D "disabled"; }; =20 - sdhc2: sdhci@f98a4900 { + sdhc2: mmc@f98a4900 { compatible =3D "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names =3D "hc_mem", "core_mem"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qc= om/msm8996.dtsi index 9932186f7ceb..e6fa71f14240 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2804,7 +2804,7 @@ hsusb_phy2: phy@7412000 { status =3D "disabled"; }; =20 - sdhc1: sdhci@7464900 { + sdhc1: mmc@7464900 { compatible =3D "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x07464900 0x11c>, <0x07464000 0x800>; reg-names =3D "hc_mem", "core_mem"; @@ -2827,7 +2827,7 @@ sdhc1: sdhci@7464900 { status =3D "disabled"; }; =20 - sdhc2: sdhci@74a4900 { + sdhc2: mmc@74a4900 { compatible =3D "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg =3D <0x074a4900 0x314>, <0x074a4000 0x800>; reg-names =3D "hc_mem", "core_mem"; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qc= om/msm8998.dtsi index 758c45bbbe78..a49a13441661 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2102,7 +2102,7 @@ qusb2phy: phy@c012000 { nvmem-cells =3D <&qusb2_hstx_trim>; }; =20 - sdhc2: sdhci@c0a4900 { + sdhc2: mmc@c0a4900 { compatible =3D "qcom,sdhci-msm-v4"; reg =3D <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; reg-names =3D "hc_mem", "core_mem"; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qco= m/qcs404.dtsi index d912166b7552..97c4e6c6f6c8 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -789,7 +789,7 @@ pcie_phy: phy@7786000 { status =3D "disabled"; }; =20 - sdcc1: sdcc@7804000 { + sdcc1: mmc@7804000 { compatible =3D "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, <0x7805000 0x1000>; reg-names =3D "hc", "cqhci"; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index 5dcaac23a138..4a316c50484d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -693,7 +693,7 @@ gpu_speed_bin: gpu_speed_bin@1d2 { }; }; =20 - sdhc_1: sdhci@7c4000 { + sdhc_1: mmc@7c4000 { compatible =3D "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0 0x7c4000 0 0x1000>, <0 0x07c5000 0 0x1000>; @@ -2578,7 +2578,7 @@ apss_merge_funnel_in: endpoint { }; }; =20 - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible =3D "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0 0x08804000 0 0x1000>; =20 diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index e66fc67de206..f1e86effa063 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -857,7 +857,7 @@ gpu_speed_bin: gpu_speed_bin@1e9 { }; }; =20 - sdhc_1: sdhci@7c4000 { + sdhc_1: mmc@7c4000 { compatible =3D "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; @@ -2936,7 +2936,7 @@ apss_merge_funnel_in: endpoint { }; }; =20 - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible =3D "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qco= m/sdm630.dtsi index b72e8e6c52f3..cadc920bcd9c 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1272,7 +1272,7 @@ qusb2phy: phy@c012000 { status =3D "disabled"; }; =20 - sdhc_2: sdhci@c084000 { + sdhc_2: mmc@c084000 { compatible =3D "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x0c084000 0x1000>; reg-names =3D "hc"; @@ -1322,7 +1322,7 @@ opp-200000000 { }; }; =20 - sdhc_1: sdhci@c0c4000 { + sdhc_1: mmc@c0c4000 { compatible =3D "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x0c0c4000 0x1000>, <0x0c0c5000 0x1000>, diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 0692ae0e60a4..85baec57b993 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3551,7 +3551,7 @@ apss_merge_funnel_in: endpoint { }; }; =20 - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible =3D "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0 0x08804000 0 0x1000>; =20 diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qco= m/sm6125.dtsi index 135e6e0da27a..77bff81af433 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -435,7 +435,7 @@ rpm_msg_ram: sram@45f0000 { reg =3D <0x045f0000 0x7000>; }; =20 - sdhc_1: sdhci@4744000 { + sdhc_1: mmc@4744000 { compatible =3D "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x04744000 0x1000>, <0x04745000 0x1000>; reg-names =3D "hc", "core"; @@ -456,7 +456,7 @@ sdhc_1: sdhci@4744000 { status =3D "disabled"; }; =20 - sdhc_2: sdhci@4784000 { + sdhc_2: mmc@4784000 { compatible =3D "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x04784000 0x1000>; reg-names =3D "hc"; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index d4f8f33f3f0c..13c7ae2e379e 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -472,7 +472,7 @@ rng: rng@793000 { clock-names =3D "core"; }; =20 - sdhc_1: sdhci@7c4000 { + sdhc_1: mmc@7c4000 { compatible =3D "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0 0x007c4000 0 0x1000>, <0 0x007c5000 0 0x1000>, @@ -921,7 +921,7 @@ compute-cb@8 { }; }; =20 - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible =3D "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0 0x08804000 0 0x1000>; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 8ea44c4b56b4..a2a1c77c0428 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3543,7 +3543,7 @@ usb_2_ssphy: phy@88eb200 { }; }; =20 - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible =3D "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0 0x08804000 0 0x1000>; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index cf0c97bd5ad3..6c06e3b2ad2d 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2917,7 +2917,7 @@ usb_2_ssphy: phy@88eb200 { }; }; =20 - sdhc_2: sdhci@8804000 { + sdhc_2: mmc@8804000 { compatible =3D "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0 0x08804000 0 0x1000>; =20 --=20 2.35.3 From nobody Fri May 8 00:59:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1402BC433EF for ; Sat, 14 May 2022 21:54:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235495AbiENVyw (ORCPT ); Sat, 14 May 2022 17:54:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235498AbiENVyl (ORCPT ); Sat, 14 May 2022 17:54:41 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EA602D1DC for ; Sat, 14 May 2022 14:54:40 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id a11so10761281pff.1 for ; Sat, 14 May 2022 14:54:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iVHLE0FSagaU/6sD2J6a+GPzkzj/n/6jKnq+SCiWCmE=; b=IJfTXbvryw4AOaqheyB6aks6Uqee2W4Vcx70IGzPZ8a55Ny4CH71weNSkvbqBAv3lH kneSd9V4aNcyl8fvtwp/oDN63xavWRhovZbFzXKLXTOFAWWN++RA2cnZeDVs9yhqNJUh CqBi0uBDUnx0E4d3FXGPio7BXeP5esbQw2l3MtjZgHhVLNK1bRfrFlyT3dQ2aRgwnJGt 4HEXKm1J0NDUFnffMn6WQzHfoEXcXRLPQMpyZIGNVM9X6NU1HRBqHlQ5nXEfCaewY3Kn jduWHsElj/dKW9xwLR2GkKmQuaPG6vFQ3IVikCcGRWb+SfTy+xzhVK6sIfH3tj9jG+v8 dXhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iVHLE0FSagaU/6sD2J6a+GPzkzj/n/6jKnq+SCiWCmE=; b=LqHbVyUsElH4NWCNx8O1dkAaXE0thAAyuYb6M1JN+ksmBCfagR85+Msw21jcIFH7dQ SBG14fV0vniI+Sw7Hb2o2B4sGphSz95d0ngVamrwb508rH1n5IxAhQ8Rg9ade8e4oPjl zwXdiDBUmHdLpwM7xkkspG/k030yZp5qU+Lw7OKVeuxvV+fmHyik8+3m7zrw84GkEyvF vuKpsfH9lq+5wCpinitl/USdWYjlY/9G1mVaADYaVA6tpNte7Z3wUnLpRsBv4iRwxQKq WsTswTVyMVhtfKdthEXuVQNedDKH14XFZJ1vZTk4Pwswim408Pfs9NzHHDIeElykAstQ fMFw== X-Gm-Message-State: AOAM532vULT+daQ8Ck80I3sjVtvNNktyigWvY3I6XC/fOx7G+x14xajV Xa7UJtlzlvmJA9i7seg4nQjkJA== X-Google-Smtp-Source: ABdhPJz1bGqQv7MnwByvRME1qtAsZA8IMh4C+YpU2vxO34U/+WpSRQNWYMgR4YDBYtU+ns2qAtcONQ== X-Received: by 2002:a63:87c6:0:b0:3c6:a7d9:5d01 with SMTP id i189-20020a6387c6000000b003c6a7d95d01mr9433225pge.341.1652565279662; Sat, 14 May 2022 14:54:39 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c60:931c:dd30:fa99:963:d0be]) by smtp.gmail.com with ESMTPSA id m13-20020a170902db0d00b0015e8d4eb2d2sm4189522plx.284.2022.05.14.14.54.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 14:54:39 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Subject: [PATCH v2 2/6] arm64: dts: qcom: sdm630: Fix 'interconnect-names' for sdhci nodes Date: Sun, 15 May 2022 03:24:20 +0530 Message-Id: <20220514215424.1007718-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> References: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports issues with inconsistent 'interconnect-names' used for sdhci nodes. Fix the same. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qco= m/sdm630.dtsi index cadc920bcd9c..34b177f0ce87 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1289,6 +1289,7 @@ sdhc_2: mmc@c084000 { =20 interconnects =3D <&a2noc 3 &a2noc 10>, <&gnoc 0 &cnoc 28>; + interconnect-names =3D "sdhc-ddr","cpu-sdhc"; operating-points-v2 =3D <&sdhc2_opp_table>; =20 pinctrl-names =3D "default", "sleep"; @@ -1341,7 +1342,7 @@ sdhc_1: mmc@c0c4000 { =20 interconnects =3D <&a2noc 2 &a2noc 10>, <&gnoc 0 &cnoc 27>; - interconnect-names =3D "sdhc1-ddr", "cpu-sdhc1"; + interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; operating-points-v2 =3D <&sdhc1_opp_table>; pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&sdc1_state_on>; --=20 2.35.3 From nobody Fri May 8 00:59:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94A8DC433EF for ; Sat, 14 May 2022 21:55:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235617AbiENVzD (ORCPT ); Sat, 14 May 2022 17:55:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235472AbiENVyp (ORCPT ); Sat, 14 May 2022 17:54:45 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CA992DA8B for ; Sat, 14 May 2022 14:54:43 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id c11so11082076plg.13 for ; Sat, 14 May 2022 14:54:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O72LBqaBFc3QSphttd7j5vD07NYu+1pVVzRqZ3jA530=; b=XOB+7ikRInJ7Du/5GtJxUlkB867+ZRSPT5Dz2hhhg0k2WjxRSHAIENr7qNLeT47k+n E76coTOYrLRpq6fg9FtfYAT0AF0glIkuCH8GDt/wr/5Z2psiyl/6buWoMlTQSQsU+PTW FlZtyIApdLLIiR1l1GAFT3ciNQpZbh7gdsdiBkLFSrToi2Wt4CrIfcJvdBFvNyPaQAWh 6P+jovj2qRdX8rmU13jGZYBBClN64SWk5iGMu9YqrfXoDDMHpvSLQpCb3khXEkGxDlHf uzxXAYOsan7qdWDzeOS9xZUq1pMcmXwT9HHzJWefY0Gcx1NQOLNIwsI+5pRlr5YV+I6N pZDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O72LBqaBFc3QSphttd7j5vD07NYu+1pVVzRqZ3jA530=; b=BQQvHbwsZgpkJB6R1Z43pvIC0JwBUShIRyEYpsDrrRsX5eA8Jf3LC6xQgQ4QNCa3l2 e1rr6qESeHDU5Hw5VFpNBE9ZrBFKmNdYO3EzMeAdS8+LHnDMdL14ik1kdg7+Mdt+5bUZ ijA18ZcoUA6xqIJJ2mLojQlwU/r7s8jxFGwOtHc8kR1Zm7NjCLfRjyLZtjgVAs0s/1vh ZDXm8ulam3mtvaVN+LzVViaUUsSJjiUTNhI/iI5Yv48BNgZkcQHZ4HIK5+UsMH1Cd7Ha doS6Hh4wUO/+qX8VcO9TxAx6PXt3KhFBy91feETOLh58NHM8yXJ7nkK3toZymSG77NJb ksGw== X-Gm-Message-State: AOAM531S5L9vQZZ7us8ud9/VmmCbjJ502LbkIWuS0YF3SOltKQSVHxMh NhvwDujHQgVZFBDqWsKNESMnWA== X-Google-Smtp-Source: ABdhPJxta0ttPlx6u9EiYauwEqUf9ORkOUSmcltYCes1vNyn8VyCN172pppcdA8Yj5J4DD/BmkelbA== X-Received: by 2002:a17:90b:1d11:b0:1dc:5dd1:b50e with SMTP id on17-20020a17090b1d1100b001dc5dd1b50emr22496454pjb.218.1652565282989; Sat, 14 May 2022 14:54:42 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c60:931c:dd30:fa99:963:d0be]) by smtp.gmail.com with ESMTPSA id m13-20020a170902db0d00b0015e8d4eb2d2sm4189522plx.284.2022.05.14.14.54.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 14:54:42 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Subject: [PATCH v2 3/6] arm64: dts: qcom: Fix node names for sdhci 'opp-table' nodes (across dts files) Date: Sun, 15 May 2022 03:24:21 +0530 Message-Id: <20220514215424.1007718-4-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> References: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports a number of issues with node names for sdhci 'opp-table' nodes, as it doesn't seem to like any 'preceding text or numbers' before 'opp-table' pattern in the node names. Fix the same. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm6350.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index 4a316c50484d..df0006d4a560 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -725,7 +725,7 @@ sdhc_1: mmc@7c4000 { =20 status =3D "disabled"; =20 - sdhc1_opp_table: sdhc1-opp-table { + sdhc1_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 opp-100000000 { @@ -2602,7 +2602,7 @@ sdhc_2: mmc@8804000 { =20 status =3D "disabled"; =20 - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 opp-100000000 { diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 13c7ae2e379e..1b1eb884136b 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -497,7 +497,7 @@ sdhc_1: mmc@7c4000 { =20 status =3D "disabled"; =20 - sdhc1_opp_table: sdhc1-opp-table { + sdhc1_opp_table: opp-table-sdhc1 { compatible =3D "operating-points-v2"; =20 opp-19200000 { @@ -941,7 +941,7 @@ sdhc_2: mmc@8804000 { =20 status =3D "disabled"; =20 - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table-sdhc2 { compatible =3D "operating-points-v2"; =20 opp-100000000 { diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index a2a1c77c0428..e6b309e9c05b 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3563,7 +3563,7 @@ sdhc_2: mmc@8804000 { =20 status =3D "disabled"; =20 - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 opp-19200000 { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 6c06e3b2ad2d..9b6dea34cd69 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2937,7 +2937,7 @@ sdhc_2: mmc@8804000 { =20 status =3D "disabled"; =20 - sdhc2_opp_table: sdhc2-opp-table { + sdhc2_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 opp-19200000 { --=20 2.35.3 From nobody Fri May 8 00:59:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C5CBC433FE for ; Sat, 14 May 2022 21:55:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235695AbiENVzS (ORCPT ); Sat, 14 May 2022 17:55:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235535AbiENVys (ORCPT ); Sat, 14 May 2022 17:54:48 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0288F2DAB2 for ; Sat, 14 May 2022 14:54:46 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id s14so11113233plk.8 for ; Sat, 14 May 2022 14:54:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0NA8yQhD9uR4XpE+J5Tv4lK1OtXwMbiM19OGeD+Yvc0=; b=dQueLe2E+xIqElBrLZerlL3uK1Z/T4RUfWioJIsqqx8MMqJ++If+Mf5+bWcxzLyuJP cTZHXuROgDnqv0ybm4TB/sN2em9hSgXl24fI3MA49Qvf+CpWeOnUsE/On9UNI/Bl+bF9 n/LeYNk5H5LWQ+6xvbQ2FGeEf8S3XAdaz1NYIWPhJnJEz3Iag37PKbNheecJAzPEbJn2 0JYNnnO2QPyq0FLm61BiZR/uaNP3gL9bY3jYw3E/S2i9uManLW9HcLpag7IJMpI6jv42 S1htLABUxqh+MhqZJ7qbOobVqJEYOnZK+2sLrglKF7E1C0CH2NpjNXxnY1jYauzR2NX4 JCVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0NA8yQhD9uR4XpE+J5Tv4lK1OtXwMbiM19OGeD+Yvc0=; b=jewD+5iXlOzGQ4h8PiJm8Z/W6LoQP5ZMdN8bp32B8uSPCUt9KnqA1vLIy8gWI3953Z DUUsYx9xjGq2DXAw0VmkkR6pGTI5q45LitgMU/DgZ0OKQSqyDfBrBb0oXIlu/Xw9irgE qlTpoRF6J7W5cFZ52NUSYgNp0/5bdeK3iFmkBUZph9IyApBTBahTMfBDv8fauTZoVOCB iFbqnS3pm7dAkGgA36lWAXEKF21Dk3fvpDXe2JvxGiDynbexvPfNdGChMokI44Yrdi0y gTigO48iX6D4XanO5IsQ+wJ0/8Pk7xjtK46RsIzFtlAn1jkyEgqDFdMTqLrDqnrkRe/K kAig== X-Gm-Message-State: AOAM531SHYnCuEqGl4Dlf8/1+rGDEF4u6jQVUYJLXFM0RiQUKtYDAeIW BuxJi+Mat2xGc4Uf6RLFQW+bsQ== X-Google-Smtp-Source: ABdhPJxqxWjzuEmAtKkxj7t14etkOzrua38LB0zf8b/2WCdpKJmVC6pfXiIznWNxn1hPVYZOCsxIfQ== X-Received: by 2002:a17:903:18a:b0:15e:c983:7c14 with SMTP id z10-20020a170903018a00b0015ec9837c14mr10689981plg.9.1652565286032; Sat, 14 May 2022 14:54:46 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c60:931c:dd30:fa99:963:d0be]) by smtp.gmail.com with ESMTPSA id m13-20020a170902db0d00b0015e8d4eb2d2sm4189522plx.284.2022.05.14.14.54.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 14:54:45 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Subject: [PATCH v2 4/6] arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names' for sdhci nodes Date: Sun, 15 May 2022 03:24:22 +0530 Message-Id: <20220514215424.1007718-5-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> References: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports a number of issues with ordering of 'clocks' & 'clock-names' for sdhci nodes: arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900: clock-names:0: 'iface' was expected arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900: clock-names:1: 'core' was expected arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900: clock-names:2: 'xo' was expected Fix the same by updating the offending 'dts' files. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/msm8916.dtsi | 12 ++++++------ arch/arm64/boot/dts/qcom/msm8994.dtsi | 14 +++++++------- arch/arm64/boot/dts/qcom/qcs404.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sc7180.dtsi | 12 ++++++------ arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 ++++++------ arch/arm64/boot/dts/qcom/sdm630.dtsi | 14 ++++++++------ 7 files changed, 40 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qc= om/ipq8074.dtsi index 9dff30c8fc85..ab2a1e7955b5 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -384,10 +384,10 @@ sdhc_1: mmc@7824900 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&xo>, - <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>; - clock-names =3D "xo", "iface", "core"; + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>; + clock-names =3D "iface", "core", "xo"; max-frequency =3D <384000000>; mmc-ddr-1_8v; mmc-hs200-1_8v; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qc= om/msm8916.dtsi index aadefb38a7cf..9cd7c625d331 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1472,10 +1472,10 @@ sdhc_1: mmc@7824000 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; mmc-ddr-1_8v; bus-width =3D <8>; non-removable; @@ -1490,10 +1490,10 @@ sdhc_2: mmc@7864000 { interrupts =3D , ; interrupt-names =3D "hc_irq", "pwr_irq"; - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; bus-width =3D <4>; status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qc= om/msm8994.dtsi index 99230e8d643f..362960d3fd18 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -470,10 +470,10 @@ sdhc1: mmc@f9824900 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; =20 pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; @@ -493,10 +493,10 @@ sdhc2: mmc@f98a4900 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, - <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names =3D "iface", "core", "xo"; =20 pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qco= m/qcs404.dtsi index 97c4e6c6f6c8..86dbf8ea04bc 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -798,10 +798,10 @@ sdcc1: mmc@7804000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; =20 status =3D "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index df0006d4a560..9076892ff4f8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -704,10 +704,10 @@ sdhc_1: mmc@7c4000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; interconnects =3D <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; interconnect-names =3D "sdhc-ddr","cpu-sdhc"; @@ -2587,10 +2587,10 @@ sdhc_2: mmc@8804000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; =20 interconnects =3D <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index f1e86effa063..e63d1a4499f8 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -873,10 +873,10 @@ sdhc_1: mmc@7c4000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; interconnects =3D <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; interconnect-names =3D "sdhc-ddr","cpu-sdhc"; @@ -2950,10 +2950,10 @@ sdhc_2: mmc@8804000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; interconnects =3D <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; interconnect-names =3D "sdhc-ddr","cpu-sdhc"; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qco= m/sdm630.dtsi index 34b177f0ce87..6d872e2f400a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1282,10 +1282,12 @@ sdhc_2: mmc@c084000 { interrupt-names =3D "hc_irq", "pwr_irq"; =20 bus-width =3D <4>; - clocks =3D <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>, + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, <&xo_board>; - clock-names =3D "core", "iface", "xo"; + clock-names =3D "iface", "core", "xo"; + =20 interconnects =3D <&a2noc 3 &a2noc 10>, <&gnoc 0 &cnoc 28>; @@ -1334,11 +1336,11 @@ sdhc_1: mmc@c0c4000 { ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 - clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>, + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, <&xo_board>, <&gcc GCC_SDCC1_ICE_CORE_CLK>; - clock-names =3D "core", "iface", "xo", "ice"; + clock-names =3D "iface", "core", "xo", "ice"; =20 interconnects =3D <&a2noc 2 &a2noc 10>, <&gnoc 0 &cnoc 27>; --=20 2.35.3 From nobody Fri May 8 00:59:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C068C43217 for ; Sat, 14 May 2022 21:55:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235555AbiENVzG (ORCPT ); Sat, 14 May 2022 17:55:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235579AbiENVyy (ORCPT ); Sat, 14 May 2022 17:54:54 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E9E22D1CD for ; Sat, 14 May 2022 14:54:50 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id m12so11120258plb.4 for ; Sat, 14 May 2022 14:54:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EeKFz6FvEbcUusdgXpBLLDhoZhZgVhmRs6eLFHdjJY8=; b=o2ylwYfA7fGITDyeMgXr6IGTtlHc8oQwug7nspKDPwGbH25+kLzPeEx3d+B+RQBYiU ABQHsTn2umyC/kgr6ZXogHO1jqVsQi3nI+5gqgbHTQxjUhpfoDk5hQaCA63W087k5ViR w8JxP5LYcVVeKBoAulRUKCoVCIOqNxesUkvbTxy358dyD4xLsTeQc2dAaYwcGe2c8ZVO RD4sJc6qlg4EsWnXwoesfHb60mAuIayEBoPgpb2f/BBOF++cmAMG9nntMIYrAB3QZoQW 5uuj+80HxveyfRIkJT7FHvgkX3N5h7NGso1tlpRonYkK2ECm+4XlBA0k29CmTWp7gIfl /WEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EeKFz6FvEbcUusdgXpBLLDhoZhZgVhmRs6eLFHdjJY8=; b=uD+DL1dNjai6jbYX3Ga0Jy8kwIVFgnOH1qaSU5y9m7djU8bNEcEQWsLH8UJaKOIgW5 G0RlzUObQtQopU21g691CZVj4ZTD1no0iD55csSbhLnU66mS8sUjcXtzQU0s1puQvfbN hskjaiYerMKHgrS8BQPt+EfR/vYr9oGjyHZ3C4vkPD51KVGIZRaDcjWEBwhlH3TRPrpA jQx0ZV44rldd+oEeAYk930GBDohDcfyZ006Yr0mfAYTEBq4f+be2AkFAXDzhrrXz9DqZ MirFT/YXBPlPUrer6eWtt7N5MwQAhngfTet+H1LCribExmPi7Prc/UyNPKJnL29PhPI6 jDyg== X-Gm-Message-State: AOAM530iUnivuwZXIjwW/TMvuQG9/k7bwVSR8lWT9B3Fj8Lm+Qlqxe9X zDHzCi7NuoDA4kTh2sW07iwj7g== X-Google-Smtp-Source: ABdhPJyCpJgeUz2YbwGcAWQjqfF/PIggNj85gfy/wL4aiBjgTuGh36+Oe0W4a15vc8BYDL/sBBwbLw== X-Received: by 2002:a17:90b:38c4:b0:1dc:6b64:3171 with SMTP id nn4-20020a17090b38c400b001dc6b643171mr23366996pjb.168.1652565289065; Sat, 14 May 2022 14:54:49 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c60:931c:dd30:fa99:963:d0be]) by smtp.gmail.com with ESMTPSA id m13-20020a170902db0d00b0015e8d4eb2d2sm4189522plx.284.2022.05.14.14.54.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 14:54:48 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Subject: [PATCH v2 5/6] arm64: dts: qcom: Fix 'reg-names' for sdhci nodes Date: Sun, 15 May 2022 03:24:23 +0530 Message-Id: <20220514215424.1007718-6-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> References: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports a number of issues with ordering of 'reg-names' as various possible combinations are possible for different qcom SoC dts files. Fix the same by updating the offending 'dts' files. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm6125.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qco= m/qcs404.dtsi index 86dbf8ea04bc..45044083faf0 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -792,7 +792,7 @@ pcie_phy: phy@7786000 { sdcc1: mmc@7804000 { compatible =3D "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x07804000 0x1000>, <0x7805000 0x1000>; - reg-names =3D "hc", "cqhci"; + reg-names =3D "hc_mem", "cqe_mem"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index 9076892ff4f8..08f2decc7f4f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -697,7 +697,7 @@ sdhc_1: mmc@7c4000 { compatible =3D "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0 0x7c4000 0 0x1000>, <0 0x07c5000 0 0x1000>; - reg-names =3D "hc", "cqhci"; + reg-names =3D "hc_mem", "cqe_mem"; =20 iommus =3D <&apps_smmu 0x60 0x0>; interrupts =3D , diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index e63d1a4499f8..eaaccf0184af 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -866,7 +866,7 @@ sdhc_1: mmc@7c4000 { =20 reg =3D <0 0x007c4000 0 0x1000>, <0 0x007c5000 0 0x1000>; - reg-names =3D "hc", "cqhci"; + reg-names =3D "hc_mem", "cqe_mem"; =20 iommus =3D <&apps_smmu 0xc0 0x0>; interrupts =3D , diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qco= m/sdm630.dtsi index 6d872e2f400a..77dc985b3634 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1275,7 +1275,7 @@ qusb2phy: phy@c012000 { sdhc_2: mmc@c084000 { compatible =3D "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x0c084000 0x1000>; - reg-names =3D "hc"; + reg-names =3D "hc_mem"; =20 interrupts =3D , ; @@ -1330,7 +1330,7 @@ sdhc_1: mmc@c0c4000 { reg =3D <0x0c0c4000 0x1000>, <0x0c0c5000 0x1000>, <0x0c0c8000 0x8000>; - reg-names =3D "hc", "cqhci", "ice"; + reg-names =3D "hc_mem", "cqe_mem", "ice_mem"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qco= m/sm6125.dtsi index 77bff81af433..94e427abbfd2 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -438,7 +438,7 @@ rpm_msg_ram: sram@45f0000 { sdhc_1: mmc@4744000 { compatible =3D "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x04744000 0x1000>, <0x04745000 0x1000>; - reg-names =3D "hc", "core"; + reg-names =3D "hc_mem", "core_mem"; =20 interrupts =3D , ; @@ -459,7 +459,7 @@ sdhc_1: mmc@4744000 { sdhc_2: mmc@4784000 { compatible =3D "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x04784000 0x1000>; - reg-names =3D "hc"; + reg-names =3D "hc_mem"; =20 interrupts =3D , ; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index 1b1eb884136b..6d959aa0ea94 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -477,7 +477,7 @@ sdhc_1: mmc@7c4000 { reg =3D <0 0x007c4000 0 0x1000>, <0 0x007c5000 0 0x1000>, <0 0x007c8000 0 0x8000>; - reg-names =3D "hc", "cqhci", "ice"; + reg-names =3D "hc_mem", "cqe_mem", "ice_mem"; =20 interrupts =3D , ; --=20 2.35.3 From nobody Fri May 8 00:59:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03F73C433EF for ; Sat, 14 May 2022 21:55:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235605AbiENVzb (ORCPT ); Sat, 14 May 2022 17:55:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235531AbiENVyz (ORCPT ); Sat, 14 May 2022 17:54:55 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 727DC2E087 for ; Sat, 14 May 2022 14:54:52 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id l7-20020a17090aaa8700b001dd1a5b9965so10882917pjq.2 for ; Sat, 14 May 2022 14:54:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AAcG7rX+mEnMpt5XVNtu3dX5eVwzJDr7gAFJhDONIy0=; b=nxxzsvWzWEKNE3cxFqH6yQ4ICQZmVH8De5uCsd8WKaCkF6jZNyxQF5xp2Cu4Z3Dzl8 gJbC40QKZlyfSDBzP7QQzgfM4GYfhBAXQYZIgzZ80553VWgDCmhZTm9bT+D8PJugAiY0 s461rzBlWZa2DpQpth4RfHtw9NJiAJNadeEKnD1AoIoJka+YRClOtfVi6QQL7oJ2SygF Z7egm0LlDM5h00heNOLguU92IlCYP8AU5ZSjjFE9Lo0FOCyO4Eq0kbvuuHQKHAJT9hO8 lVD9KGn7KT9X1pfhdAXJoQNW+XU7Q2yZrVbRjh+BvUDtCdFUnKsJPdWJFt8w2hYG18kr Znrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AAcG7rX+mEnMpt5XVNtu3dX5eVwzJDr7gAFJhDONIy0=; b=QtzEvn2SkBmB117fZuw0t1D09ROdoXJjJrb7dcLNzaKSySII3VcMYIULntfAq6Y2eh xgKobPRL9IrJi7hsbv0bI9JvkOLMUdAgcRv2O+eN/pZV7Z+RjHw9DB4HW3o6M49vFLVK xzf10ED0nV9h9fV48s7js1VZgn6evQbv4AoL1Hx+v4CmWrG4jW5TlBdz6QLawC0J7HkN JWD4Rzr9p6Nl2RC1PRFXj8H5kb4cXzGziXmAxCmpGg2Bpzlvca71gtFK1674YvKxrCF1 Drr4PNzXq7TTwFsr3G1PFKjlTbDx8VGUwLr1dypbAHtPAFEYGxHAaxmXA9YDvJi6tIkb 2APw== X-Gm-Message-State: AOAM5336qcFDrZX31762Mgtuc0TFHGTq/jsza7jBis2yZP8P5ArVYkv0 cXd5jzAc7egeJiUaaGZNggq0Uw== X-Google-Smtp-Source: ABdhPJwCxPIfJBC5n04iupZetTYjVESBk39k3MQPbmK94RzqJnkiGQiafVLDjd5ZEzsWsUgXEY+e1Q== X-Received: by 2002:a17:903:40d1:b0:15e:f8ee:c278 with SMTP id t17-20020a17090340d100b0015ef8eec278mr10911956pld.100.1652565291841; Sat, 14 May 2022 14:54:51 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c60:931c:dd30:fa99:963:d0be]) by smtp.gmail.com with ESMTPSA id m13-20020a170902db0d00b0015e8d4eb2d2sm4189522plx.284.2022.05.14.14.54.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 14:54:51 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, bjorn.andersson@linaro.org, robh@kernel.org Subject: [PATCH v2 6/6] arm64: dts: qcom: ipq8074: Fix 'max-frequency' value for sdhci node Date: Sun, 15 May 2022 03:24:24 +0530 Message-Id: <20220514215424.1007718-7-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> References: <20220514215424.1007718-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports issues with 'max-frequency' value for ipq8074 sdhci node: arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb: mmc@7824900: max-frequency:0:0: 384000000 is greater than the maximum of 200000000 Fix the same. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qc= om/ipq8074.dtsi index ab2a1e7955b5..b2d71af9b419 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -388,7 +388,7 @@ sdhc_1: mmc@7824900 { <&gcc GCC_SDCC1_APPS_CLK>, <&xo>; clock-names =3D "iface", "core", "xo"; - max-frequency =3D <384000000>; + max-frequency =3D <200000000>; mmc-ddr-1_8v; mmc-hs200-1_8v; mmc-hs400-1_8v; --=20 2.35.3