From nobody Fri May 8 02:20:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F426C433F5 for ; Fri, 13 May 2022 01:55:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376426AbiEMBzn (ORCPT ); Thu, 12 May 2022 21:55:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376412AbiEMBzi (ORCPT ); Thu, 12 May 2022 21:55:38 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D5B828F1EF for ; Thu, 12 May 2022 18:55:37 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id iq2-20020a17090afb4200b001d93cf33ae9so9468081pjb.5 for ; Thu, 12 May 2022 18:55:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XLnu5Z1M7spTOfkxmzGNMq9mvJnGiQu2ymVbvg/7Y4o=; b=Gw9bQQPrN9NnofVD2CZg8l8560k0Eu4jmDNZcgA5mtLk3BTLKuqBahKfJOhcT/w+HK OcHyg8B7V8t/tKMDwTCzbyIZqlz41e7HY0vrshiOofh2SCWGRGU6vp7WVjGtfXB902AH CvA/5xrCJeVoELhc/hwxxiuF91TqeRLlf9GEUXrd4NGWXyRx5ENi2UYWvI8LeCTlzGB1 4SPJ3vbr5iDzq93NHAszxeIOOrsK8dPPL+s0r2HpwNazNR713H3ZnADeh33QR+NuNBpt QBO36hJEof9BEbvyFpe58WHDLZKbz1SmRN2r3IA6v8MjIRrqD1A2SHafZvpWEt36WyDL 3BqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XLnu5Z1M7spTOfkxmzGNMq9mvJnGiQu2ymVbvg/7Y4o=; b=P7sXKxC0N0g/2siBqwbt2jctsLB2hnuBE7R3piLGh2lXJYNDbZl0FA8X4HqhyFmhJ6 gF4ANolwyUbIRALleqommlSmVe99JLflXDY4soMwp6Ub6cRaEGjYY3e95C0AbxjJHp8P 3aNjyRh4pRN7pEbrhNPSEDHeu8exiP/CTSke1k65kVrrbL5yTpOn0k6dET393Z9Y8xHT GGMogVoSugHuKjUUfBJTMzrPsslZZHnoM3X9GedNzd3xm6jMStIMCmMbgj3haErNmduz m7yozcdAalXx2h3EO2X6GaoOIYnnKeUOxi0/xjieVWQ2q7BvzKzgo5h0y7ThBq3LsgtP px9Q== X-Gm-Message-State: AOAM5324I2C1lO27tzB3JudGv6qnJQnkbdS/V9Y8eWFYrqvXtqmMRaDS cSCeK0kxR81qQApZ2/q2vVjHX9YOE5A7og== X-Google-Smtp-Source: ABdhPJzO+Hcgg8hisxLU7ADgG8gGPtljLastMpjQQFp1cgf81i34Pr2jRZcEr4RkNp+OCFqqJd9VjA== X-Received: by 2002:a17:902:8504:b0:15d:2c7c:ceac with SMTP id bj4-20020a170902850400b0015d2c7cceacmr2623328plb.130.1652406936838; Thu, 12 May 2022 18:55:36 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id i1-20020a6561a1000000b003c14af5063fsm365883pgv.87.2022.05.12.18.55.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 18:55:36 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Heiko Stuebner , Anup Patel , Atish Patra , Jisheng Zhang , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v2 1/3] RISC-V: Fix counter restart during overflow for RV32 Date: Thu, 12 May 2022 18:55:20 -0700 Message-Id: <20220513015522.910856-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220513015522.910856-1-atishp@rivosinc.com> References: <20220513015522.910856-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Pass the upper half of the initial value of the counter correctly for RV32. Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support") Reviewed-by: Heiko Stuebner Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index a1317a483512..1e6c150c892a 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -525,8 +525,13 @@ static inline void pmu_sbi_start_overflow_mask(struct = riscv_pmu *pmu, hwc =3D &event->hw; max_period =3D riscv_pmu_ctr_get_width_mask(event); init_val =3D local64_read(&hwc->prev_count) & max_period; +#if defined(CONFIG_32BIT) + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, + flag, init_val, init_val >> 32, 0); +#else sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, flag, init_val, 0, 0); +#endif } ctr_ovf_mask =3D ctr_ovf_mask >> 1; idx++; --=20 2.25.1 From nobody Fri May 8 02:20:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8307C433EF for ; Fri, 13 May 2022 01:55:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376434AbiEMBzs (ORCPT ); Thu, 12 May 2022 21:55:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376420AbiEMBzj (ORCPT ); Thu, 12 May 2022 21:55:39 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E932E28F1D6 for ; Thu, 12 May 2022 18:55:38 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id c9so6608170plh.2 for ; Thu, 12 May 2022 18:55:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zwpzunAvrzpyNJwdCWF/epnILRDBBON3y9jarpPPVEU=; b=jn21sS9XmXyewU4HqxnDpg8Clt6oVSJiJy9/dzvwizTppgxJ4ATD5W8DkzU4MK4uGG RXp7gz1Tfo+f+k9qSNtOp4+qIl3++tOFwLmhSiqOr5oBSZ5ivYPXQ8LFk7qXNjDS9vq6 kzydwxWF4Ivso12ENq3uSgByo/9DaPpCDbfCcpgBkqYTU+Su5s4iJwaxddAr86ZK5Wi7 381m+o3ZHxVm8iYaSh/NygFxI9wjCXeGHZ4nin5B6ZlpPelKDPC3jSuu1xBsM1R2mvMa dK3OVNw438WaKzrUjF6y3PK5L2RGN3JP95T8qtHYZ2PqY3CFRYO2CZpo6UXlzOm5O2jT PwSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zwpzunAvrzpyNJwdCWF/epnILRDBBON3y9jarpPPVEU=; b=YhYWmIwspsLjyMKJeTmqstJIXqLmFvq5wZ+D9YD6Ymb5erQkFxm1yTOB4tOLJ5ty3d IBiwAUWjolxxs1jEx6y8r55CkfQIjFpBj5ZZRPoi72v4USwSf3YTmYY1dvuEdbamU3VP qN4Iwl44Pvw7cL3RlPnfZgytugs6Q59VecUP6dt1cPElyYkmE/ZooAnDYZ0tLu7FFHMn sSoV+GwKnXZwwov1Fp71Z/Ycmh1k5OAjvOnJZ+vnc23mNWr8o6xM4dqW7vijLr7avmrP ejkNq3JZB/Sigba7FVRJ0idzx0/RveTSR7hDJyaH7tjF3vrUqfngtaOtarCD8nyue0GQ oKxw== X-Gm-Message-State: AOAM531p6iktj/MEeD0aCiok02D3nRkCoBC5FS13itomyyvYcJ4pik3C NWmlv5tqZJ3w+SCtJhLm5TvPnNE8YcbKDw== X-Google-Smtp-Source: ABdhPJw4gZ6OHEXgL59faCpkeiUSlt9ozUYGPPPvK4t1UxngjnGeG6isTHOmFxPQjvPQmoPyltbyag== X-Received: by 2002:a17:902:d54f:b0:15f:22cd:c6d2 with SMTP id z15-20020a170902d54f00b0015f22cdc6d2mr2572023plf.170.1652406938015; Thu, 12 May 2022 18:55:38 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id i1-20020a6561a1000000b003c14af5063fsm365883pgv.87.2022.05.12.18.55.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 18:55:37 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Anup Patel , Atish Patra , Jisheng Zhang , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v2 2/3] RISC-V: Update user page mapping only once during start Date: Thu, 12 May 2022 18:55:21 -0700 Message-Id: <20220513015522.910856-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220513015522.910856-1-atishp@rivosinc.com> References: <20220513015522.910856-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, riscv_pmu_event_set_period updates the userpage mapping. However, the caller of riscv_pmu_event_set_period should update the userpage mapping because the counter can not be updated/started from set_period function in counter overflow path. Invoke the perf_event_update_userpage at the caller so that it doesn't get invoked twice during counter start path. Fixes: f5bfa23f576f ("RISC-V: Add a perf core library for pmu drivers") Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu.c | 1 - drivers/perf/riscv_pmu_sbi.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c index b2b8d2074ed0..130b9f1a40e0 100644 --- a/drivers/perf/riscv_pmu.c +++ b/drivers/perf/riscv_pmu.c @@ -170,7 +170,6 @@ int riscv_pmu_event_set_period(struct perf_event *event) left =3D (max_period >> 1); =20 local64_set(&hwc->prev_count, (u64)-left); - perf_event_update_userpage(event); =20 return overflow; } diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 1e6c150c892a..7ad92039a718 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -532,6 +532,7 @@ static inline void pmu_sbi_start_overflow_mask(struct r= iscv_pmu *pmu, sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, flag, init_val, 0, 0); #endif + perf_event_update_userpage(event); } ctr_ovf_mask =3D ctr_ovf_mask >> 1; idx++; --=20 2.25.1 From nobody Fri May 8 02:20:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A977C433FE for ; Fri, 13 May 2022 01:55:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376420AbiEMBzx (ORCPT ); Thu, 12 May 2022 21:55:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376421AbiEMBzl (ORCPT ); Thu, 12 May 2022 21:55:41 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 062DAFC0 for ; Thu, 12 May 2022 18:55:39 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id fv2so6782755pjb.4 for ; Thu, 12 May 2022 18:55:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pPoRCiwoBINJx2a5XFW6qeMxXLBrBULI+jQkr1qktFo=; b=yeI2vNN+2d/X/8BAKhk7NJTErNc0t3Ri4UeoW4oeDLfEfpOVAFzJbZEdJd4OL5zlBt 16CUDGhYrbnSYKwz5l4yd+yJBt2LGu1GYKKuQlU0JXxCrFhc0y0nLHz5FdBG0Cs/EC9Q 2PipFMEIgbgErRSSzo9pc90GpReM2RdMLVJ4wjj5s3T1kCqIHw4Gtn8LQHJ6hBclILTU eJ7PTZ7bi5WndFmDlxxf7NSTRrTcclZvJ/IHeF4p/XPtcyM4vfikQtmi6VqmJqgBGTXK Hr0r7MsGu0t773x6K2OfWDTIoChx6ZbNlZ+vb2Xj4VxnpND6eIUNLaTpZDztoDBFnqlZ MrOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pPoRCiwoBINJx2a5XFW6qeMxXLBrBULI+jQkr1qktFo=; b=JUmf6hkJt+/AQGjAGoQwoPGCyamOuYe1bQFC/9tmgAGiZmiPMeTO4Wp7Fmp/VXmnWl CTbZ5JXbaF7jBW7mWPDVS+dzvnHkKzuB5bmGRjomb9Z8e88doQkLn9pXtIt9eHM72/te qhkbp9Qa06zpKgJdKHKT/uWMOtsCsPqZcJFYkFy5rIyq28TmxWDYjdI2MpDLzAqzpuxs 8FWegqe5Zs+O+cRqA5JwgCwMsMNusiIRz9E6MCDW5Y4ORntxT7BAtrQBC56vt/yBmXlo Al7sNeal8Y+zpkt9zj+UXxSsnWjkwYsWeedGTZJptfU7z6wTUYnR4JzsQacTe/jc2VOJ oghQ== X-Gm-Message-State: AOAM530zr175REF31Clpbw4q9F77KAPLLakvrIo869nduIiwxL/fq5DU oLHpLg2RezTGxWpzZGZm0nFjJJqEKlZ+BA== X-Google-Smtp-Source: ABdhPJwufGXGbLuIccz3+zyq2wHIQcgZXVxMmyj1l/g/wWcffrG37DEvEdIXB93ZMBkLn+2Hl79Afw== X-Received: by 2002:a17:902:850b:b0:15f:2a59:1c02 with SMTP id bj11-20020a170902850b00b0015f2a591c02mr2595813plb.27.1652406939289; Thu, 12 May 2022 18:55:39 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id i1-20020a6561a1000000b003c14af5063fsm365883pgv.87.2022.05.12.18.55.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 18:55:38 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Jisheng Zhang , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v2 3/3] RISC-V: Fix SBI PMU calls for RV32 Date: Thu, 12 May 2022 18:55:22 -0700 Message-Id: <20220513015522.910856-4-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220513015522.910856-1-atishp@rivosinc.com> References: <20220513015522.910856-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some of the SBI PMU calls does not pass 64bit arguments correctly and not under RV32 compile time flags. Currently, this doesn't create any incorrect results as RV64 ignores any value in the additional register and qemu doesn't support raw events. Fix those SBI calls in order to set correct values for RV32. Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU ext= ension") Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- drivers/perf/riscv_pmu_sbi.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 7ad92039a718..fab0dd497393 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -274,8 +274,13 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *even= t) cflags |=3D SBI_PMU_CFG_FLAG_SET_UINH; =20 /* retrieve the available counter index */ +#if defined(CONFIG_32BIT) + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmas= k, + cflags, hwc->event_base, hwc->config, hwc->config >> 32); +#else ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmas= k, cflags, hwc->event_base, hwc->config, 0); +#endif if (ret.error) { pr_debug("Not able to find a counter for event %lx config %llx\n", hwc->event_base, hwc->config); @@ -417,8 +422,13 @@ static void pmu_sbi_ctr_start(struct perf_event *event= , u64 ival) struct hw_perf_event *hwc =3D &event->hw; unsigned long flag =3D SBI_PMU_START_FLAG_SET_INIT_VALUE; =20 +#if defined(CONFIG_32BIT) ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx, 1, flag, ival, ival >> 32, 0); +#else + ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx, + 1, flag, ival, 0, 0); +#endif if (ret.error && (ret.error !=3D SBI_ERR_ALREADY_STARTED)) pr_err("Starting counter idx %d failed with error %d\n", hwc->idx, sbi_err_map_linux_errno(ret.error)); --=20 2.25.1