From nobody Fri May 8 03:10:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51F2FC433F5 for ; Thu, 12 May 2022 11:01:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352909AbiELLBu (ORCPT ); Thu, 12 May 2022 07:01:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238426AbiELLBr (ORCPT ); Thu, 12 May 2022 07:01:47 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7761C2E697; Thu, 12 May 2022 04:01:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652353306; x=1683889306; h=from:to:cc:subject:date:message-id; bh=XswWfruTz3bYVjoW5r66/vCbMkAhLTZ/FrO1QjUGPC8=; b=F+6wJSaom6qbokT0FRZ5HLwepMcm/5WWQBt9gJ+AWMpQK4i0Sotkrwa9 SgFFsiQ/WWaraolV2tgCy3KNVGowz2hNeIAuDlwJexmY2uVwO5gj0j+aU TF9E/+YtX7BX4ejicdv73EB43J5ReL1NKX3pnDwpws12olleCwKlhErxu I=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 12 May 2022 04:01:46 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 12 May 2022 04:01:44 -0700 X-QCInternal: smtphost Received: from blr-ubuntu-435.qualcomm.com ([10.79.42.176]) by ironmsg01-blr.qualcomm.com with ESMTP; 12 May 2022 16:31:42 +0530 Received: by blr-ubuntu-435.qualcomm.com (Postfix, from userid 2327845) id 98C169008B1; Thu, 12 May 2022 16:31:41 +0530 (IST) From: Shreyas K K To: Will Deacon , Catalin Marinas , Marc Zyngier , Suzuki K Poulose , Mark Rutland Cc: Andre Przywara , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Jeffrey Hugo , Shreyas K K , Sai Prakash Ranjan , Rajendra Nayak , Prasanna Kumar Subject: [PATCH V3] arm64: Enable repeat tlbi workaround on KRYO4XX gold CPUs Date: Thu, 12 May 2022 16:31:34 +0530 Message-Id: <20220512110134.12179-1-quic_shrekk@quicinc.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add KRYO4XX gold/big cores to the list of CPUs that need the repeat TLBI workaround. Apply this to the affected KRYO4XX cores (rcpe to rfpe). The variant and revision bits are implementation defined and are different from the their Cortex CPU counterparts on which they are based on, i.e., (r0p0 to r3p0) is equivalent to (rcpe to rfpe). Signed-off-by: Shreyas K K Reviewed-by: Sai Prakash Ranjan --- Changes in v2: * r2p0 and r3p0 are also affected by this erratum. * Add the corresponding cores (repe and rfpe) making the range rcpe to rfp= e. Changes in v3: * Fix the CPU model macro. Documentation/arm64/silicon-errata.rst | 3 +++ arch/arm64/kernel/cpu_errata.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/s= ilicon-errata.rst index 466cb9e89047..d27db84d585e 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -189,6 +189,9 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_10247= 18 | +----------------+-----------------+-----------------+--------------------= ---------+ +| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_12868= 07 | ++----------------+-----------------+-----------------+--------------------= ---------+ + +----------------+-----------------+-----------------+--------------------= ---------+ | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010= 001 | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 4c9b5b4b7a0b..a0f3d0aaa3c5 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -208,6 +208,8 @@ static const struct arm64_cpu_capabilities arm64_repeat= _tlbi_list[] =3D { #ifdef CONFIG_ARM64_ERRATUM_1286807 { ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), + /* Kryo4xx Gold (rcpe to rfpe) =3D> (r0p0 to r3p0) */ + ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe), }, #endif {}, --=20 2.17.1