From nobody Sun Sep 22 03:37:51 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67C42C433EF for ; Wed, 11 May 2022 04:28:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234996AbiEKE23 (ORCPT ); Wed, 11 May 2022 00:28:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233135AbiEKE2N (ORCPT ); Wed, 11 May 2022 00:28:13 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33FD2506E5 for ; Tue, 10 May 2022 21:28:07 -0700 (PDT) X-UUID: d4394107dc414c67baeebb97395fb0b2-20220511 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:b02845c7-f103-4172-8a93-45928bf73e5a,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:75 X-CID-INFO: VERSION:1.1.4,REQID:b02845c7-f103-4172-8a93-45928bf73e5a,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:75 X-CID-META: VersionHash:faefae9,CLOUDID:93600ae6-38f2-431d-8de7-bf8fac490b0a,C OID:2eeeae7f4fda,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: d4394107dc414c67baeebb97395fb0b2-20220511 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 495322957; Wed, 11 May 2022 12:28:03 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Wed, 11 May 2022 12:28:02 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 11 May 2022 12:28:02 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 11 May 2022 12:28:02 +0800 From: Tinghan Shen To: Matthias Brugger , Pierre-Louis Bossart , Liam Girdwood , Ranjani Sridharan , Kai Vehmanen , Daniel Baluta , "Mark Brown" , Jaroslav Kysela , Takashi Iwai , Javier Martinez Canillas , "Thomas Zimmermann" , Daniel Vetter , Bjorn Andersson , Sudeep Holla , Michal Suchanek , Shuai Xue , Simon Trimmer , Cristian Marussi , TingHan Shen , Arnd Bergmann , Borislav Petkov , Greg Kroah-Hartman , John Stultz , Curtis Malainey , AngeloGioacchino Del Regno , Allen-KH Cheng , YC Hung , Tzung-Bi Shih , Yang Yingliang , Geert Uytterhoeven , =?UTF-8?q?P=C3=A9ter=20Ujfalusi?= CC: , , , , , , Allen-KH Cheng Subject: [PATCH v8 3/3] ASoC: SOF: mediatek: Add mt8186 ipc support Date: Wed, 11 May 2022 12:27:18 +0800 Message-ID: <20220511042718.4305-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220511042718.4305-1-tinghan.shen@mediatek.com> References: <20220511042718.4305-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" mt8186 DSP uses two hardware mailbox IP to communicate with AP. One mailbox is used for requests coming from AP, and the other one is for requests from DSP. Signed-off-by: Allen-KH Cheng Signed-off-by: Tinghan Shen --- sound/soc/sof/mediatek/mt8186/mt8186-loader.c | 5 + sound/soc/sof/mediatek/mt8186/mt8186.c | 141 ++++++++++++++++++ 2 files changed, 146 insertions(+) diff --git a/sound/soc/sof/mediatek/mt8186/mt8186-loader.c b/sound/soc/sof/= mediatek/mt8186/mt8186-loader.c index 548b12c33d8a..946e6c43204f 100644 --- a/sound/soc/sof/mediatek/mt8186/mt8186-loader.c +++ b/sound/soc/sof/mediatek/mt8186/mt8186-loader.c @@ -17,6 +17,11 @@ void mt8186_sof_hifixdsp_boot_sequence(struct snd_sof_de= v *sdev, u32 boot_addr) snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG, RUNSTALL, RUNSTALL); =20 + /* enable mbox 0 & 1 IRQ */ + snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_MBOX_IRQ_EN, + DSP_MBOX0_IRQ_EN | DSP_MBOX1_IRQ_EN, + DSP_MBOX0_IRQ_EN | DSP_MBOX1_IRQ_EN); + /* set core boot address */ snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVEC_C0, boot_addr); snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVECSEL, ADSP_ALTVECSEL_C0= ); diff --git a/sound/soc/sof/mediatek/mt8186/mt8186.c b/sound/soc/sof/mediate= k/mt8186/mt8186.c index 6d574fd4492e..3333a0634e29 100644 --- a/sound/soc/sof/mediatek/mt8186/mt8186.c +++ b/sound/soc/sof/mediatek/mt8186/mt8186.c @@ -27,6 +27,99 @@ #include "mt8186.h" #include "mt8186-clk.h" =20 +static int mt8186_get_mailbox_offset(struct snd_sof_dev *sdev) +{ + return MBOX_OFFSET; +} + +static int mt8186_get_window_offset(struct snd_sof_dev *sdev, u32 id) +{ + return MBOX_OFFSET; +} + +static int mt8186_send_msg(struct snd_sof_dev *sdev, + struct snd_sof_ipc_msg *msg) +{ + struct adsp_priv *priv =3D sdev->pdata->hw_pdata; + + sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, + msg->msg_size); + + return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP= _REQ); +} + +static void mt8186_get_reply(struct snd_sof_dev *sdev) +{ + struct snd_sof_ipc_msg *msg =3D sdev->msg; + struct sof_ipc_reply reply; + int ret =3D 0; + + if (!msg) { + dev_warn(sdev->dev, "unexpected ipc interrupt\n"); + return; + } + + /* get reply */ + sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply)); + if (reply.error < 0) { + memcpy(msg->reply_data, &reply, sizeof(reply)); + ret =3D reply.error; + } else { + /* reply has correct size? */ + if (reply.hdr.size !=3D msg->reply_size) { + dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n", + msg->reply_size, reply.hdr.size); + ret =3D -EINVAL; + } + + /* read the message */ + if (msg->reply_size > 0) + sof_mailbox_read(sdev, sdev->host_box.offset, + msg->reply_data, msg->reply_size); + } + + msg->reply_error =3D ret; +} + +static void mt8186_dsp_handle_reply(struct mtk_adsp_ipc *ipc) +{ + struct adsp_priv *priv =3D mtk_adsp_ipc_get_data(ipc); + unsigned long flags; + + spin_lock_irqsave(&priv->sdev->ipc_lock, flags); + mt8186_get_reply(priv->sdev); + snd_sof_ipc_reply(priv->sdev, 0); + spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags); +} + +static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc) +{ + struct adsp_priv *priv =3D mtk_adsp_ipc_get_data(ipc); + u32 p; /* panic code */ + int ret; + + /* Read the message from the debug box. */ + sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4, + &p, sizeof(p)); + + /* Check to see if the message is a panic code 0x0dead*** */ + if ((p & SOF_IPC_PANIC_MAGIC_MASK) =3D=3D SOF_IPC_PANIC_MAGIC) { + snd_sof_dsp_panic(priv->sdev, p, true); + } else { + snd_sof_ipc_msgs_rx(priv->sdev); + + /* tell DSP cmd is done */ + ret =3D mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_= OP_RSP); + if (ret) + dev_err(priv->dev, "request send ipc failed"); + } +} + +static struct mtk_adsp_ipc_ops dsp_ops =3D { + .handle_reply =3D mt8186_dsp_handle_reply, + .handle_request =3D mt8186_dsp_handle_request, +}; + static int platform_parse_resource(struct platform_device *pdev, void *dat= a) { struct resource *mmio; @@ -271,6 +364,9 @@ static int mt8186_dsp_probe(struct snd_sof_dev *sdev) sdev->mmio_bar =3D SOF_FW_BLK_TYPE_SRAM; sdev->mailbox_bar =3D SOF_FW_BLK_TYPE_SRAM; =20 + /* set default mailbox offset for FW ready message */ + sdev->dsp_box.offset =3D mt8186_get_mailbox_offset(sdev); + ret =3D adsp_memory_remap_init(sdev, priv->adsp); if (ret) { dev_err(sdev->dev, "adsp_memory_remap_init fail!\n"); @@ -292,11 +388,41 @@ static int mt8186_dsp_probe(struct snd_sof_dev *sdev) =20 adsp_sram_power_on(sdev); =20 + priv->ipc_dev =3D platform_device_register_data(&pdev->dev, "mtk-adsp-ipc= ", + PLATFORM_DEVID_NONE, + pdev, sizeof(*pdev)); + if (IS_ERR(priv->ipc_dev)) { + ret =3D IS_ERR(priv->ipc_dev); + dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n"); + goto err_adsp_off; + } + + priv->dsp_ipc =3D dev_get_drvdata(&priv->ipc_dev->dev); + if (!priv->dsp_ipc) { + ret =3D -EPROBE_DEFER; + dev_err(sdev->dev, "failed to get drvdata\n"); + goto exit_pdev_unregister; + } + + mtk_adsp_ipc_set_data(priv->dsp_ipc, priv); + priv->dsp_ipc->ops =3D &dsp_ops; + return 0; + +exit_pdev_unregister: + platform_device_unregister(priv->ipc_dev); +err_adsp_off: + adsp_sram_power_off(sdev); + mt8186_adsp_clock_off(sdev); + + return ret; } =20 static int mt8186_dsp_remove(struct snd_sof_dev *sdev) { + struct adsp_priv *priv =3D sdev->pdata->hw_pdata; + + platform_device_unregister(priv->ipc_dev); mt8186_sof_hifixdsp_shutdown(sdev); adsp_sram_power_off(sdev); mt8186_adsp_clock_off(sdev); @@ -334,6 +460,14 @@ static int mt8186_get_bar_index(struct snd_sof_dev *sd= ev, u32 type) return type; } =20 +static int mt8186_ipc_msg_data(struct snd_sof_dev *sdev, + struct snd_pcm_substream *substream, + void *p, size_t sz) +{ + sof_mailbox_read(sdev, sdev->dsp_box.offset, p, sz); + return 0; +} + /* mt8186 ops */ static struct snd_sof_dsp_ops sof_mt8186_ops =3D { /* probe and remove */ @@ -353,6 +487,13 @@ static struct snd_sof_dsp_ops sof_mt8186_ops =3D { .write64 =3D sof_io_write64, .read64 =3D sof_io_read64, =20 + /* ipc */ + .send_msg =3D mt8186_send_msg, + .get_mailbox_offset =3D mt8186_get_mailbox_offset, + .get_window_offset =3D mt8186_get_window_offset, + .ipc_msg_data =3D mt8186_ipc_msg_data, + .set_stream_data_offset =3D sof_set_stream_data_offset, + /* misc */ .get_bar_index =3D mt8186_get_bar_index, =20 --=20 2.18.0