From nobody Sun May 10 09:55:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C35CC433F5 for ; Tue, 10 May 2022 23:10:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235270AbiEJXKc (ORCPT ); Tue, 10 May 2022 19:10:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232405AbiEJXKR (ORCPT ); Tue, 10 May 2022 19:10:17 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 923B9293B7C for ; Tue, 10 May 2022 16:10:13 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 281542C02DE; Tue, 10 May 2022 23:10:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1652224210; bh=M/qdruHJlEw4eVXCC1MdUNQ3IqTaibvAe3rgnPTiJHE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=2+lNn1byUYE1CpiHaR0kf+hkDekvwINV3yp5b3uL+mxdpB0GOAUBTyd0m5WoR1H05 KMhVQ5q4aWkH6flinE73bsxdLaeUBBQzH9l/5GQdvk35VzRwq1ZE1z4g1WfLbccIFt GYwbk5InSf79jaC1jEfHNA8z5Cm3ylkuFLhpAjOEGWdyyjHCPTC0Lj++QCrYmGuXZX 3MHBdIXv6UL/ALF9M7rw76qN5QlWZcCDr8QOF3oMlB9TllqY6kb0Jf0IEV+6aJC4mH JGKca2uWoUY2pxDhsOIVx8m7kwyeEOnUWW37LB2HzS24MKKPifOP1rZqsYtBtC6b6X UeoCpbN5/s7Sw== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Wed, 11 May 2022 11:10:09 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id C811313EE56; Wed, 11 May 2022 11:10:09 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id C37C12A00A0; Wed, 11 May 2022 11:10:09 +1200 (NZST) From: Chris Packham To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, kostap@marvell.com, robert.marko@sartura.hr Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles Date: Wed, 11 May 2022 11:10:00 +1200 Message-Id: <20220510231002.1160798-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220510231002.1160798-1-chris.packham@alliedtelesis.co.nz> References: <20220510231002.1160798-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SEG-SpamProfiler-Analysis: v=2.3 cv=C7GXNjH+ c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=oZkIemNP1mAA:10 a=gEfo2CItAAAA:8 a=SCFnzoBICK1g0U61-m0A:9 a=sptkURWiP4Gy88Gu7hUp:22 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Describe the compatible properties for the Marvell Alleycat5/5X switches with integrated CPUs. Alleycat5: * 98DX2538: 24x1G + 2x10G + 2x10G Stack * 98DX2535: 24x1G + 4x1G Stack * 98DX2532: 8x1G + 2x10G + 2x1G Stack * 98DX2531: 8x1G + 4x1G Stack * 98DX2528: 24x1G + 2x10G + 2x10G Stack * 98DX2525: 24x1G + 4x1G Stack * 98DX2522: 8x1G + 2x10G + 2x1G Stack * 98DX2521: 8x1G + 4x1G Stack * 98DX2518: 24x1G + 2x10G + 2x10G Stack * 98DX2515: 24x1G + 4x1G Stack * 98DX2512: 8x1G + 2x10G + 2x1G Stack * 98DX2511: 8x1G + 4x1G Stack Alleycat5X: * 98DX3500: 24x1G + 6x25G * 98DX3501: 16x1G + 6x10G * 98DX3510: 48x1G + 6x25G * 98DX3520: 24x2.5G + 6x25G * 98DX3530: 48x2.5G + 6x25G * 98DX3540: 12x5G/6x10G + 6x25G * 98DX3550: 24x5G/12x10G + 6x25G Signed-off-by: Chris Packham --- Notes: Changes in v6: - New .../bindings/arm/marvell/armada-98dx2530.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-98= dx2530.yaml diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-98dx2530.= yaml b/Documentation/devicetree/bindings/arm/marvell/armada-98dx2530.yaml new file mode 100644 index 000000000000..6d9185baf0c5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/armada-98dx2530.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/armada-98dx2530.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Alleycat5/5X Platforms + +maintainers: + - Chris Packham + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: Alleycat5 (98DX25xx) + items: + - const: marvell,ac5 + + - description: Alleycat5X (98DX35xx) + items: + - const: marvell,ac5x + - const: marvell,ac5 + +additionalProperties: true --=20 2.36.0 From nobody Sun May 10 09:55:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3F84C433F5 for ; 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d=alliedtelesis.co.nz; s=mail181024; t=1652224210; bh=a6oaYzZEzedcBkB9KIscmhFUhvzTQyTjKfpFG10vpfs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f2NmmfQ2W3ojFQDTLbie72xwx8MmLTEeRtkb3zJcsK38BZg2HdAVF1U/OP+4txwpo SuPcqN7qaC4wrRwTIsXJvwYqnl69jThEo3HTHuUszhJflS89560H7OUdmOAge6PRWf AUxgr5c7XY1//xyXrLO1kFeHfGK2V2lGoleJk3K1pOW77Zy+EeZx04SUtvsdotG/aY p1DYnwmJ9qL6p8FFn9erCrJiFCFs0bCsUIcoi8PWUFuCmnhT1gT1INvAZdBMPjygDG pHZcPohD4e6DOJ+DMw7PmiN04T8IgAavNp9enikOMCn7ZtrZj710Y2+W3i3O4hsohF GRQA++PZJA3Gw== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Wed, 11 May 2022 11:10:09 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by pat.atlnz.lc (Postfix) with ESMTP id CACF913EE85; Wed, 11 May 2022 11:10:09 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id C7B6B2A040A; Wed, 11 May 2022 11:10:09 +1200 (NZST) From: Chris Packham To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, catalin.marinas@arm.com, will@kernel.org, andrew@lunn.ch, gregory.clement@bootlin.com, sebastian.hesselbarth@gmail.com, kostap@marvell.com, robert.marko@sartura.hr Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Chris Packham Subject: [PATCH v6 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Date: Wed, 11 May 2022 11:10:01 +1200 Message-Id: <20220510231002.1160798-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220510231002.1160798-1-chris.packham@alliedtelesis.co.nz> References: <20220510231002.1160798-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SEG-SpamProfiler-Analysis: v=2.3 cv=C7GXNjH+ c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=oZkIemNP1mAA:10 a=sHAJOpqgVnCWuCwbjzwA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The 98DX2530 SoC is the Control and Management CPU integrated into the Marvell 98DX25xx and 98DX35xx series of switch chip (internally referred to as AlleyCat5 and AlleyCat5X). These files have been taken from the Marvell SDK and lightly cleaned up with the License and copyright retained. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn --- Notes: The Marvell SDK has a number of new compatible strings. I've brought through some of the drivers or where possible used an in-tree alternative (e.g. there is SDK code for a ac5-gpio but two instances of the existing marvell,orion-gpio seems to cover what is needed if you use an appropriate binding). I expect that there will a new series of patches when I get some different hardware (or additions to this series depending on if/when it lands). =20 Changes in v6: - Move CPU nodes above the SoC (Krzysztof) - Minor formatting clean ups (Krzysztof) - Run through `make dtbs_check` - Move gic nodes inside SoC - Group clocks under a clock node Changes in v5: - add #{address,size}-cells property to i2c nodes - make i2c nodes disabled in the SoC and enable them in the board - add interrupt controller attributes to gpio nodes - Move fixed-clock nodes up a level and remove unnecessary @0 Changes in v4: - use 'phy-handle' instead of 'phy' - move status=3D"okay" on usb nodes to board dts - Add review from Andrew Changes in v3: - Move memory node to board - Use single digit reg value for phy address - Remove MMC node (driver needs work) - Remove syscon & simple-mfd for pinctrl Changes in v2: - Make pinctrl a child node of a syscon node - Use marvell,armada-8k-gpio instead of orion-gpio - Remove nand peripheral. The Marvell SDK does have some changes for the ac5-nand-controller but I currently lack hardware with NAND fitted so I can't test it right now. I've therefore chosen to omit the node and not attempted to bring in the driver or binding. - Remove pcie peripheral. Again there are changes in the SDK and I have no way of testing them. - Remove prestera node. - Remove "marvell,ac5-ehci" compatible from USB node as "marvell,orion-ehci" is sufficient - Remove watchdog node. There is a buggy driver for the ac5 watchdog in the SDK but it needs some work so I've dropped the node for now. arch/arm64/boot/dts/marvell/Makefile | 1 + .../boot/dts/marvell/armada-98dx2530.dtsi | 313 ++++++++++++++++++ arch/arm64/boot/dts/marvell/rd-ac5x.dts | 90 +++++ 3 files changed, 404 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx2530.dtsi create mode 100644 arch/arm64/boot/dts/marvell/rd-ac5x.dts diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/mar= vell/Makefile index 1c794cdcb8e6..3905dee558b4 100644 --- a/arch/arm64/boot/dts/marvell/Makefile +++ b/arch/arm64/boot/dts/marvell/Makefile @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9132-db.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9132-db-B.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) +=3D cn9130-crb-B.dtb +dtb-$(CONFIG_ARCH_MVEBU) +=3D rd-ac5x.dtb diff --git a/arch/arm64/boot/dts/marvell/armada-98dx2530.dtsi b/arch/arm64/= boot/dts/marvell/armada-98dx2530.dtsi new file mode 100644 index 000000000000..724e722b4265 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-98dx2530.dtsi @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5. + * + * Copyright (C) 2021 Marvell + * + */ + +/dts-v1/; + +#include +#include + +/ { + model =3D "Marvell AC5 SoC"; + compatible =3D "marvell,ac5"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + aliases { + serial0 =3D &uart0; + spiflash0 =3D &spiflash0; + gpio0 =3D &gpio0; + gpio1 =3D &gpio1; + ethernet0 =3D ð0; + ethernet1 =3D ð1; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,armv8"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,armv8"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l2>; + }; + + l2: l2-cache { + compatible =3D "cache"; + }; + }; + + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + clock-frequency =3D <25000000>; + }; + + pmu { + compatible =3D "arm,armv8-pmuv3"; + interrupts =3D ; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + dma-ranges; + + internal-regs@7f000000 { + #address-cells =3D <1>; + #size-cells =3D <1>; + compatible =3D "simple-bus"; + /* 16M internal register @ 0x7f00_0000 */ + ranges =3D <0x0 0x0 0x7f000000 0x1000000>; + dma-coherent; + + uart0: serial@12000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x12000 0x100>; + reg-shift =3D <2>; + interrupts =3D ; + reg-io-width =3D <1>; + clock-frequency =3D <328000000>; + status =3D "okay"; + }; + + mdio: mdio@22004 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,orion-mdio"; + reg =3D <0x22004 0x4>; + clocks =3D <&core_clock>; + }; + + i2c0: i2c@11000{ + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x11000 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + clocks =3D <&core_clock>; + clock-names =3D "core"; + interrupts =3D ; + clock-frequency=3D<100000>; + + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&i2c0_pins>; + pinctrl-1 =3D <&i2c0_gpio>; + scl_gpio =3D <&gpio0 26 GPIO_ACTIVE_HIGH>; + sda_gpio =3D <&gpio0 27 GPIO_ACTIVE_HIGH>; + status =3D "disabled"; + }; + + i2c1: i2c@11100{ + compatible =3D "marvell,mv78230-i2c"; + reg =3D <0x11100 0x20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + clocks =3D <&core_clock>; + clock-names =3D "core"; + interrupts =3D ; + clock-frequency=3D<100000>; + + pinctrl-names =3D "default", "gpio"; + pinctrl-0 =3D <&i2c1_pins>; + pinctrl-1 =3D <&i2c1_gpio>; + scl_gpio =3D <&gpio0 20 GPIO_ACTIVE_HIGH>; + sda_gpio =3D <&gpio0 21 GPIO_ACTIVE_HIGH>; + status =3D "disabled"; + }; + + gpio0: gpio@18100 { + compatible =3D "marvell,orion-gpio"; + reg =3D <0x18100 0x40>; + ngpios =3D <32>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl0 0 0 32>; + marvell,pwm-offset =3D <0x1f0>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpio1: gpio@18140 { + reg =3D <0x18140 0x40>; + compatible =3D "marvell,orion-gpio"; + ngpios =3D <14>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl0 0 32 14>; + marvell,pwm-offset =3D <0x1f0>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + /* + * Dedicated section for devices behind 32bit controllers so we + * can configure specific DMA mapping for them + */ + behind-32bit-controller@7f000000 { + compatible =3D "simple-bus"; + #address-cells =3D <0x2>; + #size-cells =3D <0x2>; + ranges =3D <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>; + /* Host phy ram starts at 0x200M */ + dma-ranges =3D <0x0 0x0 0x2 0x0 0x1 0x0>; + dma-coherent; + + eth0: ethernet@20000 { + compatible =3D "marvell,armada-ac5-neta"; + reg =3D <0x0 0x20000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&core_clock>; + phy-mode =3D "sgmii"; + status =3D "disabled"; + }; + + eth1: ethernet@24000 { + compatible =3D "marvell,armada-ac5-neta"; + reg =3D <0x0 0x24000 0x0 0x4000>; + interrupts =3D ; + clocks =3D <&core_clock>; + phy-mode =3D "sgmii"; + status =3D "disabled"; + }; + + /* A dummy entry used for chipidea phy init */ + usb1phy: usb-phy { + compatible =3D "usb-nop-xceiv"; + #phy-cells =3D <0>; + }; + + /* USB0 is a host USB */ + usb0: usb@80000 { + compatible =3D "marvell,orion-ehci"; + reg =3D <0x0 0x80000 0x0 0x500>; + interrupts =3D ; + status =3D "disabled"; + }; + + /* USB1 is a peripheral USB */ + usb1: usb@a0000 { + reg =3D <0x0 0xa0000 0x0 0x500>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + + pinctrl0: pinctrl@80020100 { + compatible =3D "marvell,ac5-pinctrl"; + reg =3D <0 0x80020100 0 0x20>; + + i2c0_pins: i2c0-pins { + marvell,pins =3D "mpp26", "mpp27"; + marvell,function =3D "i2c0"; + }; + + i2c0_gpio: i2c0-gpio-pins { + marvell,pins =3D "mpp26", "mpp27"; + marvell,function =3D "gpio"; + }; + + i2c1_pins: i2c1-pins { + marvell,pins =3D "mpp20", "mpp21"; + marvell,function =3D "i2c1"; + }; + + i2c1_gpio: i2c1-gpio-pins { + marvell,pins =3D "mpp20", "mpp21"; + marvell,function =3D "i2c1"; + }; + }; + + spi0: spi@805a0000 { + compatible =3D "marvell,armada-3700-spi"; + reg =3D <0x0 0x805a0000 0x0 0x50>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + clocks =3D <&spi_clock>; + interrupts =3D ; + num-cs =3D <1>; + status =3D "disabled"; + }; + + spi1: spi@805a8000 { + compatible =3D "marvell,armada-3700-spi"; + reg =3D <0x0 0x805a8000 0x0 0x50>; + #address-cells =3D <0x1>; + #size-cells =3D <0x0>; + clocks =3D <&spi_clock>; + interrupts =3D ; + num-cs =3D <1>; + status =3D "disabled"; + }; + + gic: interrupt-controller@80600000 { + compatible =3D "arm,gic-v3"; + #interrupt-cells =3D <3>; + interrupt-controller; + /*#redistributor-regions =3D <1>;*/ + redistributor-stride =3D <0x0 0x20000>; // 128kB stride + reg =3D <0x0 0x80600000 0x0 0x10000>, /* GICD */ + <0x0 0x80660000 0x0 0x40000>; /* GICR */ + interrupts =3D ; + }; + }; + + clocks { + core_clock: core-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <400000000>; + }; + + axi_clock: axi-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <325000000>; + }; + + spi_clock: spi-clock { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/rd-ac5x.dts b/arch/arm64/boot/dts/= marvell/rd-ac5x.dts new file mode 100644 index 000000000000..7ac87413e023 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/rd-ac5x.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For AC5X. + * + * Copyright (C) 2021 Marvell + * + */ +/* + * Device Tree file for Marvell Alleycat 5X development board + * This board file supports the B configuration of the board + */ + +/dts-v1/; + +#include "armada-98dx2530.dtsi" + +/ { + model =3D "Marvell RD-AC5X Board"; + compatible =3D "marvell,ac5x", "marvell,ac5"; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x2 0x00000000 0x0 0x40000000>; + }; +}; + +&mdio { + phy0: ethernet-phy@0 { + reg =3D <0>; + }; +}; + +&i2c0 { + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; +}; + +ð0 { + status =3D "okay"; + phy-handle =3D <&phy0>; +}; + +&usb0 { + status =3D "okay"; +}; + +&usb1 { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; + + spiflash0: flash@0 { + compatible =3D "jedec,spi-nor"; + spi-max-frequency =3D <50000000>; + spi-tx-bus-width =3D <1>; /* 1-single, 2-dual, 4-quad */ + spi-rx-bus-width =3D <1>; /* 1-single, 2-dual, 4-quad */ + reg =3D <0>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + label =3D "spi_flash_part0"; + reg =3D <0x0 0x800000>; + }; + + parition@1 { + label =3D "spi_flash_part1"; + reg =3D <0x800000 0x700000>; + }; + + parition@2 { + label =3D "spi_flash_part2"; + reg =3D <0xF00000 0x100000>; + }; + }; +}; + +&usb1 { + compatible =3D "chipidea,usb2"; + phys =3D <&usb1phy>; + phy-names =3D "usb-phy"; + dr_mode =3D "peripheral"; +}; + --=20 2.36.0 From nobody Sun May 10 09:55:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2114C433EF for ; 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charset="utf-8" This commit makes sure the drivers for the 98DX2530 pin controller is enabled. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn --- Notes: Changes in v6: - New Changes in v5: - None Changes in v4: - None Changes in v3: - Add review from Andrew Changes in v2: - None arch/arm64/Kconfig.platforms | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 30b123cde02c..229571d57496 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -183,11 +183,13 @@ config ARCH_MVEBU select PINCTRL_ARMADA_37XX select PINCTRL_ARMADA_AP806 select PINCTRL_ARMADA_CP110 + select PINCTRL_AC5 help This enables support for Marvell EBU familly, including: - Armada 3700 SoC Family - Armada 7K SoC Family - Armada 8K SoC Family + - 98DX2530 SoC Family =20 config ARCH_MXC bool "ARMv8 based NXP i.MX SoC family" --=20 2.36.0