From nobody Sun May 10 09:54:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6947EC433EF for ; Tue, 10 May 2022 18:30:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348928AbiEJSas (ORCPT ); Tue, 10 May 2022 14:30:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348875AbiEJSap (ORCPT ); Tue, 10 May 2022 14:30:45 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22F5E2DDC; Tue, 10 May 2022 11:30:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652207444; x=1683743444; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SByInZuezabV9ptXq3P9/wReRUwF7TvR/B7eWfqBJNI=; b=FFcHRannz73f2PGL9On+udmF4wU0dphoajICexSFzbCmWgV9ML9iOeUE nJJjgKjaorygBAkuJgFzEm729ua+YZnEgCpIoPrMxj9Fd939pCcQ5BaXJ xRY448uA2LnfEOVvpW6l4/ChezAswO2dE9zg1fvOSZHkSHjU+RRjc0KHk pwPli+WNLP+hBb4/AEUtIwzD6qgzt0TWO6W84QXmbb/KP2iSOPZrzvx/E +YDRteHoSqVCY5kfeTHJLEXpotqUf7UYPYR2Dj7LC5AiTdzHWiVsj89dB SNswjlBVrc64GHiJomJNPcghiV5K982S7FUOvhJCpXplzntLtm9AyFPNc A==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="249998288" X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="249998288" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:30:43 -0700 X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="738839902" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:30:42 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach , Krzysztof Kozlowski Subject: [PATCH v5 1/3] dt-bindings: soc: add bindings for Intel HPS Copy Engine Date: Tue, 10 May 2022 11:30:39 -0700 Message-Id: <20220510183041.876583-2-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220510183041.876583-1-matthew.gerlach@linux.intel.com> References: <20220510183041.876583-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matthew Gerlach Add device tree bindings documentation for the Intel Hard Processor System (HPS) Copy Engine. Signed-off-by: Matthew Gerlach Reviewed-by: Krzysztof Kozlowski --- v5: - add Reviewed-by: Krzysztof Kozlowski v4: - move from soc to soc/intel/ v3: - remove unused label - move from misc to soc - remove 0x from #address-cells/#size-cells values - change hps_cp_eng@0 to dma-controller@0 - remote inaccurate 'items:' tag --- .../soc/intel/intel,hps-copy-engine.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-c= opy-engine.yaml diff --git a/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-eng= ine.yaml b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engin= e.yaml new file mode 100644 index 000000000000..8634865015cd --- /dev/null +++ b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2022, Intel Corporation +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel HPS Copy Engine + +maintainers: + - Matthew Gerlach + +description: | + The Intel Hard Processor System (HPS) Copy Engine is an IP block used to= copy + a bootable image from host memory to HPS DDR. Additionally, there is a + register the HPS can use to indicate the state of booting the copied ima= ge as + well as a keep-a-live indication to the host. + +properties: + compatible: + const: intel,hps-copy-engine + + '#dma-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + bus@80000000 { + compatible =3D "simple-bus"; + reg =3D <0x80000000 0x60000000>, + <0xf9000000 0x00100000>; + reg-names =3D "axi_h2f", "axi_h2f_lw"; + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges =3D <0x00000000 0x00000000 0xf9000000 0x00001000>; + + dma-controller@0 { + compatible =3D "intel,hps-copy-engine"; + reg =3D <0x00000000 0x00000000 0x00001000>; + #dma-cells =3D <1>; + }; + }; --=20 2.25.1 From nobody Sun May 10 09:54:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2679DC433F5 for ; Tue, 10 May 2022 18:30:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348944AbiEJSaw (ORCPT ); Tue, 10 May 2022 14:30:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348885AbiEJSap (ORCPT ); Tue, 10 May 2022 14:30:45 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C7561573B; Tue, 10 May 2022 11:30:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652207445; x=1683743445; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7k1HLML8EiHrtt/rP2Re4XQ7J53RxaR/YSDTSazTTZk=; b=Zbb2wA6vwfQHib7wqPf7Ddyln6BvCkRHc5CHbrvTKHVI+G9lZE4v9DAS lvJEPr6Y7tFDQX4TZtcSlAGoHGQzZiqprhghME3xbFEGFuU5wIkEPzWL8 3hsM+gaIc7a40vAN/9K5Ty4PQEgK8FZ520Z8vSd+7ayUA72Gtu4nKZ0SQ UPRidi0gj/PuERAAlJXZ4zEHUPZe2RWTu6/+KtNzxv0DY/9hkMOSIp/M8 WKeuQ6j5HYa+RG0x3ltEsHAb85P1NUf3cK74xfZZXv1R0pJD2zE1UHq29 zNX3fNmLwB1nRaoHugElkFdDsZ5PPhyqZRXcmeNl0iCnvVK0xCXJbKVYw g==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="249998290" X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="249998290" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:30:43 -0700 X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="738839903" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:30:43 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach , Krzysztof Kozlowski Subject: [PATCH v5 2/3] dt-bindings: intel: add binding for Intel n6000 Date: Tue, 10 May 2022 11:30:40 -0700 Message-Id: <20220510183041.876583-3-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220510183041.876583-1-matthew.gerlach@linux.intel.com> References: <20220510183041.876583-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matthew Gerlach Add the binding string for the Agilex based Intel n6000 board. Signed-off-by: Matthew Gerlach Acked-by: Krzysztof Kozlowski --- v3: - added Acked-by --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Doc= umentation/devicetree/bindings/arm/intel,socfpga.yaml index 6e043459fcd5..61a454a40e87 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - intel,n5x-socdk + - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk - const: intel,socfpga-agilex =20 --=20 2.25.1 From nobody Sun May 10 09:54:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11444C433EF for ; Tue, 10 May 2022 18:31:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348949AbiEJSaz (ORCPT ); Tue, 10 May 2022 14:30:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348906AbiEJSaq (ORCPT ); Tue, 10 May 2022 14:30:46 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50E7515825; Tue, 10 May 2022 11:30:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652207445; x=1683743445; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Rj7oGtN5LoVAeeqFFjCZt1C5yNvjDB+nOkDtsQLjZRE=; b=DxX04RxOwgppvIbniOgoIIdA5mLSD4+DRRQRfH417fqL5hq+JhIrS5C7 QY4GNNzWtzHPOlOzK8LeViFSDRNzI9yD0vhJnzeM1yS/L33U1fZ/wRPc6 WSnX6zGD20Odr5vug/E+VDiFcv5hinhlkiAKC2twba/xjGZG0/k4Bxv9f Hw17atR1SoeMrufMkxZq0Sk2zafu6usuTnavrccejdJq4YcBbk9vAqgGP 41n8zq4MbX+yiSw/sOQnpm/IAcJ9ZA7M0wUhRhktFPnzOBQmQPfvDAnCy xjL2XWJ3ODyjdYavEwRVN3A06bjCTDZgZ958S0+rruOJu/Fnsou5LqJW6 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10343"; a="249998292" X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="249998292" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:30:43 -0700 X-IronPort-AV: E=Sophos;i="5.91,214,1647327600"; d="scan'208";a="738839904" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 May 2022 11:30:43 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach , Krzysztof Kozlowski Subject: [PATCH v5 3/3] arm64: dts: intel: add device tree for n6000 Date: Tue, 10 May 2022 11:30:41 -0700 Message-Id: <20220510183041.876583-4-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220510183041.876583-1-matthew.gerlach@linux.intel.com> References: <20220510183041.876583-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matthew Gerlach Add a device tree for the n6000 instantiation of Agilex Hard Processor System (HPS). Signed-off-by: Matthew Gerlach Acked-by: Krzysztof Kozlowski --- v5: - add Acked-by: Krzysztof Kozlowski v3: - add unit number to memory node - remove unused label - remove 0x from #address-cells/#size-cells values - change hps_cp_eng@0 to dma-controller@0 - remove spi node with unaccepted compatible value v2: - fix copy engine node name - fix compatible field for copy engine - remove redundant status field - add compatibility field for the board - fix SPDX - fix how osc1 clock frequency is set --- arch/arm64/boot/dts/intel/Makefile | 3 +- .../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel= /Makefile index 0b5477442263..c2a723838344 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D socfpga_agilex_socdk.dtb \ +dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D socfpga_agilex_n6000.dtb \ + socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) +=3D keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm6= 4/boot/dts/intel/socfpga_agilex_n6000.dts new file mode 100644 index 000000000000..6231a69204b1 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021-2022, Intel Corporation + */ +#include "socfpga_agilex.dtsi" + +/ { + model =3D "SoCFPGA Agilex n6000"; + compatible =3D "intel,socfpga-agilex-n6000", "intel,socfpga-agilex"; + + aliases { + serial0 =3D &uart1; + serial1 =3D &uart0; + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + ethernet2 =3D &gmac2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@0 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the reg */ + reg =3D <0 0 0 0>; + }; + + soc { + bus@80000000 { + compatible =3D "simple-bus"; + reg =3D <0x80000000 0x60000000>, + <0xf9000000 0x00100000>; + reg-names =3D "axi_h2f", "axi_h2f_lw"; + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges =3D <0x00000000 0x00000000 0xf9000000 0x00001000>; + + dma-controller@0 { + compatible =3D "intel,hps-copy-engine"; + reg =3D <0x00000000 0x00000000 0x00001000>; + #dma-cells =3D <1>; + }; + }; + }; +}; + +&osc1 { + clock-frequency =3D <25000000>; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&watchdog0 { + status =3D "okay"; +}; + +&fpga_mgr { + status =3D "disabled"; +}; --=20 2.25.1