From nobody Sun May 10 21:18:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0CADC433F5 for ; Mon, 9 May 2022 18:29:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240186AbiEISdm (ORCPT ); Mon, 9 May 2022 14:33:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240185AbiEISdj (ORCPT ); Mon, 9 May 2022 14:33:39 -0400 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0AC52B09D8 for ; Mon, 9 May 2022 11:29:44 -0700 (PDT) Received: by mail-pf1-x433.google.com with SMTP id y41so8137935pfw.12 for ; Mon, 09 May 2022 11:29:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=HT8JD8HOTg70SDyIzNGh8qklo/ybWwxwLyVZIAu4uKc=; b=XcvLTWGxN4frUHzM4LzCHdAuFx3DpO20/OXKwC2zVshCYLJaALwhqZIRXwaXuun6OA gwtIPYUj8zYlJGRfZpiR/xVyPUYBP58JmN68uPjbdKjbpGg3Th2W16JOjKWNOB3LxWd4 iWp1/IaoAx7+oCYctKVczAa6fFdOvkoVFg2hPG/ks0+DECCoo14DWpdUleauO0QAY/Lb uaTxBtvLt1hevoDrFbYIppb2fVwy+IdqvduULR3vLQn9RJYoI75+KKP/4kbExVvFgkpv n4DvUXLPNOOLQpaVSAgsIGfPY9P7auJjP9FtCLlZMZOI979Eeeres3CyWxbQibIJYuVQ H0+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=HT8JD8HOTg70SDyIzNGh8qklo/ybWwxwLyVZIAu4uKc=; b=OIOddgv+GEJZ6ErKZFNCsGtV3yeuq7c/yfL+kqMCj0d1usdk7Oml8Ls4Vtz2TV42no TcuAeDNgnYG2J/eLP1SppA730Yr/iz6H5t/E+oAE7vfNS1pNxzzHj/O5i+SNZ1k6XBmR MxE/RfbQ+ZwVKJj6S7piDWZlp2B8qHYQxdXUbEydew2qotg4YhZUt1DNfhSeirFPz9EI +PfB8Q+hq3hZrBlKZZ3+TI7KXRrlgvdx1pLpx6uyLJSaXksVoNjXD8N4zKMSOG4h+uh9 RdPZVgoGBySumwa/pXxf7g+qABVd1/BRxtba87z9YgrtLTdHWI72ygWKwokWm0ULcbac fpGA== X-Gm-Message-State: AOAM5328ZG9H9mKsGmlGFdv843pr3rglLo0yBuuFCXel8MbUT8rIOx4L jZcc9DaaHSU17UiAPYO0qvV2Iw== X-Google-Smtp-Source: ABdhPJzSD1S4Vbwz090UVw92it+rCH+3IIV0yVjA3VXqDucYwpY7LMkmNRSFkJFpxGMCjeM1K3cCpA== X-Received: by 2002:a05:6a00:16c7:b0:4f7:e497:69b8 with SMTP id l7-20020a056a0016c700b004f7e49769b8mr17070165pfc.6.1652120984019; Mon, 09 May 2022 11:29:44 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id d20-20020a170902aa9400b0015ebbaccc46sm177241plr.159.2022.05.09.11.29.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 11:29:43 -0700 (PDT) From: Atish Patra To: kvm@vger.kernel.org Cc: Atish Patra , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , kvm-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3] RISC-V: KVM: Introduce ISA extension register Date: Mon, 9 May 2022 11:29:37 -0700 Message-Id: <20220509182937.1881849-1-atishp@rivosinc.com> X-Mailer: git-send-email 2.36.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, there is no provision for vmm (qemu-kvm or kvmtool) to query about multiple-letter ISA extensions. The config register is only used for base single letter ISA extensions. A new ISA extension register is added that will allow the vmm to query about any ISA extension one at a time. It is enabled for both single letter or multi-letter ISA extensions. The ISA extension register is useful to if the vmm requires to retrieve/set single extension while the config register should be used if all the base ISA extension required to retrieve or set. For any multi-letter ISA extensions, the new register interface must be used. Signed-off-by: Atish Patra --- Changes from v2->v3: 1. Fixed the comment style. 2. Fixed the kvm_riscv_vcpu_get_reg_isa_ext function. --- arch/riscv/include/uapi/asm/kvm.h | 20 +++++++ arch/riscv/kvm/vcpu.c | 99 +++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index f808ad1ce500..92bd469e2ba6 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -82,6 +82,23 @@ struct kvm_riscv_timer { __u64 state; }; =20 +/** + * ISA extension IDs specific to KVM. This is not the same as the host ISA + * extension IDs as that is internal to the host and should not be exposed + * to the guest. This should always be contiguous to keep the mapping simp= le + * in KVM implementation. + */ +enum KVM_RISCV_ISA_EXT_ID { + KVM_RISCV_ISA_EXT_A =3D 0, + KVM_RISCV_ISA_EXT_C, + KVM_RISCV_ISA_EXT_D, + KVM_RISCV_ISA_EXT_F, + KVM_RISCV_ISA_EXT_H, + KVM_RISCV_ISA_EXT_I, + KVM_RISCV_ISA_EXT_M, + KVM_RISCV_ISA_EXT_MAX, +}; + /* Possible states for kvm_riscv_timer */ #define KVM_RISCV_TIMER_STATE_OFF 0 #define KVM_RISCV_TIMER_STATE_ON 1 @@ -123,6 +140,9 @@ struct kvm_riscv_timer { #define KVM_REG_RISCV_FP_D_REG(name) \ (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) =20 +/* ISA Extension registers are mapped as type 7 */ +#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT) + #endif =20 #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 7461f964d20a..0875beaa1973 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -365,6 +365,101 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu= *vcpu, return 0; } =20 +/* Mapping between KVM ISA Extension ID & Host ISA extension ID */ +static unsigned long kvm_isa_ext_arr[] =3D { + RISCV_ISA_EXT_a, + RISCV_ISA_EXT_c, + RISCV_ISA_EXT_d, + RISCV_ISA_EXT_f, + RISCV_ISA_EXT_h, + RISCV_ISA_EXT_i, + RISCV_ISA_EXT_m, +}; + +static int kvm_riscv_vcpu_get_reg_isa_ext(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + unsigned long __user *uaddr =3D + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_ISA_EXT); + unsigned long reg_val =3D 0; + unsigned long host_isa_ext; + + if (KVM_REG_SIZE(reg->id) !=3D sizeof(unsigned long)) + return -EINVAL; + + if (reg_num >=3D KVM_RISCV_ISA_EXT_MAX || reg_num >=3D ARRAY_SIZE(kvm_isa= _ext_arr)) + return -EINVAL; + + host_isa_ext =3D kvm_isa_ext_arr[reg_num]; + if (__riscv_isa_extension_available(&vcpu->arch.isa, host_isa_ext)) + reg_val =3D 1; /* Mark the given extension as available */ + + if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + return 0; +} + +static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + unsigned long __user *uaddr =3D + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + KVM_REG_RISCV_ISA_EXT); + unsigned long reg_val; + unsigned long host_isa_ext; + unsigned long host_isa_ext_mask; + + if (KVM_REG_SIZE(reg->id) !=3D sizeof(unsigned long)) + return -EINVAL; + + if (reg_num >=3D KVM_RISCV_ISA_EXT_MAX || reg_num >=3D ARRAY_SIZE(kvm_isa= _ext_arr)) + return -EINVAL; + + if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) + return -EFAULT; + + host_isa_ext =3D kvm_isa_ext_arr[reg_num]; + if (!__riscv_isa_extension_available(NULL, host_isa_ext)) + return -EOPNOTSUPP; + + if (host_isa_ext >=3D RISCV_ISA_EXT_BASE && + host_isa_ext < RISCV_ISA_EXT_MAX) { + /* + * Multi-letter ISA extension. Currently there is no provision + * to enable/disable the multi-letter ISA extensions for guests. + * Return success if the request is to enable any ISA extension + * that is available in the hardware. + * Return -EOPNOTSUPP otherwise. + */ + if (!reg_val) + return -EOPNOTSUPP; + else + return 0; + } + + /* Single letter base ISA extension */ + if (!vcpu->arch.ran_atleast_once) { + host_isa_ext_mask =3D BIT_MASK(host_isa_ext); + if (!reg_val && (host_isa_ext_mask & KVM_RISCV_ISA_DISABLE_ALLOWED)) + vcpu->arch.isa &=3D ~host_isa_ext_mask; + else + vcpu->arch.isa |=3D host_isa_ext_mask; + vcpu->arch.isa &=3D riscv_isa_extension_base(NULL); + vcpu->arch.isa &=3D KVM_RISCV_ISA_ALLOWED; + kvm_riscv_vcpu_fp_reset(vcpu); + } else { + return -EOPNOTSUPP; + } + + return 0; +} + static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -382,6 +477,8 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_D) return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, KVM_REG_RISCV_FP_D); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_ISA_EXT) + return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg); =20 return -EINVAL; } @@ -403,6 +500,8 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_D) return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, KVM_REG_RISCV_FP_D); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_ISA_EXT) + return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg); =20 return -EINVAL; } --=20 2.36.0