From nobody Sun Sep 22 01:38:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6091AC4332F for ; Mon, 9 May 2022 10:21:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230255AbiEIKZn (ORCPT ); Mon, 9 May 2022 06:25:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233774AbiEIKZO (ORCPT ); Mon, 9 May 2022 06:25:14 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B506201EA8; Mon, 9 May 2022 03:21:11 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id C5C011F4376E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1652091669; bh=olbInTBcsJ7OBs0Az64gQWO87DN9MjbVGnMzsKIcrgw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Lvi3SIcfXeRf4XU7UFmELdSoDYNvwzyS+GodMXAeztXY501u1tqhVvhHK5ok97XaR NJTLdS9FxXSHmbeoOkHfxfGyRROOOLGktuQYN6qL4XGPYFVyW4mNkDEvpfAfAN5hDE YsQ8jVB+BdjEQphUehmPmxRibikOUzaBKYAWOtYulS1KGWQdQCh5uTRIcXFcm8k2AQ SUEa5i1SzrSJWrJ8sx6nmcaa8bHcl9y2+oLResDfgece6cPW9nFdo17gtwFD8ehmzU hwJgL3Wld7ukzwGviCsC9GcU4uIkX6RQmUFx7okjDOy8Yp6QqxXCBOZDegZ9mppqxQ 3s/kCoV9quA6w== From: AngeloGioacchino Del Regno To: daniel.lezcano@linaro.org Cc: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, AngeloGioacchino Del Regno Subject: [PATCH 1/2] dt-bindings: timer: mediatek: Add CPUX System Timer and MT6795 compatible Date: Mon, 9 May 2022 12:20:57 +0200 Message-Id: <20220509102058.3064215-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220509102058.3064215-1-angelogioacchino.delregno@collabora.com> References: <20220509102058.3064215-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the "CPUXGPT" CPU General Purpose Timer, used as ARM/ARM64 System Timer on MediaTek platforms and add the MT6795 compatible for it. Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/timer/mediatek,mtk-timer.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt= b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index fbd76a8e023b..2d139d24e535 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -2,6 +2,7 @@ MediaTek Timers --------------- =20 MediaTek SoCs have two different timers on different platforms, +- CPUX (ARM/ARM64 System Timer) - GPT (General Purpose Timer) - SYST (System Timer) =20 @@ -28,6 +29,9 @@ Required properties: * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYS= T) =20 + For those SoCs that use CPUX + * "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX) + - reg: Should contain location and length for timer register. - clocks: Should contain system clock. =20 --=20 2.35.1 From nobody Sun Sep 22 01:38:10 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C82BC433F5 for ; Mon, 9 May 2022 10:22:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233774AbiEIK0B (ORCPT ); Mon, 9 May 2022 06:26:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233751AbiEIKZO (ORCPT ); Mon, 9 May 2022 06:25:14 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 638C2205240; Mon, 9 May 2022 03:21:12 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: kholk11) with ESMTPSA id CC5BA1F43775 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1652091670; bh=N/xFCvKpoAZh2zlF3Dq+42C4SMmmwu82wr+2m9ru8DI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=K1fUD82gaTaVnXZwBd5AmniwgMGLLSxTb3Lo6efhswnak254z65tHgqpYHX1hs/FI WWA9K+ZUbzVg3Qy8NUOjX36ky77R0rGW1Wt7ivpxrgy6G2hhuNUwTC9UIPsC04byve Hx4ZUvB0kbvlB4j/ybfE8b2dr5k7/3m5IzqYwWzRo7KR1GVhUEMebitfs/4B7fQeoX LgiJYuNmgjRG6377OqwYtAmOlY2/VzpytNednxZa/ENYUF+FqRPnWlc7j5PQRpj3XC qOm5xhaGf3pkqw11qxuAdzAfOmMQMRzu/J7ZpRI+d8BssyHeKAoL9ucKfWRn9J2F0A yVyAkMmdePjxQ== From: AngeloGioacchino Del Regno To: daniel.lezcano@linaro.org Cc: tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, konrad.dybcio@somainline.org, marijn.suijten@somainline.org, martin.botka@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, paul.bouchara@somainline.org, AngeloGioacchino Del Regno Subject: [PATCH 2/2] clocksource/drivers/timer-mediatek: Implement CPUXGPT timers Date: Mon, 9 May 2022 12:20:58 +0200 Message-Id: <20220509102058.3064215-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220509102058.3064215-1-angelogioacchino.delregno@collabora.com> References: <20220509102058.3064215-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some MediaTek platforms with a buggy TrustZone ATF firmware will not initialize the AArch64 System Timer correctly: in these cases, the System Timer address is correctly programmed, as well as the CNTFRQ_EL0 register (reading 13MHz, as it should be), but the assigned hardware timers are never started before (or after) booting Linux. In this condition, any call to function get_cycles() will be returning zero, as CNTVCT_EL0 will always read zero. One common critical symptom of that is trying to use the udelay() function (calling __delay()), which executes the following loop: start =3D get_cycles(); while ((get_cycles() - start) < cycles) cpu_relax(); which, when CNTVCT_EL0 always reads zero, translates to: while((0 - 0) < 0) =3D=3D> while(0 < 0) ... generating an infinite loop, even though zero is never less than zero, but always equal to it (this has to be researched, but it's out of the scope of this commit). To fix this issue on the affected MediaTek platforms, the solution is to simply start the timers that are designed to be System Timer(s). These timers, downstream, are called "CPUXGPT" and there is one timer per CPU core; luckily, it is not necessary to set a start bit on each CPUX General Purpose Timer, but it's conveniently enough to: - Set the clock divider (input =3D 26MHz, divider =3D 2, output =3D 13MHz); - Set the ENABLE bit on a global register (starts all CPUX timers). The only small hurdle with this setup is that it's all done through the MCUSYS wrapper, where it is needed, for each read or write, to select a register address (by writing it to an index register) and then to perform any R/W on a "CON" register. For example, writing "0x1" to the CPUXGPT register offset 0x4: - Write 0x4 to mcusys INDEX register - Write 0x1 to mcusys CON register Reading from CPUXGPT register offset 0x4: - Write 0x4 to mcusys INDEX register - Read mcusys CON register. Finally, starting this timer makes platforms affected by this issue to work correctly. Signed-off-by: AngeloGioacchino Del Regno Reported-by: kernel test robot --- drivers/clocksource/timer-mediatek.c | 118 +++++++++++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/tim= er-mediatek.c index 7bcb4a3f26fb..52120bba29c4 100644 --- a/drivers/clocksource/timer-mediatek.c +++ b/drivers/clocksource/timer-mediatek.c @@ -22,6 +22,19 @@ =20 #define TIMER_SYNC_TICKS (3) =20 +/* cpux mcusys wrapper */ +#define CPUX_CON_REG 0x0 +#define CPUX_IDX_REG 0x4 + +/* cpux */ +#define CPUX_IDX_GLOBAL_CTRL 0x0 + #define CPUX_ENABLE BIT(0) + #define CPUX_CLK_DIV_MASK GENMASK(10, 8) + #define CPUX_CLK_DIV1 BIT(8) + #define CPUX_CLK_DIV2 BIT(9) + #define CPUX_CLK_DIV4 BIT(10) +#define CPUX_IDX_GLOBAL_IRQ 0x30 + /* gpt */ #define GPT_IRQ_EN_REG 0x00 #define GPT_IRQ_ENABLE(val) BIT((val) - 1) @@ -72,6 +85,56 @@ =20 static void __iomem *gpt_sched_reg __read_mostly; =20 +static u32 mtk_cpux_readl(u32 reg_idx, struct timer_of *to) +{ + writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG); + return readl(timer_of_base(to) + CPUX_CON_REG); +} + +static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to) +{ + writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG); + writel(val, timer_of_base(to) + CPUX_CON_REG); +} + +static void mtk_cpux_disable_irq(struct timer_of *to) +{ + const unsigned long *irq_mask =3D cpumask_bits(cpu_possible_mask); + u32 val; + + val =3D mtk_cpux_readl(CPUX_IDX_GLOBAL_IRQ, to); + val &=3D ~(*irq_mask); +} + +static void mtk_cpux_enable_irq(struct timer_of *to) +{ + const unsigned long *irq_mask =3D cpumask_bits(cpu_possible_mask); + u32 val; + + val =3D mtk_cpux_readl(CPUX_IDX_GLOBAL_IRQ, to); + val |=3D *irq_mask; + mtk_cpux_writel(val, CPUX_IDX_GLOBAL_IRQ, to); +} + +static int mtk_cpux_clkevt_shutdown(struct clock_event_device *clkevt) +{ + /* Clear any irq */ + mtk_cpux_disable_irq(to_timer_of(clkevt)); + + /* + * Disabling CPUXGPT timer will crash the platform, especially + * if Trusted Firmware is using it (usually, for sleep states), + * so we only mask the IRQ and call it a day. + */ + return 0; +} + +static int mtk_cpux_clkevt_resume(struct clock_event_device *clkevt) +{ + mtk_cpux_enable_irq(to_timer_of(clkevt)); + return 0; +} + static void mtk_syst_ack_irq(struct timer_of *to) { /* Clear and disable interrupt */ @@ -281,6 +344,60 @@ static struct timer_of to =3D { }, }; =20 +static int __init mtk_cpux_init(struct device_node *node) +{ + static struct timer_of to_cpux; + u32 freq, val; + int ret; + + /* + * There are per-cpu interrupts for the CPUX General Purpose Timer + * but since this timer feeds the AArch64 System Timer we can rely + * on the CPU timer PPIs as well, so we don't declare TIMER_OF_IRQ. + */ + to_cpux.flags =3D TIMER_OF_BASE | TIMER_OF_CLOCK; + to_cpux.clkevt.name =3D "mtk-cpuxgpt"; + to_cpux.clkevt.rating =3D 10; + to_cpux.clkevt.cpumask =3D cpu_possible_mask; + to_cpux.clkevt.set_state_shutdown =3D mtk_cpux_clkevt_shutdown; + to_cpux.clkevt.tick_resume =3D mtk_cpux_clkevt_resume; + + /* If this fails, bad things are about to happen... */ + ret =3D timer_of_init(node, &to_cpux); + if (ret) { + WARN(1, "Cannot start CPUX timers.\n"); + return ret; + } + + /* + * Check if we're given a clock with the right frequency for this + * timer, otherwise warn but keep going with the setup anyway, as + * that makes it possible to still boot the kernel, even though + * it may not work correctly (random lockups, etc). + * The reason behind this is that having an early UART may not be + * possible for everyone and this gives a chance to retrieve kmsg + * for eventual debugging even on consumer devices. + */ + freq =3D timer_of_rate(&to_cpux); + if (freq > 13000000) + WARN(1, "Requested unsupported timer frequency %u\n", freq); + + /* Clock input is 26MHz, set DIV2 to achieve 13MHz clock */ + val =3D mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to_cpux); + val &=3D ~CPUX_CLK_DIV_MASK; + val |=3D CPUX_CLK_DIV2; + mtk_cpux_writel(val, CPUX_IDX_GLOBAL_CTRL, &to_cpux); + + /* Enable all CPUXGPT timers */ + val =3D mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to_cpux); + mtk_cpux_writel(val | CPUX_ENABLE, CPUX_IDX_GLOBAL_CTRL, &to_cpux); + + clockevents_config_and_register(&to_cpux.clkevt, timer_of_rate(&to_cpux), + TIMER_SYNC_TICKS, 0xffffffff); + + return 0; +} + static int __init mtk_syst_init(struct device_node *node) { int ret; @@ -339,3 +456,4 @@ static int __init mtk_gpt_init(struct device_node *node) } TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init); TIMER_OF_DECLARE(mtk_mt6765, "mediatek,mt6765-timer", mtk_syst_init); +TIMER_OF_DECLARE(mtk_mt6795, "mediatek,mt6795-systimer", mtk_cpux_init); --=20 2.35.1