From nobody Fri May 8 06:49:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B947C433FE for ; Mon, 9 May 2022 08:57:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237120AbiEII5o (ORCPT ); Mon, 9 May 2022 04:57:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237123AbiEIIxa (ORCPT ); Mon, 9 May 2022 04:53:30 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82A0D18B94C; Mon, 9 May 2022 01:49:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1652086175; x=1683622175; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=6lCNDnYJkosgYLV0xK1CqQWOhk+Z+YnHv527i+VzDNc=; b=Ki7RJTVEOmepcsCr07bt1kixKXZ4EKjEsaReSod9Z2MWJwtatB9qmNYI mruN1lzT0dSyQL5LRy5dfD/ZQZI8fgvSEDw4MWIJ5GnmdQ5GMAFNoraSu i58QC/8ggESgBG75HLWfHHib7YQTMmShHpO4iB3Svgmgj/mQttolZA+MR v0B1A+ShjBNE7PGSdbXqOPBFA+nGoVf9X+WFRhKoG9+JF+eedAYtm3t/7 cIEZd6ULpW/GRNCZ5MXnkkSQM0fC6x1hf3P3nz+mpHuynX2y/7aFkGbjk LpL8TVzJl7Um4JeaYbLEnDHqX2VfqhExUtZjCVK2qkKCkIrL8ajBqW/Up g==; X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="163212300" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 May 2022 01:49:34 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 9 May 2022 01:49:34 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 9 May 2022 01:49:29 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , , , Subject: [PATCH v2 1/4] dt-bindings: mfd: atmel,flexcom: Convert to json-schema Date: Mon, 9 May 2022 14:19:17 +0530 Message-ID: <20220509084920.14529-2-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> References: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert the Atmel flexcom device tree bindings to json schema. Signed-off-by: Kavyasree Kotagiri --- .../bindings/mfd/atmel,flexcom.yaml | 92 +++++++++++++++++++ .../devicetree/bindings/mfd/atmel-flexcom.txt | 63 ------------- 2 files changed, 92 insertions(+), 63 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-flexcom.txt diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Doc= umentation/devicetree/bindings/mfd/atmel,flexcom.yaml new file mode 100644 index 000000000000..79ec7ebc7055 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,flexcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device tree bindings for Atmel Flexcom (Flexible Serial Communicati= on Unit) + +maintainers: + - Kavyasree Kotagiri + +description: + The Atmel Flexcom is just a wrapper which embeds a SPI controller, + an I2C controller and an USART. Only one function can be used at a + time and is chosen at boot time according to the device tree. + +properties: + compatible: + const: atmel,sama5d2-flexcom + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: + description: + One range for the full I/O register region. (including USART, + TWI and SPI registers). + items: + maxItems: 3 + + atmel,flexcom-mode: + description: | + Specifies the flexcom mode as follows: + 1: USART + 2: SPI + 3: I2C. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + - ranges + - atmel,flexcom-mode + +additionalProperties: false + +patternProperties: + "^serial@[0-9a-f]+$": + description: See atmel-usart.txt for details of USART bindings. + "^spi@[0-9a-f]+$": + description: See ../spi/spi_atmel.txt for details of SPI bindings. + "^i2c@[0-9a-f]+$": + description: See ../i2c/i2c-at91.txt for details of I2C bindings. + +examples: + - | + flx0: flexcom@f8034000 { + compatible =3D "atmel,sama5d2-flexcom"; + reg =3D <0xf8034000 0x200>; + clocks =3D <&flx0_clk>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xf8034000 0x800>; + atmel,flexcom-mode =3D <2>; + + spi0: spi@400 { + compatible =3D "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <19 4 7>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flx0_default>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&flx0_clk>; + clock-names =3D "spi_clk"; + atmel,fifo-size =3D <32>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt b/Docu= mentation/devicetree/bindings/mfd/atmel-flexcom.txt deleted file mode 100644 index 692300117c64..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-flexcom.txt +++ /dev/null @@ -1,63 +0,0 @@ -* Device tree bindings for Atmel Flexcom (Flexible Serial Communication Un= it) - -The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C -controller and an USART. Only one function can be used at a time and is ch= osen -at boot time according to the device tree. - -Required properties: -- compatible: Should be "atmel,sama5d2-flexcom" -- reg: Should be the offset/length value for Flexcom dedicated - I/O registers (without USART, TWI or SPI registers). -- clocks: Should be the Flexcom peripheral clock from PMC. -- #address-cells: Should be <1> -- #size-cells: Should be <1> -- ranges: Should be one range for the full I/O register region - (including USART, TWI and SPI registers). -- atmel,flexcom-mode: Should be one of the following values: - - <1> for USART - - <2> for SPI - - <3> for I2C - -Required child: -A single available child device of type matching the "atmel,flexcom-mode" -property. - -The phandle provided by the clocks property of the child is the same as on= e for -the Flexcom parent. - -For other properties, please refer to the documentations of the respective -device: -- ../serial/atmel-usart.txt -- ../spi/spi_atmel.txt -- ../i2c/i2c-at91.txt - -Example: - -flexcom@f8034000 { - compatible =3D "atmel,sama5d2-flexcom"; - reg =3D <0xf8034000 0x200>; - clocks =3D <&flx0_clk>; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges =3D <0x0 0xf8034000 0x800>; - atmel,flexcom-mode =3D <2>; - - spi@400 { - compatible =3D "atmel,at91rm9200-spi"; - reg =3D <0x400 0x200>; - interrupts =3D <19 IRQ_TYPE_LEVEL_HIGH 7>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_flx0_default>; - #address-cells =3D <1>; - #size-cells =3D <0>; - clocks =3D <&flx0_clk>; - clock-names =3D "spi_clk"; - atmel,fifo-size =3D <32>; - - mtd_dataflash@0 { - compatible =3D "atmel,at25f512b"; - reg =3D <0>; - spi-max-frequency =3D <20000000>; - }; - }; -}; --=20 2.17.1 From nobody Fri May 8 06:49:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A788C433EF for ; Mon, 9 May 2022 08:53:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235599AbiEII5O (ORCPT ); Mon, 9 May 2022 04:57:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232093AbiEIIxr (ORCPT ); Mon, 9 May 2022 04:53:47 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F6DA248E0; Mon, 9 May 2022 01:49:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1652086195; x=1683622195; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=n8bFpjbKPYvw3e9bni1/T6bQ+4R6TyrCTJBZUgNett4=; b=DJbo119jsIT9ILlPUqLtxyaharrZlZM9b82hjGBbBVXKRmCAVkKigxKq PrG894/dqrNNZq+kImyQ0sDZnEj/GeDqVSZ0LaPbzCrnsdobYaQ6v2aWs 84spgHeaowncODVVSjnoj847puOk1cQKcJepr0T4FAZTtCZH8mTrlic1W SEVxG9S4I0f2Rtvtt431cB/Xonjv2ZHJYttzSE4FfPwZpcOgPe5cD+n1k M3L/42eFa868U5udhPKj66WRZ7bnhOk91IcXDwW65TzBECTzbnpzOVdtp 9GEwLWVO5R1/odEzJGDJWUax8kvZuNfhJ8yWPa6wBFuOBztxq1tOFKDSo g==; X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="162812532" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 May 2022 01:49:44 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 9 May 2022 01:49:42 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 9 May 2022 01:49:37 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , , , Subject: [PATCH v2 2/4] dt-bindings: mfd: atmel,flexcom: Add lan966 compatible string and mux properties Date: Mon, 9 May 2022 14:19:18 +0530 Message-ID: <20220509084920.14529-3-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> References: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add lan966 flexcom compatible string and flexcom mux device tree properties. Signed-off-by: Kavyasree Kotagiri --- .../bindings/mfd/atmel,flexcom.yaml | 52 ++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml b/Doc= umentation/devicetree/bindings/mfd/atmel,flexcom.yaml index 79ec7ebc7055..228c095c84ca 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,flexcom.yaml @@ -16,7 +16,9 @@ description: =20 properties: compatible: - const: atmel,sama5d2-flexcom + enum: + - atmel,sama5d2-flexcom + - microchip,lan966-flexcom =20 reg: maxItems: 1 @@ -57,6 +59,27 @@ required: =20 additionalProperties: false =20 +allOf: + - if: + properties: + compatible: + contains: + const: microchip,lan966-flexcom + + then: + properties: + mux-controls: + minItems: 1 + maxItems: 2 + $ref: /schemas/types.yaml#/definitions/phandle-array + + mux-control-names: + minItems: 1 + $ref: ../mux/mux-consumer.yaml + items: + - const: cs0 + - const: cs1 + patternProperties: "^serial@[0-9a-f]+$": description: See atmel-usart.txt for details of USART bindings. @@ -89,4 +112,31 @@ examples: atmel,fifo-size =3D <32>; }; }; + + - | + flx3: flexcom@e0064000 { + compatible =3D "microchip,lan966-flexcom"; + reg =3D <0xe0064000 0x100>; + clocks =3D <&fabric_clk>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0xe0064000 0x800>; + atmel,flexcom-mode =3D <2>; + mux-controls =3D <&mux 0>; + mux-control-names =3D "cs0"; + + spi3: spi@400 { + compatible =3D "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D <0 51 4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&fabric_clk>; + clock-names =3D "spi_clk"; + pinctrl-0 =3D <&fc3_b_sck_pins>, <&fc3_b_rxd_pins>, + <&fc3_b_txd_pins>, <&fc_shrd9_pins>; + pinctrl-names =3D "default"; + atmel,fifo-size =3D <32>; + }; + }; ... --=20 2.17.1 From nobody Fri May 8 06:49:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE478C38161 for ; Mon, 9 May 2022 08:57:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237775AbiEII7f (ORCPT ); Mon, 9 May 2022 04:59:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235691AbiEIIx4 (ORCPT ); Mon, 9 May 2022 04:53:56 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D48E1F639C; Mon, 9 May 2022 01:50:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1652086200; x=1683622200; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=P1qgV17lnh2akycIs/7RD3U7hySjZfZcLWGAANbzE+U=; b=AafctKHDrq8rWkdEnNDJnybSUa6WZFHoFUiefQ6O/oS06AHMbmNl1PXc SLGLbpxdkwJQorwXAKSWZyax+kG/Ez8JdUDlSPRekVgkApyJQMejXCUhi YsvFDjXXE31VNcO4j1dijIjQ3xdEyRkv8Mbw2e09eT1K3TIPpC34Wk4ps F5vk331qB93/ePDyIx89XsHt0Q4kSywTFQ1IVojw/8Xi7KMYgZLHDU/AZ PeCv46IcNRN9ao05fLLVTU+A5T1bTvYCKqPBXFYyBeZKKVtiavuMFGUD9 3oAg1+KG/aBHw69XShTwFN3aKVzaueyDbpc/6SkBFWQC0KPcDP/CU+ysT w==; X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="172473008" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 May 2022 01:49:49 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 9 May 2022 01:49:48 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 9 May 2022 01:49:43 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , , , Subject: [PATCH v2 3/4] dt-bindings: mux: Add lan966 flexcom mux controller Date: Mon, 9 May 2022 14:19:19 +0530 Message-ID: <20220509084920.14529-4-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> References: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This adds DT bindings documentation for lan966 flexcom mux controller. Signed-off-by: Kavyasree Kotagiri --- .../mux/microchip,lan966-flx-mux.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mux/microchip,lan966-= flx-mux.yaml diff --git a/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux= .yaml b/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml new file mode 100644 index 000000000000..63147a2e8f3a --- /dev/null +++ b/Documentation/devicetree/bindings/mux/microchip,lan966-flx-mux.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/microchip,lan966-flx-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Lan966 Flexcom multiplexer bindings + +maintainers: + - Kavyasree Kotagiri + +description: |+ + The Microchip Lan966 have 5 Flexcoms. Each flexcom has 2 chip-selects + when operating in USART and SPI modes. + Each chip select of each flexcom can be mapped to 21 flexcom shared pins. + Define register offset and pin number to map a flexcom chip-select + to flexcom shared pin. + +allOf: + - $ref: /schemas/mux/mux-controller.yaml# + +properties: + compatible: + const: microchip,lan966-flx-mux + + reg: + maxItems: 1 + + '#mux-control-cells': + const: 1 + + mux-offset-pin: + description: an array of register offset and flexcom shared pin(0-20). + +required: + - compatible + - reg + - '#mux-control-cells' + - mux-offset-pin + +additionalProperties: false + +examples: + - | + mux: mux-controller@e2004168 { + compatible =3D "microchip,lan966-flx-mux"; + reg =3D <0xe2004168 0x8>; + #mux-control-cells =3D <1>; + mux-offset-pin =3D <0x18 9>; /* 0: flx3 cs0 offset, pin-9 */ + }; +... --=20 2.17.1 From nobody Fri May 8 06:49:51 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3780FC352A8 for ; Mon, 9 May 2022 08:57:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237573AbiEII7D (ORCPT ); Mon, 9 May 2022 04:59:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235907AbiEIIx6 (ORCPT ); Mon, 9 May 2022 04:53:58 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 703341F63A6; Mon, 9 May 2022 01:50:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1652086201; x=1683622201; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=ieGfMLq5LDxsat388CrFyabnXfbuBIV0dPDiKawScOY=; b=EMJpFW7+Jf8RMq8nHFAvxrR5Y9nFEHxGs/a0seMvBmHziYolP5QGltzJ rXpxCdop1tT3C/0r47yEZs0pFvC2JkXe9wTUWr39QyXd/a0PXN11y2ZU1 GV93dPzwHzYuE3i46uLiHfPrhVTwkw2OMV7+fHuN0HLUnc1prbGTXun3Z UJHE02+KYy2eJmVaW6ADCtq4WKMdG58ZfbtDmTkDzxqnfZz9HOWdvnTzq v7uPdJ2FiWrMCbEtYgzAg+wpHknj9ZDq2SAT3f9e/UFVJhx1MUL5ymhGR dQnLP+k4wKfLmUGpAfBXWUn+l2l+SJXPs/Q18CrK2kfhmL6Kv2ZhASTrX Q==; X-IronPort-AV: E=Sophos;i="5.91,210,1647327600"; d="scan'208";a="94992693" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 09 May 2022 01:49:55 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 9 May 2022 01:49:55 -0700 Received: from kavya-HP-Compaq-6000-Pro-SFF-PC.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 9 May 2022 01:49:50 -0700 From: Kavyasree Kotagiri To: , , , , CC: , , , , , , , Subject: [PATCH v2 4/4] mux: lan966: Add support for flexcom mux controller Date: Mon, 9 May 2022 14:19:20 +0530 Message-ID: <20220509084920.14529-5-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> References: <20220509084920.14529-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LAN966 SoC have 5 flexcoms. Each flexcom has 2 chip-selects. For each chip select of each flexcom there is a configuration register FLEXCOM_SHARED[0-4]:SS_MASK[0-1]. The width of configuration register is 21 because there are 21 shared pins on each of which the chip select can be mapped. Each bit of the register represents a different FLEXCOM_SHARED pin. Signed-off-by: Kavyasree Kotagiri Reported-by: kernel test robot --- arch/arm/mach-at91/Kconfig | 2 + drivers/mfd/atmel-flexcom.c | 55 +++++++++++++++- drivers/mux/Kconfig | 12 ++++ drivers/mux/Makefile | 2 + drivers/mux/lan966-flx.c | 121 ++++++++++++++++++++++++++++++++++++ 5 files changed, 191 insertions(+), 1 deletion(-) create mode 100644 drivers/mux/lan966-flx.c diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 279810381256..26fb0f4e1b79 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -74,6 +74,8 @@ config SOC_LAN966 select DW_APB_TIMER_OF select ARM_GIC select MEMORY + select MULTIPLEXER + select MUX_LAN966 help This enables support for ARMv7 based Microchip LAN966 SoC family. =20 diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c index 559eb4d352b6..7cfd0fc3f4f0 100644 --- a/drivers/mfd/atmel-flexcom.c +++ b/drivers/mfd/atmel-flexcom.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 /* I/O register offsets */ #define FLEX_MR 0x0 /* Mode Register */ @@ -28,6 +29,10 @@ #define FLEX_MR_OPMODE(opmode) (((opmode) << FLEX_MR_OPMODE_OFFSET) & \ FLEX_MR_OPMODE_MASK) =20 +struct atmel_flex_caps { + bool has_flx_mux; +}; + struct atmel_flexcom { void __iomem *base; u32 opmode; @@ -37,6 +42,7 @@ struct atmel_flexcom { static int atmel_flexcom_probe(struct platform_device *pdev) { struct device_node *np =3D pdev->dev.of_node; + const struct atmel_flex_caps *caps; struct resource *res; struct atmel_flexcom *ddata; int err; @@ -76,13 +82,60 @@ static int atmel_flexcom_probe(struct platform_device *= pdev) */ writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR); =20 + caps =3D of_device_get_match_data(&pdev->dev); + if (!caps) { + dev_err(&pdev->dev, "Could not retrieve flexcom caps\n"); + return -EINVAL; + } + + /* Flexcom Mux */ + if (caps->has_flx_mux && of_property_read_bool(np, "mux-controls")) { + struct mux_control *flx_mux; + struct of_phandle_args args; + int i, count; + + flx_mux =3D devm_mux_control_get(&pdev->dev, NULL); + if (IS_ERR(flx_mux)) + return PTR_ERR(flx_mux); + + count =3D of_property_count_strings(np, "mux-control-names"); + for (i =3D 0; i < count; i++) { + err =3D of_parse_phandle_with_fixed_args(np, "mux-controls", 1, i, &arg= s); + if (err) + break; + + err =3D mux_control_select(flx_mux, args.args[0]); + if (!err) { + mux_control_deselect(flx_mux); + } else { + dev_err(&pdev->dev, "Failed to select FLEXCOM mux\n"); + return err; + } + } + } + clk_disable_unprepare(ddata->clk); =20 return devm_of_platform_populate(&pdev->dev); } =20 +static const struct atmel_flex_caps atmel_flexcom_caps =3D {}; + +static const struct atmel_flex_caps lan966x_flexcom_caps =3D { + .has_flx_mux =3D true, +}; + static const struct of_device_id atmel_flexcom_of_match[] =3D { - { .compatible =3D "atmel,sama5d2-flexcom" }, + { + .compatible =3D "atmel,sama5d2-flexcom", + .data =3D &atmel_flexcom_caps, + }, + + { + .compatible =3D "microchip,lan966-flexcom", + .data =3D &lan966x_flexcom_caps, + }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match); diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig index e5c571fd232c..ea09f474bc2f 100644 --- a/drivers/mux/Kconfig +++ b/drivers/mux/Kconfig @@ -45,6 +45,18 @@ config MUX_GPIO To compile the driver as a module, choose M here: the module will be called mux-gpio. =20 +config MUX_LAN966 + tristate "LAN966 Flexcom multiplexer" + depends on OF || COMPILE_TEST + help + Lan966 Flexcom Multiplexer controller. + + The driver supports mapping 2 chip-selects of each of the lan966 + flexcoms to 21 flexcom shared pins. + + To compile the driver as a module, choose M here: the module will + be called mux-lan966. + config MUX_MMIO tristate "MMIO/Regmap register bitfield-controlled Multiplexer" depends on OF || COMPILE_TEST diff --git a/drivers/mux/Makefile b/drivers/mux/Makefile index 6e9fa47daf56..53a9840d96fa 100644 --- a/drivers/mux/Makefile +++ b/drivers/mux/Makefile @@ -7,10 +7,12 @@ mux-core-objs :=3D core.o mux-adg792a-objs :=3D adg792a.o mux-adgs1408-objs :=3D adgs1408.o mux-gpio-objs :=3D gpio.o +mux-lan966-objs :=3D lan966-flx.o mux-mmio-objs :=3D mmio.o =20 obj-$(CONFIG_MULTIPLEXER) +=3D mux-core.o obj-$(CONFIG_MUX_ADG792A) +=3D mux-adg792a.o obj-$(CONFIG_MUX_ADGS1408) +=3D mux-adgs1408.o obj-$(CONFIG_MUX_GPIO) +=3D mux-gpio.o +obj-$(CONFIG_MUX_LAN966) +=3D mux-lan966.o obj-$(CONFIG_MUX_MMIO) +=3D mux-mmio.o diff --git a/drivers/mux/lan966-flx.c b/drivers/mux/lan966-flx.c new file mode 100644 index 000000000000..2c7dab616a6a --- /dev/null +++ b/drivers/mux/lan966-flx.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * LAN966 Flexcom MUX driver + * + * Copyright (c) 2022 Microchip Inc. + * + * Author: Kavyasree Kotagiri + */ + +#include +#include +#include +#include +#include +#include +#include + +#define FLEX_SHRD_MASK 0x1FFFFF +#define LAN966_MAX_CS 21 + +static void __iomem *flx_shared_base; +struct mux_lan966x { + u32 offset; + u32 ss_pin; +}; + +static int mux_lan966x_set(struct mux_control *mux, int state) +{ + struct mux_lan966x *mux_lan966x =3D mux_chip_priv(mux->chip); + u32 val; + + val =3D ~(1 << mux_lan966x[state].ss_pin) & FLEX_SHRD_MASK; + writel(val, flx_shared_base + mux_lan966x[state].offset); + + return 0; +} + +static const struct mux_control_ops mux_lan966x_ops =3D { + .set =3D mux_lan966x_set, +}; + +static const struct of_device_id mux_lan966x_dt_ids[] =3D { + { .compatible =3D "microchip,lan966-flx-mux", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mux_lan966x_dt_ids); + +static int mux_lan966x_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + struct mux_lan966x *mux_lan966x; + struct mux_chip *mux_chip; + int ret, num_fields, i; + + ret =3D of_property_count_u32_elems(np, "mux-offset-pin"); + if (ret =3D=3D 0 || ret % 2) + ret =3D -EINVAL; + if (ret < 0) + return dev_err_probe(dev, ret, + "mux-offset-pin property missing or invalid"); + num_fields =3D ret / 2; + + mux_chip =3D devm_mux_chip_alloc(dev, num_fields, sizeof(*mux_lan966x)); + if (IS_ERR(mux_chip)) + return dev_err_probe(dev, PTR_ERR(mux_chip), + "failed to allocate mux_chips\n"); + + mux_lan966x =3D mux_chip_priv(mux_chip); + + flx_shared_base =3D devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(flx_shared_base)) + return dev_err_probe(dev, PTR_ERR(flx_shared_base), + "failed to get flexcom shared base address\n"); + + for (i =3D 0; i < num_fields; i++) { + struct mux_control *mux =3D &mux_chip->mux[i]; + u32 offset, shared_pin; + + ret =3D of_property_read_u32_index(np, "mux-offset-pin", + 2 * i, &offset); + if (ret =3D=3D 0) + ret =3D of_property_read_u32_index(np, "mux-offset-pin", + 2 * i + 1, + &shared_pin); + if (ret < 0) + return dev_err_probe(dev, ret, + "failed to read mux-offset-pin property: %d", i); + + if (shared_pin >=3D LAN966_MAX_CS) + return -EINVAL; + + mux_lan966x[i].offset =3D offset; + mux_lan966x[i].ss_pin =3D shared_pin; + + mux->states =3D LAN966_MAX_CS; + } + + mux_chip->ops =3D &mux_lan966x_ops; + + ret =3D devm_mux_chip_register(dev, mux_chip); + if (ret < 0) + return ret; + + return 0; +} + +static struct platform_driver mux_lan966x_driver =3D { + .driver =3D { + .name =3D "lan966-mux", + .of_match_table =3D of_match_ptr(mux_lan966x_dt_ids), + }, + .probe =3D mux_lan966x_probe, +}; + +module_platform_driver(mux_lan966x_driver); + +MODULE_DESCRIPTION("LAN966 Flexcom multiplexer driver"); +MODULE_AUTHOR("Kavyasree Kotagiri "); +MODULE_LICENSE("GPL v2"); + --=20 2.17.1