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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id bw22-20020a0560001f9600b0020c5253d8d8sm11784768wrb.36.2022.05.09.00.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 00:49:05 -0700 (PDT) From: Corentin Labbe To: alexandre.torgue@foss.st.com, andrew@lunn.ch, broonie@kernel.org, calvin.johnson@oss.nxp.com, davem@davemloft.net, edumazet@google.com, hkallweit1@gmail.com, jernej.skrabec@gmail.com, joabreu@synopsys.com, krzysztof.kozlowski+dt@linaro.org, kuba@kernel.org, lgirdwood@gmail.com, linux@armlinux.org.uk, pabeni@redhat.com, peppe.cavallaro@st.com, robh+dt@kernel.org, samuel@sholland.org, wens@csie.org Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Corentin Labbe Subject: [PATCH 1/6] phy: handle optional regulator for PHY Date: Mon, 9 May 2022 07:48:52 +0000 Message-Id: <20220509074857.195302-2-clabbe@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509074857.195302-1-clabbe@baylibre.com> References: <20220509074857.195302-1-clabbe@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add handling of optional regulators for PHY. Regulators need to be enabled before PHY scanning, so MDIO bus initiate this task. Signed-off-by: Corentin Labbe --- drivers/net/mdio/fwnode_mdio.c | 32 ++++++++++++++++++++++++++++++++ drivers/net/phy/phy_device.c | 20 ++++++++++++++++++++ include/linux/phy.h | 3 +++ 3 files changed, 55 insertions(+) diff --git a/drivers/net/mdio/fwnode_mdio.c b/drivers/net/mdio/fwnode_mdio.c index 1c1584fca632..c377cadc14c3 100644 --- a/drivers/net/mdio/fwnode_mdio.c +++ b/drivers/net/mdio/fwnode_mdio.c @@ -10,6 +10,7 @@ #include #include #include +#include =20 MODULE_AUTHOR("Calvin Johnson "); MODULE_LICENSE("GPL"); @@ -95,6 +96,8 @@ int fwnode_mdiobus_register_phy(struct mii_bus *bus, bool is_c45 =3D false; u32 phy_id; int rc; + struct regulator *regulator_phy; + struct regulator *regulator_phy_io; =20 mii_ts =3D fwnode_find_mii_timestamper(child); if (IS_ERR(mii_ts)) @@ -104,6 +107,32 @@ int fwnode_mdiobus_register_phy(struct mii_bus *bus, "ethernet-phy-ieee802.3-c45"); if (rc >=3D 0) is_c45 =3D true; + regulator_phy_io =3D devm_regulator_get_optional(&bus->dev, "phy-io"); + if (IS_ERR(regulator_phy_io)) { + rc =3D PTR_ERR(regulator_phy_io); + if (rc =3D=3D -ENODEV) + regulator_phy_io =3D NULL; + else + return rc; + } + regulator_phy =3D devm_regulator_get_optional(&bus->dev, "phy"); + if (IS_ERR(regulator_phy)) { + rc =3D PTR_ERR(regulator_phy); + if (rc =3D=3D -ENODEV) + regulator_phy =3D NULL; + else + return rc; + } + if (regulator_phy_io) { + rc =3D regulator_enable(regulator_phy_io); + if (rc) + return rc; + } + if (regulator_phy) { + rc =3D regulator_enable(regulator_phy); + if (rc) + return rc; + } =20 if (is_c45 || fwnode_get_phy_id(child, &phy_id)) phy =3D get_phy_device(bus, addr, is_c45); @@ -114,6 +143,9 @@ int fwnode_mdiobus_register_phy(struct mii_bus *bus, return PTR_ERR(phy); } =20 + phy->regulator_phy =3D regulator_phy; + phy->regulator_phy_io =3D regulator_phy_io; + if (is_acpi_node(child)) { phy->irq =3D bus->irq[addr]; =20 diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 431a8719c635..ce64df596580 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -1785,6 +1786,11 @@ int phy_suspend(struct phy_device *phydev) if (!ret) phydev->suspended =3D true; =20 + if (phydev->regulator_phy) + regulator_disable(phydev->regulator_phy); + if (phydev->regulator_phy_io) + regulator_disable(phydev->regulator_phy_io); + return ret; } EXPORT_SYMBOL(phy_suspend); @@ -1811,6 +1817,20 @@ int phy_resume(struct phy_device *phydev) { int ret; =20 + if (phydev->regulator_phy_io) { + ret =3D regulator_enable(phydev->regulator_phy_io); + if (ret) + return ret; + } + if (phydev->regulator_phy) { + ret =3D regulator_enable(phydev->regulator_phy); + if (ret) { + if (phydev->regulator_phy_io) + regulator_disable(phydev->regulator_phy_io); + return ret; + } + } + mutex_lock(&phydev->lock); ret =3D __phy_resume(phydev); mutex_unlock(&phydev->lock); diff --git a/include/linux/phy.h b/include/linux/phy.h index 2d12054932ba..c29f45668d94 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -704,6 +704,9 @@ struct phy_device { void (*phy_link_change)(struct phy_device *phydev, bool up); void (*adjust_link)(struct net_device *dev); =20 + struct regulator *regulator_phy; + struct regulator *regulator_phy_io; + #if IS_ENABLED(CONFIG_MACSEC) /* MACsec management functions */ const struct macsec_ops *macsec_ops; --=20 2.35.1 From nobody Sun Feb 8 05:00:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60EA4C433EF for ; Mon, 9 May 2022 07:52:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236313AbiEIHzo (ORCPT ); Mon, 9 May 2022 03:55:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236537AbiEIHxC (ORCPT ); Mon, 9 May 2022 03:53:02 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 155C813C095 for ; Mon, 9 May 2022 00:49:09 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id bg25so7860448wmb.4 for ; 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id bw22-20020a0560001f9600b0020c5253d8d8sm11784768wrb.36.2022.05.09.00.49.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 00:49:07 -0700 (PDT) From: Corentin Labbe To: alexandre.torgue@foss.st.com, andrew@lunn.ch, broonie@kernel.org, calvin.johnson@oss.nxp.com, davem@davemloft.net, edumazet@google.com, hkallweit1@gmail.com, jernej.skrabec@gmail.com, joabreu@synopsys.com, krzysztof.kozlowski+dt@linaro.org, kuba@kernel.org, lgirdwood@gmail.com, linux@armlinux.org.uk, pabeni@redhat.com, peppe.cavallaro@st.com, robh+dt@kernel.org, samuel@sholland.org, wens@csie.org Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Corentin Labbe Subject: [PATCH 2/6] net: stmmac: dwmac-sun8i: remove regulator Date: Mon, 9 May 2022 07:48:53 +0000 Message-Id: <20220509074857.195302-3-clabbe@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509074857.195302-1-clabbe@baylibre.com> References: <20220509074857.195302-1-clabbe@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now regulator is handled by phy core, there is no need to handle it in stmmac driver. Signed-off-by: Corentin Labbe --- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 37 +------------------ 1 file changed, 2 insertions(+), 35 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-sun8i.c index f834472599f7..17888813c707 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include =20 @@ -59,7 +58,6 @@ struct emac_variant { =20 /* struct sunxi_priv_data - hold all sunxi private data * @ephy_clk: reference to the optional EPHY clock for the internal PHY - * @regulator: reference to the optional regulator * @rst_ephy: reference to the optional EPHY reset for the internal PHY * @variant: reference to the current board variant * @regmap: regmap for using the syscon @@ -69,7 +67,6 @@ struct emac_variant { */ struct sunxi_priv_data { struct clk *ephy_clk; - struct regulator *regulator; struct reset_control *rst_ephy; const struct emac_variant *variant; struct regmap_field *regmap_field; @@ -568,29 +565,11 @@ static int sun8i_dwmac_init(struct platform_device *p= dev, void *priv) { struct net_device *ndev =3D platform_get_drvdata(pdev); struct sunxi_priv_data *gmac =3D priv; - int ret; =20 - if (gmac->regulator) { - ret =3D regulator_enable(gmac->regulator); - if (ret) { - dev_err(&pdev->dev, "Fail to enable regulator\n"); - return ret; - } - } - - if (gmac->use_internal_phy) { - ret =3D sun8i_dwmac_power_internal_phy(netdev_priv(ndev)); - if (ret) - goto err_disable_regulator; - } + if (gmac->use_internal_phy) + return sun8i_dwmac_power_internal_phy(netdev_priv(ndev)); =20 return 0; - -err_disable_regulator: - if (gmac->regulator) - regulator_disable(gmac->regulator); - - return ret; } =20 static void sun8i_dwmac_core_init(struct mac_device_info *hw, @@ -1034,9 +1013,6 @@ static void sun8i_dwmac_exit(struct platform_device *= pdev, void *priv) =20 if (gmac->variant->soc_has_internal_phy) sun8i_dwmac_unpower_internal_phy(gmac); - - if (gmac->regulator) - regulator_disable(gmac->regulator); } =20 static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable) @@ -1157,15 +1133,6 @@ static int sun8i_dwmac_probe(struct platform_device = *pdev) return -EINVAL; } =20 - /* Optional regulator for PHY */ - gmac->regulator =3D devm_regulator_get_optional(dev, "phy"); - if (IS_ERR(gmac->regulator)) { - if (PTR_ERR(gmac->regulator) =3D=3D -EPROBE_DEFER) - return -EPROBE_DEFER; - dev_info(dev, "No regulator found\n"); - gmac->regulator =3D NULL; - } - /* The "GMAC clock control" register might be located in the * CCU address range (on the R40), or the system control address * range (on most other sun8i and later SoCs). --=20 2.35.1 From nobody Sun Feb 8 05:00:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19B1BC4167B for ; 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id bw22-20020a0560001f9600b0020c5253d8d8sm11784768wrb.36.2022.05.09.00.49.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 00:49:08 -0700 (PDT) From: Corentin Labbe To: alexandre.torgue@foss.st.com, andrew@lunn.ch, broonie@kernel.org, calvin.johnson@oss.nxp.com, davem@davemloft.net, edumazet@google.com, hkallweit1@gmail.com, jernej.skrabec@gmail.com, joabreu@synopsys.com, krzysztof.kozlowski+dt@linaro.org, kuba@kernel.org, lgirdwood@gmail.com, linux@armlinux.org.uk, pabeni@redhat.com, peppe.cavallaro@st.com, robh+dt@kernel.org, samuel@sholland.org, wens@csie.org Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Corentin Labbe Subject: [PATCH 3/6] dt-bindings: net: Add documentation for phy-supply Date: Mon, 9 May 2022 07:48:54 +0000 Message-Id: <20220509074857.195302-4-clabbe@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509074857.195302-1-clabbe@baylibre.com> References: <20220509074857.195302-1-clabbe@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add entries for the 2 new phy-supply and phy-io-supply. Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/ethernet-phy.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Docu= mentation/devicetree/bindings/net/ethernet-phy.yaml index ed1415a4381f..2a6b45ddf010 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -153,6 +153,16 @@ properties: used. The absence of this property indicates the muxers should be configured so that the external PHY is used. =20 + phy-supply: + description: + Phandle to a regulator that provides power to the PHY. This + regulator will be managed during the PHY power on/off sequence. + + phy-io-supply: + description: + Phandle to a regulator that provides power to the PHY. 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id bw22-20020a0560001f9600b0020c5253d8d8sm11784768wrb.36.2022.05.09.00.49.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 00:49:09 -0700 (PDT) From: Corentin Labbe To: alexandre.torgue@foss.st.com, andrew@lunn.ch, broonie@kernel.org, calvin.johnson@oss.nxp.com, davem@davemloft.net, edumazet@google.com, hkallweit1@gmail.com, jernej.skrabec@gmail.com, joabreu@synopsys.com, krzysztof.kozlowski+dt@linaro.org, kuba@kernel.org, lgirdwood@gmail.com, linux@armlinux.org.uk, pabeni@redhat.com, peppe.cavallaro@st.com, robh+dt@kernel.org, samuel@sholland.org, wens@csie.org Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Corentin Labbe Subject: [PATCH 4/6] ARM: dts: sunxi: move phy regulator in PHY node Date: Mon, 9 May 2022 07:48:55 +0000 Message-Id: <20220509074857.195302-5-clabbe@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509074857.195302-1-clabbe@baylibre.com> References: <20220509074857.195302-1-clabbe@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that PHY core can handle regulators, move regulator handle in PHY node. Signed-off-by: Corentin Labbe --- arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 2 +- arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 2 +- arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 2 +- arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts | 2 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 2 +- arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 2 +- arch/arm/boot/dts/sun8i-h3-zeropi.dts | 2 +- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 2 +- arch/arm/boot/dts/sun8i-r40-oka40i-c.dts | 2 +- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 2 +- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 2 +- arch/arm/boot/dts/sun9i-a80-optimus.dts | 2 +- arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 2 +- 13 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/d= ts/sun8i-a83t-bananapi-m3.dts index 5a7e1bd5f825..b450be0a45ed 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -129,7 +129,6 @@ &ehci0 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_sw>; phy-handle =3D <&rgmii_phy>; phy-mode =3D "rgmii-id"; allwinner,rx-delay-ps =3D <700>; @@ -151,6 +150,7 @@ &mdio { rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_sw>; }; }; =20 diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/bo= ot/dts/sun8i-a83t-cubietruck-plus.dts index 870993393fc2..fe70b350cdbb 100644 --- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts +++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts @@ -181,7 +181,6 @@ &ehci1 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_dldo4>; phy-handle =3D <&rgmii_phy>; phy-mode =3D "rgmii-id"; status =3D "okay"; @@ -201,6 +200,7 @@ &mdio { rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_dldo4>; }; }; =20 diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/= dts/sun8i-h3-nanopi-m1-plus.dts index a2f2ef2b0092..c393612f44c6 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts @@ -103,7 +103,6 @@ &ehci2 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii"; =20 @@ -114,6 +113,7 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <7>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/boot/dts/s= un8i-h3-nanopi-r1.dts index 26e2e6172e0d..70bde396856b 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts @@ -80,7 +80,6 @@ &ehci2 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii-id"; status =3D "okay"; @@ -90,6 +89,7 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@7 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <7>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/d= ts/sun8i-h3-orangepi-plus.dts index d05fa679dcd3..c6dcf1af3298 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -83,7 +83,6 @@ &ehci3 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii-id"; =20 @@ -94,6 +93,7 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <0>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot= /dts/sun8i-h3-orangepi-plus2e.dts index b6ca45d18e51..61eb8c003186 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts @@ -65,7 +65,6 @@ reg_gmac_3v3: gmac-3v3 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii-id"; status =3D "okay"; @@ -75,5 +74,6 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_gmac_3v3>; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-zeropi.dts b/arch/arm/boot/dts/sun8= i-h3-zeropi.dts index 7d3e7323b661..54174ef18823 100644 --- a/arch/arm/boot/dts/sun8i-h3-zeropi.dts +++ b/arch/arm/boot/dts/sun8i-h3-zeropi.dts @@ -65,13 +65,13 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@7 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <7>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii-id"; =20 diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/b= oot/dts/sun8i-r40-bananapi-m2-ultra.dts index a6a1087a0c9b..b1f269bbd479 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -130,7 +130,6 @@ &gmac { pinctrl-0 =3D <&gmac_rgmii_pins>; phy-handle =3D <&phy1>; phy-mode =3D "rgmii-id"; - phy-supply =3D <®_dc1sw>; status =3D "okay"; }; =20 @@ -138,6 +137,7 @@ &gmac_mdio { phy1: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_dc1sw>; }; }; =20 diff --git a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts b/arch/arm/boot/dts/s= un8i-r40-oka40i-c.dts index 0bd1336206b8..c43476b426df 100644 --- a/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts +++ b/arch/arm/boot/dts/sun8i-r40-oka40i-c.dts @@ -93,7 +93,6 @@ &gmac { pinctrl-0 =3D <&gmac_rgmii_pins>; phy-handle =3D <&phy1>; phy-mode =3D "rgmii-id"; - phy-supply =3D <®_dcdc1>; status =3D "okay"; }; =20 @@ -101,6 +100,7 @@ &gmac_mdio { phy1: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_dcdc1>; }; }; =20 diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/b= oot/dts/sun8i-v40-bananapi-m2-berry.dts index 47954551f573..050a649d7bda 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -121,7 +121,6 @@ &gmac { pinctrl-0 =3D <&gmac_rgmii_pins>; phy-handle =3D <&phy1>; phy-mode =3D "rgmii-id"; - phy-supply =3D <®_dc1sw>; status =3D "okay"; }; =20 @@ -129,6 +128,7 @@ &gmac_mdio { phy1: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_dc1sw>; }; }; =20 diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dt= s/sun9i-a80-cubieboard4.dts index c8ca8cb7f5c9..ab9bf4bf7343 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -130,7 +130,6 @@ &gmac { pinctrl-0 =3D <&gmac_rgmii_pins>; phy-handle =3D <&phy1>; phy-mode =3D "rgmii-id"; - phy-supply =3D <®_cldo1>; status =3D "okay"; }; =20 @@ -142,6 +141,7 @@ &i2c3 { =20 &mdio { phy1: ethernet-phy@1 { + phy-supply =3D <®_cldo1>; reg =3D <1>; }; }; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/su= n9i-a80-optimus.dts index 5c3580d712e4..48219b8049b1 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -125,13 +125,13 @@ &gmac { pinctrl-0 =3D <&gmac_rgmii_pins>; phy-handle =3D <&phy1>; phy-mode =3D "rgmii-id"; - phy-supply =3D <®_cldo1>; status =3D "okay"; }; =20 &mdio { phy1: ethernet-phy@1 { reg =3D <1>; + phy-supply =3D <®_cldo1>; }; }; =20 diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/= dts/sunxi-bananapi-m2-plus.dtsi index d03f5853ef7b..65f0a3c2af3f 100644 --- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi +++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi @@ -125,7 +125,6 @@ &ehci2 { &emac { pinctrl-names =3D "default"; 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id bw22-20020a0560001f9600b0020c5253d8d8sm11784768wrb.36.2022.05.09.00.49.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 00:49:10 -0700 (PDT) From: Corentin Labbe To: alexandre.torgue@foss.st.com, andrew@lunn.ch, broonie@kernel.org, calvin.johnson@oss.nxp.com, davem@davemloft.net, edumazet@google.com, hkallweit1@gmail.com, jernej.skrabec@gmail.com, joabreu@synopsys.com, krzysztof.kozlowski+dt@linaro.org, kuba@kernel.org, lgirdwood@gmail.com, linux@armlinux.org.uk, pabeni@redhat.com, peppe.cavallaro@st.com, robh+dt@kernel.org, samuel@sholland.org, wens@csie.org Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Corentin Labbe Subject: [PATCH 5/6] arm64: dts: allwinner: move phy regulator in PHY node Date: Mon, 9 May 2022 07:48:56 +0000 Message-Id: <20220509074857.195302-6-clabbe@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509074857.195302-1-clabbe@baylibre.com> References: <20220509074857.195302-1-clabbe@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that PHY core can handle regulators, move regulator handle in PHY node. Signed-off-by: Corentin Labbe --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 2 +- .../boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 2 +- .../boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 2 +- .../boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts | 2 +- .../boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 2 +- .../arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 2 +- .../boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 2 +- arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 2 +- .../boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts | 8 ++++---- arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 2 +- 17 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/ar= ch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts index 997a19372683..f44345e0f749 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts @@ -107,7 +107,6 @@ &emac { pinctrl-0 =3D <&rgmii_pins>; phy-mode =3D "rgmii-id"; phy-handle =3D <&ext_rgmii_phy>; - phy-supply =3D <®_dc1sw>; status =3D "okay"; }; =20 @@ -134,6 +133,7 @@ &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_dc1sw>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch= /arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts index e47ff06a6fa9..9923d8fb3289 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts @@ -82,7 +82,6 @@ &emac { pinctrl-0 =3D <&rgmii_pins>; phy-mode =3D "rgmii"; phy-handle =3D <&ext_rgmii_phy>; - phy-supply =3D <®_dcdc1>; status =3D "okay"; }; =20 @@ -106,6 +105,7 @@ &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <7>; + phy-supply =3D <®_dcdc1>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.d= ts b/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts index 577f9e1d08a1..ec511efee942 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-oceanic-5205-5inmfd.dts @@ -30,7 +30,6 @@ &emac { pinctrl-0 =3D <&rgmii_pins>; phy-mode =3D "rgmii"; phy-handle =3D <&ext_rgmii_phy>; - phy-supply =3D <®_dc1sw>; allwinner,tx-delay-ps =3D <600>; status =3D "okay"; }; @@ -55,6 +54,7 @@ &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_dc1sw>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/= arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts index bfb806cf6d7a..c172cc4291b7 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -104,7 +104,6 @@ &emac { pinctrl-0 =3D <&rgmii_pins>; phy-mode =3D "rgmii"; phy-handle =3D <&ext_rgmii_phy>; - phy-supply =3D <®_dcdc1>; allwinner,tx-delay-ps =3D <600>; status =3D "okay"; }; @@ -124,6 +123,7 @@ &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_dcdc1>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/ar= ch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts index c519d9fa6967..3f9622f141b6 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts @@ -122,7 +122,6 @@ &emac { pinctrl-0 =3D <&rgmii_pins>; phy-mode =3D "rgmii-id"; phy-handle =3D <&ext_rgmii_phy>; - phy-supply =3D <®_gmac_3v3>; status =3D "okay"; }; =20 @@ -141,6 +140,7 @@ &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm= 64/boot/dts/allwinner/sun50i-a64-pine64.dts index 2accb5ddf783..70039380d454 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts @@ -83,7 +83,6 @@ &emac { pinctrl-0 =3D <&rmii_pins>; phy-mode =3D "rmii"; phy-handle =3D <&ext_rmii_phy1>; - phy-supply =3D <®_dc1sw>; status =3D "okay"; =20 }; @@ -111,6 +110,7 @@ &mdio { ext_rmii_phy1: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_dc1sw>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts = b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts index 5e66ce1a334f..716a8c1faef2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts @@ -81,7 +81,6 @@ &emac { pinctrl-0 =3D <&rgmii_pins>; phy-mode =3D "rgmii-txid"; phy-handle =3D <&ext_rgmii_phy>; - phy-supply =3D <®_dc1sw>; status =3D "okay"; }; =20 @@ -100,6 +99,7 @@ &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_dc1sw>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dt= s b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts index 6e30a564c87f..4e3dae6ee3a4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-libretech-all-h5-cc.dts @@ -34,7 +34,6 @@ &codec { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii-id"; /delete-property/ allwinner,leds-active-low; @@ -45,6 +44,7 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b= /arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts index 4c3921ac236c..e07142b0cddf 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts @@ -94,7 +94,6 @@ &ehci3 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii-id"; status =3D "okay"; @@ -104,6 +103,7 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@7 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <7>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch= /arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts index 05486cccee1c..77940e90bd36 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts @@ -73,7 +73,6 @@ &ehci3 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii-id"; status =3D "okay"; @@ -83,6 +82,7 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@7 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <7>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/ar= ch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts index 55b369534a08..7280bcbc0f40 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts @@ -125,7 +125,6 @@ &ehci2 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii-id"; status =3D "okay"; @@ -135,6 +134,7 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@7 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <7>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arc= h/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index 1010c1b22d2e..95bc670a4b8e 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -121,7 +121,6 @@ &ehci3 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii-id"; status =3D "okay"; @@ -131,6 +130,7 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/a= rch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts index 74e0444af19b..8b4403ca610f 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts @@ -122,7 +122,6 @@ &ehci3 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii-id"; status =3D "okay"; @@ -132,6 +131,7 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts= b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts index 7ec5ac850a0d..74d2a60ce113 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts @@ -67,7 +67,6 @@ &ehci1 { &emac { pinctrl-names =3D "default"; pinctrl-0 =3D <&emac_rgmii_pins>; - phy-supply =3D <®_gmac_3v3>; phy-handle =3D <&ext_rgmii_phy>; phy-mode =3D "rgmii-id"; status =3D "okay"; @@ -77,6 +76,7 @@ &external_mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch= /arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index 6249e9e02928..ecfb99c07f69 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -99,7 +99,6 @@ &emac { pinctrl-0 =3D <&ext_rgmii_pins>; phy-mode =3D "rgmii-id"; phy-handle =3D <&ext_rgmii_phy>; - phy-supply =3D <®_aldo2>; status =3D "okay"; }; =20 @@ -122,6 +121,7 @@ &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_aldo2>; }; }; =20 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts b= /arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts index 686f58e77004..6594d2e5284a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts @@ -18,12 +18,12 @@ wifi_pwrseq: wifi_pwrseq { }; }; =20 -&hdmi_connector { - /delete-property/ ddc-en-gpios; +&ext_rgmii_phy { + phy-supply =3D <®_aldo2>; }; =20 -&emac { - phy-supply =3D <®_aldo2>; +&hdmi_connector { + /delete-property/ ddc-en-gpios; }; =20 &mmc1 { diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/ar= m64/boot/dts/allwinner/sun50i-h6-pine-h64.dts index 1ffd68f43f87..dae637720432 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts @@ -102,7 +102,6 @@ &emac { pinctrl-0 =3D <&ext_rgmii_pins>; phy-mode =3D "rgmii-id"; phy-handle =3D <&ext_rgmii_phy>; - phy-supply =3D <®_gmac_3v3>; allwinner,rx-delay-ps =3D <200>; allwinner,tx-delay-ps =3D <200>; status =3D "okay"; @@ -127,6 +126,7 @@ &mdio { ext_rgmii_phy: ethernet-phy@1 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <1>; + phy-supply =3D <®_gmac_3v3>; }; }; =20 --=20 2.35.1 From nobody Sun Feb 8 05:00:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B14E8C43217 for ; Mon, 9 May 2022 07:52:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236482AbiEIH4H (ORCPT ); Mon, 9 May 2022 03:56:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236573AbiEIHxH (ORCPT ); Mon, 9 May 2022 03:53:07 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 025CB14C76F for ; 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id bw22-20020a0560001f9600b0020c5253d8d8sm11784768wrb.36.2022.05.09.00.49.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 00:49:12 -0700 (PDT) From: Corentin Labbe To: alexandre.torgue@foss.st.com, andrew@lunn.ch, broonie@kernel.org, calvin.johnson@oss.nxp.com, davem@davemloft.net, edumazet@google.com, hkallweit1@gmail.com, jernej.skrabec@gmail.com, joabreu@synopsys.com, krzysztof.kozlowski+dt@linaro.org, kuba@kernel.org, lgirdwood@gmail.com, linux@armlinux.org.uk, pabeni@redhat.com, peppe.cavallaro@st.com, robh+dt@kernel.org, samuel@sholland.org, wens@csie.org Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, =?UTF-8?q?Ond=C5=99ej=20Jirman?= , Corentin Labbe Subject: [PATCH 6/6] arm64: dts: allwinner: orange-pi-3: Enable ethernet Date: Mon, 9 May 2022 07:48:57 +0000 Message-Id: <20220509074857.195302-7-clabbe@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509074857.195302-1-clabbe@baylibre.com> References: <20220509074857.195302-1-clabbe@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ond=C5=99ej Jirman Orange Pi 3 has two regulators that power the Realtek RTL8211E PHY. According to the datasheet, both regulators need to be enabled at the same time, or that "phy-io" should be enabled slightly earlier than "phy" regulator. RTL8211E/RTL8211EG datasheet says: Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power later than 3.3V power may lead to errors. The timing is set in DT via startup-delay-us. Signed-off-by: Ondrej Jirman Signed-off-by: Corentin Labbe --- .../dts/allwinner/sun50i-h6-orangepi-3.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/= arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index c45d7b7fb39a..fd1d4f5bbc83 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -13,6 +13,7 @@ / { compatible =3D "xunlong,orangepi-3", "allwinner,sun50i-h6"; =20 aliases { + ethernet0 =3D &emac; serial0 =3D &uart0; serial1 =3D &uart1; }; @@ -55,6 +56,15 @@ led-1 { }; }; =20 + reg_gmac_2v5: gmac-2v5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "gmac-2v5"; + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; + enable-active-high; + gpio =3D <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + }; + reg_vcc5v: vcc5v { /* board wide 5V supply directly from the DC jack */ compatible =3D "regulator-fixed"; @@ -113,6 +123,33 @@ &ehci3 { status =3D "okay"; }; =20 +&emac { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ext_rgmii_pins>; + phy-mode =3D "rgmii-id"; + phy-handle =3D <&ext_rgmii_phy>; + status =3D "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + /* + * The board uses 2.5V RGMII signalling. Power sequence to enable + * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails + * at the same time and to wait 100ms. The driver enables phy-io + * first. Delay is achieved with enable-ramp-delay on reg_aldo2. + */ + phy-io-supply =3D <®_gmac_2v5>; + phy-supply =3D <®_aldo2>; + + reset-gpios =3D <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ + reset-assert-us =3D <15000>; + reset-deassert-us =3D <40000>; + }; +}; + &gpu { mali-supply =3D <®_dcdcc>; status =3D "okay"; @@ -211,6 +248,7 @@ reg_aldo2: aldo2 { regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-name =3D "vcc33-audio-tv-ephy-mac"; + regulator-enable-ramp-delay =3D <100000>; }; =20 /* ALDO3 is shorted to CLDO1 */ --=20 2.35.1