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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT047.mail.protection.outlook.com (10.13.174.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5227.15 via Frontend Transport; Mon, 9 May 2022 07:49:00 +0000 Received: from sp5-759chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 9 May 2022 02:48:29 -0500 From: Suravee Suthikulpanit To: , CC: , , , "Suravee Suthikulpanit" Subject: [PATCH v2] iommu/amd: Set translation valid bit only when IO page tables are in used Date: Mon, 9 May 2022 02:48:15 -0500 Message-ID: <20220509074815.11881-1-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fb7fc74f-7fd1-4968-ce76-08da31906184 X-MS-TrafficTypeDiagnostic: BN7PR12MB2787:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2022 07:49:00.5460 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb7fc74f-7fd1-4968-ce76-08da31906184 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT047.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2787 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" On AMD system with SNP enabled, IOMMU hardware checks the host translation valid (TV) and guest translation valid (GV) bits in the device table entry (DTE) before accessing the corresponded page tables. However, current IOMMU driver sets the TV bit for all devices regardless of whether the host page table is in used. This results in ILLEGAL_DEV_TABLE_ENTRY event for devices, which do not the host page table root pointer set up. Thefore, only set TV bit when DMA remapping is not used, which is when domain ID in the AMD IOMMU device table entry (DTE) is zero. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/init.c | 4 +--- drivers/iommu/amd/iommu.c | 8 ++++++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 648d6b94ba8c..6a2dadf2b2dc 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -2336,10 +2336,8 @@ static void init_device_table_dma(void) { u32 devid; =20 - for (devid =3D 0; devid <=3D amd_iommu_last_bdf; ++devid) { + for (devid =3D 0; devid <=3D amd_iommu_last_bdf; ++devid) set_dev_entry_bit(devid, DEV_ENTRY_VALID); - set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); - } } =20 static void __init uninit_device_table_dma(void) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index a1ada7bff44e..cea254968f06 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1473,7 +1473,7 @@ static void set_dte_entry(u16 devid, struct protectio= n_domain *domain, =20 pte_root |=3D (domain->iop.mode & DEV_ENTRY_MODE_MASK) << DEV_ENTRY_MODE_SHIFT; - pte_root |=3D DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV; + pte_root |=3D DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V; =20 flags =3D amd_iommu_dev_table[devid].data[1]; =20 @@ -1513,6 +1513,10 @@ static void set_dte_entry(u16 devid, struct protecti= on_domain *domain, flags |=3D tmp; } =20 + /* Only set TV bit when IOMMU page translation is in used */ + if (domain->id !=3D 0) + pte_root |=3D DTE_FLAG_TV; + flags &=3D ~DEV_DOMID_MASK; flags |=3D domain->id; =20 @@ -1535,7 +1539,7 @@ static void set_dte_entry(u16 devid, struct protectio= n_domain *domain, static void clear_dte_entry(u16 devid) { /* remove entry from the device table seen by the hardware */ - amd_iommu_dev_table[devid].data[0] =3D DTE_FLAG_V | DTE_FLAG_TV; + amd_iommu_dev_table[devid].data[0] =3D DTE_FLAG_V; amd_iommu_dev_table[devid].data[1] &=3D DTE_FLAG_MASK; =20 amd_iommu_apply_erratum_63(devid); --=20 2.25.1