From nobody Sun Sep 22 04:38:19 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41051C433EF for ; Sat, 7 May 2022 06:06:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1445616AbiEGGKg (ORCPT ); Sat, 7 May 2022 02:10:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383375AbiEGGKb (ORCPT ); Sat, 7 May 2022 02:10:31 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61EFE2D1DD; Fri, 6 May 2022 23:06:39 -0700 (PDT) X-UUID: 56cdd10e60b54743b065c207a496c13c-20220507 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:61f4a0ed-69b8-40c7-abce-095517d2e7cd,OB:0,LO B:0,IP:0,URL:25,TC:0,Content:-20,EDM:0,RT:0,SF:100,FILE:0,RULE:Release_Ham ,ACTION:release,TS:105 X-CID-INFO: VERSION:1.1.4,REQID:61f4a0ed-69b8-40c7-abce-095517d2e7cd,OB:0,LOB: 0,IP:0,URL:25,TC:0,Content:-20,EDM:0,RT:0,SF:100,FILE:0,RULE:Spam_GS981B3D ,ACTION:quarantine,TS:105 X-CID-META: VersionHash:faefae9,CLOUDID:fbbce8b2-56b5-4c9e-8d83-0070b288eb6a,C OID:d447d653637e,Recheck:0,SF:28|16|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: 56cdd10e60b54743b065c207a496c13c-20220507 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1040593329; Sat, 07 May 2022 14:06:33 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Sat, 7 May 2022 14:06:33 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 7 May 2022 14:06:32 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Sat, 7 May 2022 14:06:31 +0800 From: Jianjun Wang To: Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Matthias Brugger , Chen-Yu Tsai , AngeloGioacchino Del Regno , Krzysztof Kozlowski CC: Wei-Shun Chang , Jianjun Wang , , , , , , , , , , , Subject: [PATCH v8 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY Date: Sat, 7 May 2022 14:06:20 +0800 Message-ID: <20220507060621.32252-2-jianjun.wang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220507060621.32252-1-jianjun.wang@mediatek.com> References: <20220507060621.32252-1-jianjun.wang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add YAML schema documentation for PCIe PHY on MediaTek chipsets. Signed-off-by: Jianjun Wang Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/phy/mediatek,pcie-phy.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy= .yaml diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b= /Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml new file mode 100644 index 000000000000..422750cc4121 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek PCIe PHY + +maintainers: + - Jianjun Wang + +description: | + The PCIe PHY supports physical layer functionality for PCIe Gen3 port. + +properties: + compatible: + const: mediatek,mt8195-pcie-phy + + reg: + maxItems: 1 + + reg-names: + items: + - const: sif + + "#phy-cells": + const: 0 + + nvmem-cells: + maxItems: 7 + description: + Phandles to nvmem cell that contains the efuse data, if unspecified, + default value is used. + + nvmem-cell-names: + items: + - const: glb_intr + - const: tx_ln0_pmos + - const: tx_ln0_nmos + - const: rx_ln0 + - const: tx_ln1_pmos + - const: tx_ln1_nmos + - const: rx_ln1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@11e80000 { + compatible =3D "mediatek,mt8195-pcie-phy"; + #phy-cells =3D <0>; + reg =3D <0x11e80000 0x10000>; + reg-names =3D "sif"; + nvmem-cells =3D <&pciephy_glb_intr>, + <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, + <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, + <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names =3D "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains =3D <&spm 2>; + }; --=20 2.18.0