From nobody Mon Jun 15 02:46:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05885C433EF for ; Fri, 6 May 2022 13:23:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1392465AbiEFN1T (ORCPT ); Fri, 6 May 2022 09:27:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1392445AbiEFN1A (ORCPT ); Fri, 6 May 2022 09:27:00 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C33D469729; Fri, 6 May 2022 06:23:17 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id i20-20020a05600c355400b0039456976dcaso3810934wmq.1; Fri, 06 May 2022 06:23:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Haj+pN6JlXocxjPEnNzE2m0NqLyZQmn83EhQMLGbRWo=; b=WRUROltatrMECKYrCYeUq5TSl75j4AsvjghB2KUd/R8VL1hjYAdffn7Ny7kLmgyyiA eJD2ZjrxqwmPYb8MboyTS4UBISnXi3KESXKT6unurnNMtprA2T50Bw7zdGdoeO5VNEJL o5H7lNZmW+CZx+SRnHj1Istn0+hFZPhCwB3Gx1b1zoDpw7IjdCb2d+OEcYptnUJC3meZ EjnmW6H1s4O53tzAL7UReUnM0BbeRsLT5cDZiafc2mYVtyZLFjfDSIx6TavUeT3eEOfD zpGLOe01nwTcL6RcPUUXaPQq09qb7IHg1Qssehs7p/xmRrKsqC3GRPY8q38s9K46unST dvxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Haj+pN6JlXocxjPEnNzE2m0NqLyZQmn83EhQMLGbRWo=; b=d4tZyu5EQWl6WPnJ5xetBPccCRXerE4jSANjJSmK1r++LtYpBLmC7foW4zo3cw1sMI DGOr7xo7DMblRoTGIbh+wCjFgVLl71OU+8H+fjdQDuBkXa83aTy3yI35fphQqVFg5X5x X8JGQTrBtHUaTyWUOme5ojkHTrkopEsMBti2Ru1bH/VwEXd16LENq/CP2KoqJLJaps6l G9N2m26BFdSUqR3ANnzH+CNhdk+CRaB7+pEGNN5GGLcJ8X7nQlv9Xj53mc5bpCsP+1lS 4dlTfkzFRqf8JqP8ffMD61Z+U70+0sgUIldQNPeMzYFHDkhRyPkClOUWB8OvvnfT1QYg IYjw== X-Gm-Message-State: AOAM532lhRLKy8MaV3Wg42CRGh39b+MRGrjd3C9Knwp2kgudQUYylxcr jjmtWGo/C18gnTB9OwQJuIawFPu9X+o= X-Google-Smtp-Source: ABdhPJxi3busQ743jN6os0VE9WDErOUuMMXg7V8gGNQgL5xizSsYLFVGYafPCd+F1yzwLZ0mj2M4Vw== X-Received: by 2002:a05:600c:4187:b0:394:4cf8:7c61 with SMTP id p7-20020a05600c418700b003944cf87c61mr3339880wmh.119.1651843396215; Fri, 06 May 2022 06:23:16 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id p33-20020a05600c1da100b0038ec8b633fesm4108848wms.1.2022.05.06.06.23.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 06:23:15 -0700 (PDT) From: Thierry Reding To: Krzysztof Kozlowski Cc: Thierry Reding , Jon Hunter , Ashish Mhetre , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] memory: tegra: Add Tegra234 support Date: Fri, 6 May 2022 15:23:09 +0200 Message-Id: <20220506132312.3910637-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220506132312.3910637-1-thierry.reding@gmail.com> References: <20220506132312.3910637-1-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Thierry Reding The memory controller and external memory controller found on Tegra234 is similar to the version found on earlier SoCs but supports a number of new memory clients. Add initial memory client definitions for the Tegra234 so that the SMMU stream ID override registers can be properly programmed at boot time. Signed-off-by: Thierry Reding --- drivers/memory/tegra/Makefile | 2 + drivers/memory/tegra/mc.c | 3 ++ drivers/memory/tegra/mc.h | 7 ++- drivers/memory/tegra/tegra186-emc.c | 3 ++ drivers/memory/tegra/tegra234.c | 81 +++++++++++++++++++++++++++++ 5 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 drivers/memory/tegra/tegra234.c diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile index c992e87782d2..0750847dac3c 100644 --- a/drivers/memory/tegra/Makefile +++ b/drivers/memory/tegra/Makefile @@ -9,6 +9,7 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) +=3D tegra124.o tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) +=3D tegra210.o tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) +=3D tegra186.o tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) +=3D tegra186.o tegra194.o +tegra-mc-$(CONFIG_ARCH_TEGRA_234_SOC) +=3D tegra186.o tegra234.o =20 obj-$(CONFIG_TEGRA_MC) +=3D tegra-mc.o =20 @@ -19,5 +20,6 @@ obj-$(CONFIG_TEGRA210_EMC_TABLE) +=3D tegra210-emc-table.o obj-$(CONFIG_TEGRA210_EMC) +=3D tegra210-emc.o obj-$(CONFIG_ARCH_TEGRA_186_SOC) +=3D tegra186-emc.o obj-$(CONFIG_ARCH_TEGRA_194_SOC) +=3D tegra186-emc.o +obj-$(CONFIG_ARCH_TEGRA_234_SOC) +=3D tegra186-emc.o =20 tegra210-emc-y :=3D tegra210-emc-core.o tegra210-emc-cc-r21021.o diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 44b4a4080920..bf3abb6d8354 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -44,6 +44,9 @@ static const struct of_device_id tegra_mc_of_match[] =3D { #endif #ifdef CONFIG_ARCH_TEGRA_194_SOC { .compatible =3D "nvidia,tegra194-mc", .data =3D &tegra194_mc_soc }, +#endif +#ifdef CONFIG_ARCH_TEGRA_234_SOC + { .compatible =3D "nvidia,tegra234-mc", .data =3D &tegra234_mc_soc }, #endif { /* sentinel */ } }; diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 1e492989c363..062886e94c04 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -137,6 +137,10 @@ extern const struct tegra_mc_soc tegra186_mc_soc; extern const struct tegra_mc_soc tegra194_mc_soc; #endif =20 +#ifdef CONFIG_ARCH_TEGRA_234_SOC +extern const struct tegra_mc_soc tegra234_mc_soc; +#endif + #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ defined(CONFIG_ARCH_TEGRA_114_SOC) || \ defined(CONFIG_ARCH_TEGRA_124_SOC) || \ @@ -147,7 +151,8 @@ extern const struct tegra_mc_ops tegra30_mc_ops; #endif =20 #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \ - defined(CONFIG_ARCH_TEGRA_194_SOC) + defined(CONFIG_ARCH_TEGRA_194_SOC) || \ + defined(CONFIG_ARCH_TEGRA_234_SOC) extern const struct tegra_mc_ops tegra186_mc_ops; #endif =20 diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/teg= ra186-emc.c index 746c4ef2c0af..54b47ca33483 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -272,6 +272,9 @@ static const struct of_device_id tegra186_emc_of_match[= ] =3D { #endif #if defined(CONFIG_ARCH_TEGRA_194_SOC) { .compatible =3D "nvidia,tegra194-emc" }, +#endif +#if defined(CONFIG_ARCH_TEGRA_234_SOC) + { .compatible =3D "nvidia,tegra234-emc" }, #endif { /* sentinel */ } }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c new file mode 100644 index 000000000000..45efc5139960 --- /dev/null +++ b/drivers/memory/tegra/tegra234.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 NVIDIA CORPORATION. All rights reserved. + */ + +#include + +#include + +#include "mc.h" + +static const struct tegra_mc_client tegra234_mc_clients[] =3D { + { + .id =3D TEGRA234_MEMORY_CLIENT_SDMMCRAB, + .name =3D "sdmmcrab", + .sid =3D TEGRA234_SID_SDMMC4, + .regs =3D { + .sid =3D { + .override =3D 0x318, + .security =3D 0x31c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_SDMMCWAB, + .name =3D "sdmmcwab", + .sid =3D TEGRA234_SID_SDMMC4, + .regs =3D { + .sid =3D { + .override =3D 0x338, + .security =3D 0x33c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPR, + .name =3D "bpmpr", + .sid =3D TEGRA234_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x498, + .security =3D 0x49c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPW, + .name =3D "bpmpw", + .sid =3D TEGRA234_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x4a0, + .security =3D 0x4a4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPDMAR, + .name =3D "bpmpdmar", + .sid =3D TEGRA234_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x4a8, + .security =3D 0x4ac, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPDMAW, + .name =3D "bpmpdmaw", + .sid =3D TEGRA234_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x4b0, + .security =3D 0x4b4, + }, + }, + }, +}; + +const struct tegra_mc_soc tegra234_mc_soc =3D { + .num_clients =3D ARRAY_SIZE(tegra234_mc_clients), + .clients =3D tegra234_mc_clients, + .num_address_bits =3D 40, + .ops =3D &tegra186_mc_ops, +}; --=20 2.35.1 From nobody Mon Jun 15 02:46:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D915CC433F5 for ; Fri, 6 May 2022 13:23:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1392449AbiEFN1O (ORCPT ); Fri, 6 May 2022 09:27:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1392443AbiEFN1C (ORCPT ); Fri, 6 May 2022 09:27:02 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A6FB6973F; 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Fri, 06 May 2022 06:23:17 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id o9-20020a5d4089000000b0020c5253d8d2sm3669451wrp.30.2022.05.06.06.23.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 06:23:17 -0700 (PDT) From: Thierry Reding To: Krzysztof Kozlowski Cc: Thierry Reding , Jon Hunter , Ashish Mhetre , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH 2/4] memory: tegra: Add APE memory clients for Tegra234 Date: Fri, 6 May 2022 15:23:10 +0200 Message-Id: <20220506132312.3910637-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220506132312.3910637-1-thierry.reding@gmail.com> References: <20220506132312.3910637-1-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sameer Pujar Add the memory clients on Tegra234 which are needed for APE DMA to properly use the SMMU. Signed-off-by: Sameer Pujar Acked-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra234.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index 45efc5139960..e22824a79f45 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2021 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2021-2022, NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -70,6 +70,26 @@ static const struct tegra_mc_client tegra234_mc_clients[= ] =3D { .security =3D 0x4b4, }, }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_APEDMAR, + .name =3D "apedmar", + .sid =3D TEGRA234_SID_APE, + .regs =3D { + .sid =3D { + .override =3D 0x4f8, + .security =3D 0x4fc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_APEDMAW, + .name =3D "apedmaw", + .sid =3D TEGRA234_SID_APE, + .regs =3D { + .sid =3D { + .override =3D 0x500, + .security =3D 0x504, + }, + }, }, }; =20 --=20 2.35.1 From nobody Mon Jun 15 02:46:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FBE2C433EF for ; Fri, 6 May 2022 13:23:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1392464AbiEFN1R (ORCPT ); Fri, 6 May 2022 09:27:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50576 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1392455AbiEFN1E (ORCPT ); Fri, 6 May 2022 09:27:04 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 103836830B; Fri, 6 May 2022 06:23:21 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id bg25so4428914wmb.4; Fri, 06 May 2022 06:23:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=siDa636j/ccVMOI4OmPBh0Ww1kY8nIuskxtAz5IKxAA=; b=e0AWiWVeItrFT6XCJTwvZpyhP8yRXdoz7bIOMBWUYloX/RqMwWTkLXuHYiS6ArJUX0 lazPv9QAiH54DoXqYdGqkYztJIfgLhvpnxyAq/Wpwu5krD2Xi3YTloHT8EzQ9lRuM16C 4I0V3c2OdDu+ZbtaPxP779pDDe1USOkjeiLMhjxH1E04JjS3gGAnFXrx2d6P4LufpD// DCqI21TLEcjZ3mz4h6lHvcJAvtGFw2fBJwCkKts0f9v+zSt4SEoqPvdWGlQJ+X/muNJR bwBy7D/IBp6y8KngfR2BJQ63uNAePOdR0Qhsw0gF17+Uy6nOpYiXn/p04X6StZ4dQgpv KV5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=siDa636j/ccVMOI4OmPBh0Ww1kY8nIuskxtAz5IKxAA=; b=gqIOjV94pJ36kYuAqGvEQ9zhGIBaswq268hS3nbhIGJlRbX4yXDq7HgICtQySHtxit SEgswXjcnzW57BmgH80+ySe3tWoZiKsI/lcyqvTTjHLWMkcoQgVdQj38R+r/SIvfI1Wj mR3DwckIHgA9gtW47CJHaLFQd6RwTgpeYh14d9lcIZF8Vah7nAaOuz/ZJnvIIMsAKW6m NegMgzXED0jdxdFbVxLTBg5xJkD6opPIm3FexD06XYoW95EdKeT5w1qDjjxJjjWdqVw8 DbebaX8vsHEBc+bP/QRLNSav39jEXORIOidDJkg4BTUk66WXpm9Us7/aWmHIT6OiL+zE HOZw== X-Gm-Message-State: AOAM5334ByeT9+vdR8X2+lPTEImHVhsmahN+q35nPRW595ZoRxi+74Le pWjOebSg+svLtPSRiAirhLE= X-Google-Smtp-Source: ABdhPJyTvI12wWn8mrigq9l5gN+PBy6gzpWUCTZh4ozk54NQUFLwKUmcrBHB2RrIZczvLq5ZwnlD9Q== X-Received: by 2002:a1c:2185:0:b0:38f:f4ed:f964 with SMTP id h127-20020a1c2185000000b0038ff4edf964mr3358191wmh.115.1651843399520; Fri, 06 May 2022 06:23:19 -0700 (PDT) Received: from localhost ([62.96.65.119]) by smtp.gmail.com with ESMTPSA id v1-20020a05600c15c100b003942a244f2bsm7318524wmf.4.2022.05.06.06.23.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 06:23:18 -0700 (PDT) From: Thierry Reding To: Krzysztof Kozlowski Cc: Thierry Reding , Jon Hunter , Ashish Mhetre , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Osipenko Subject: [PATCH 3/4] memory: tegra: Add memory controller channels support Date: Fri, 6 May 2022 15:23:11 +0200 Message-Id: <20220506132312.3910637-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220506132312.3910637-1-thierry.reding@gmail.com> References: <20220506132312.3910637-1-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Ashish Mhetre From Tegra186 onwards, the memory controller supports multiple channels. Add support for mapping the address spaces of these channels and specify the number of channels supported by Tegra186, Tegra194 and Tegra234. In case of old bindings, channels won't be present. If channels are not present then print a warning and continue so that backward compatibility will be preserved in driver. During error interrupts from memory controller, appropriate registers from these channels need to be accessed for logging error info. Signed-off-by: Ashish Mhetre Reviewed-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra186.c | 30 ++++++++++++++++++++++++++++++ drivers/memory/tegra/tegra194.c | 1 + drivers/memory/tegra/tegra234.c | 1 + include/soc/tegra/mc.h | 3 +++ 4 files changed, 35 insertions(+) diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index 3d153881abc1..4a84752403d8 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -48,8 +48,37 @@ static void tegra186_mc_program_sid(struct tegra_mc *mc) =20 static int tegra186_mc_probe(struct tegra_mc *mc) { + struct platform_device *pdev =3D to_platform_device(mc->dev); + unsigned int i; + char name[8]; int err; =20 + mc->bcast_ch_regs =3D devm_platform_ioremap_resource_byname(pdev, "broadc= ast"); + if (IS_ERR(mc->bcast_ch_regs)) { + if (PTR_ERR(mc->bcast_ch_regs) =3D=3D -EINVAL) { + dev_warn(&pdev->dev, + "Broadcast channel is missing, please update your device-tree\n"); + mc->bcast_ch_regs =3D NULL; + goto populate; + } + + return PTR_ERR(mc->bcast_ch_regs); + } + + mc->ch_regs =3D devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->= ch_regs), + GFP_KERNEL); + if (!mc->ch_regs) + return -ENOMEM; + + for (i =3D 0; i < mc->soc->num_channels; i++) { + snprintf(name, sizeof(name), "ch%u", i); + + mc->ch_regs[i] =3D devm_platform_ioremap_resource_byname(pdev, name); + if (IS_ERR(mc->ch_regs[i])) + return PTR_ERR(mc->ch_regs[i]); + } + +populate: err =3D of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev); if (err < 0) return err; @@ -875,6 +904,7 @@ const struct tegra_mc_soc tegra186_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra186_mc_clients), .clients =3D tegra186_mc_clients, .num_address_bits =3D 40, + .num_channels =3D 4, .ops =3D &tegra186_mc_ops, }; #endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra19= 4.c index cab998b8bd5c..94001174deaf 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1347,5 +1347,6 @@ const struct tegra_mc_soc tegra194_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra194_mc_clients), .clients =3D tegra194_mc_clients, .num_address_bits =3D 40, + .num_channels =3D 16, .ops =3D &tegra186_mc_ops, }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index e22824a79f45..6335a132be2d 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -97,5 +97,6 @@ const struct tegra_mc_soc tegra234_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra234_mc_clients), .clients =3D tegra234_mc_clients, .num_address_bits =3D 40, + .num_channels =3D 16, .ops =3D &tegra186_mc_ops, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1066b1194a5a..40f1d02a1358 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -194,6 +194,7 @@ struct tegra_mc_soc { unsigned int atom_size; =20 u8 client_id_mask; + u8 num_channels; =20 const struct tegra_smmu_soc *smmu; =20 @@ -212,6 +213,8 @@ struct tegra_mc { struct tegra_smmu *smmu; struct gart_device *gart; void __iomem *regs; + void __iomem *bcast_ch_regs; + void __iomem **ch_regs; struct clk *clk; int irq; =20 --=20 2.35.1 From nobody Mon Jun 15 02:46:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABD4BC433EF for ; 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Fri, 06 May 2022 06:23:20 -0700 (PDT) From: Thierry Reding To: Krzysztof Kozlowski Cc: Thierry Reding , Jon Hunter , Ashish Mhetre , linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Osipenko Subject: [PATCH 4/4] memory: tegra: Add MC error logging on Tegra186 onward Date: Fri, 6 May 2022 15:23:12 +0200 Message-Id: <20220506132312.3910637-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220506132312.3910637-1-thierry.reding@gmail.com> References: <20220506132312.3910637-1-thierry.reding@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Ashish Mhetre Add support for logging memory controller errors on Tegra186, Tegra194 and Tegra234. On these SoCs, interrupts can occur on multiple channels. Add support required to read the status of interrupts across multiple channels, log and clear them. Also add new interrupts supported on these SoCs. Reviewed-by: Dmitry Osipenko Signed-off-by: Ashish Mhetre Signed-off-by: Thierry Reding --- drivers/memory/tegra/mc.c | 134 ++++++++++++++++++++++++++++---- drivers/memory/tegra/mc.h | 43 +++++++++- drivers/memory/tegra/tegra186.c | 9 +++ drivers/memory/tegra/tegra194.c | 8 ++ drivers/memory/tegra/tegra234.c | 8 ++ include/soc/tegra/mc.h | 5 +- 6 files changed, 189 insertions(+), 18 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index bf3abb6d8354..8395ab6046cf 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -508,14 +508,54 @@ int tegra30_mc_probe(struct tegra_mc *mc) return 0; } =20 -static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) +const struct tegra_mc_ops tegra30_mc_ops =3D { + .probe =3D tegra30_mc_probe, + .handle_irq =3D tegra30_mc_handle_irq, +}; +#endif + +static int mc_global_intstatus_to_channel(const struct tegra_mc *mc, u32 s= tatus, + unsigned int *mc_channel) +{ + if ((status & mc->soc->ch_intmask) =3D=3D 0) + return -EINVAL; + + *mc_channel =3D __ffs((status & mc->soc->ch_intmask) >> + mc->soc->global_intstatus_channel_shift); + + return 0; +} + +static u32 mc_channel_to_global_intstatus(const struct tegra_mc *mc, + unsigned int channel) +{ + return BIT(channel) << mc->soc->global_intstatus_channel_shift; +} + +irqreturn_t tegra30_mc_handle_irq(int irq, void *data) { struct tegra_mc *mc =3D data; + unsigned int bit, channel; unsigned long status; - unsigned int bit; =20 - /* mask all interrupts to avoid flooding */ - status =3D mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + if (mc->soc->num_channels) { + u32 global_status; + int err; + + global_status =3D mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTA= TUS); + err =3D mc_global_intstatus_to_channel(mc, global_status, &channel); + if (err < 0) { + dev_err_ratelimited(mc->dev, "unknown interrupt channel 0x%08x\n", + global_status); + return IRQ_NONE; + } + + /* mask all interrupts to avoid flooding */ + status =3D mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmask; + } else { + status =3D mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + } + if (!status) return IRQ_NONE; =20 @@ -523,18 +563,70 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, voi= d *data) const char *error =3D tegra_mc_status_names[bit] ?: "unknown"; const char *client =3D "unknown", *desc; const char *direction, *secure; + u32 status_reg, addr_reg; + u32 intmask =3D BIT(bit); phys_addr_t addr =3D 0; +#ifdef CONFIG_PHYS_ADDR_T_64BIT + u32 addr_hi_reg =3D 0; +#endif unsigned int i; char perm[7]; u8 id, type; u32 value; =20 - value =3D mc_readl(mc, MC_ERR_STATUS); + switch (intmask) { + case MC_INT_DECERR_VPR: + status_reg =3D MC_ERR_VPR_STATUS; + addr_reg =3D MC_ERR_VPR_ADR; + break; + + case MC_INT_SECERR_SEC: + status_reg =3D MC_ERR_SEC_STATUS; + addr_reg =3D MC_ERR_SEC_ADR; + break; + + case MC_INT_DECERR_MTS: + status_reg =3D MC_ERR_MTS_STATUS; + addr_reg =3D MC_ERR_MTS_ADR; + break; + + case MC_INT_DECERR_GENERALIZED_CARVEOUT: + status_reg =3D MC_ERR_GENERALIZED_CARVEOUT_STATUS; + addr_reg =3D MC_ERR_GENERALIZED_CARVEOUT_ADR; + break; + + case MC_INT_DECERR_ROUTE_SANITY: + status_reg =3D MC_ERR_ROUTE_SANITY_STATUS; + addr_reg =3D MC_ERR_ROUTE_SANITY_ADR; + break; + + default: + status_reg =3D MC_ERR_STATUS; + addr_reg =3D MC_ERR_ADR; + +#ifdef CONFIG_PHYS_ADDR_T_64BIT + if (mc->soc->has_addr_hi_reg) + addr_hi_reg =3D MC_ERR_ADR_HI; +#endif + break; + } + + if (mc->soc->num_channels) + value =3D mc_ch_readl(mc, channel, status_reg); + else + value =3D mc_readl(mc, status_reg); =20 #ifdef CONFIG_PHYS_ADDR_T_64BIT if (mc->soc->num_address_bits > 32) { - addr =3D ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & - MC_ERR_STATUS_ADR_HI_MASK); + if (addr_hi_reg) { + if (mc->soc->num_channels) + addr =3D mc_ch_readl(mc, channel, addr_hi_reg); + else + addr =3D mc_readl(mc, addr_hi_reg); + } else { + addr =3D ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & + MC_ERR_STATUS_ADR_HI_MASK); + } addr <<=3D 32; } #endif @@ -591,7 +683,10 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void= *data) break; } =20 - value =3D mc_readl(mc, MC_ERR_ADR); + if (mc->soc->num_channels) + value =3D mc_ch_readl(mc, channel, addr_reg); + else + value =3D mc_readl(mc, addr_reg); addr |=3D value; =20 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", @@ -600,17 +695,18 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, voi= d *data) } =20 /* clear interrupts */ - mc_writel(mc, status, MC_INTSTATUS); + if (mc->soc->num_channels) { + mc_ch_writel(mc, channel, status, MC_INTSTATUS); + mc_ch_writel(mc, MC_BROADCAST_CHANNEL, + mc_channel_to_global_intstatus(mc, channel), + MC_GLOBAL_INTSTATUS); + } else { + mc_writel(mc, status, MC_INTSTATUS); + } =20 return IRQ_HANDLED; } =20 -const struct tegra_mc_ops tegra30_mc_ops =3D { - .probe =3D tegra30_mc_probe, - .handle_irq =3D tegra30_mc_handle_irq, -}; -#endif - const char *const tegra_mc_status_names[32] =3D { [ 1] =3D "External interrupt", [ 6] =3D "EMEM address decode error", @@ -622,6 +718,8 @@ const char *const tegra_mc_status_names[32] =3D { [12] =3D "VPR violation", [13] =3D "Secure carveout violation", [16] =3D "MTS carveout violation", + [17] =3D "Generalized carveout violation", + [20] =3D "Route Sanity error", }; =20 const char *const tegra_mc_error_names[8] =3D { @@ -764,7 +862,11 @@ static int tegra_mc_probe(struct platform_device *pdev) =20 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); =20 - mc_writel(mc, mc->soc->intmask, MC_INTMASK); + if (mc->soc->num_channels) + mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask, + MC_INTMASK); + else + mc_writel(mc, mc->soc->intmask, MC_INTMASK); =20 err =3D devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, = 0, dev_name(&pdev->dev), mc); diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 062886e94c04..bc01586b6560 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -43,7 +43,21 @@ #define MC_EMEM_ARB_OVERRIDE 0xe8 #define MC_TIMING_CONTROL_DBG 0xf8 #define MC_TIMING_CONTROL 0xfc - +#define MC_ERR_VPR_STATUS 0x654 +#define MC_ERR_VPR_ADR 0x658 +#define MC_ERR_SEC_STATUS 0x67c +#define MC_ERR_SEC_ADR 0x680 +#define MC_ERR_MTS_STATUS 0x9b0 +#define MC_ERR_MTS_ADR 0x9b4 +#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0 +#define MC_ERR_ROUTE_SANITY_ADR 0x9c4 +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 +#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 +#define MC_GLOBAL_INTSTATUS 0xf24 +#define MC_ERR_ADR_HI 0x11fc + +#define MC_INT_DECERR_ROUTE_SANITY BIT(20) +#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) #define MC_INT_DECERR_MTS BIT(16) #define MC_INT_SECERR_SEC BIT(13) #define MC_INT_DECERR_VPR BIT(12) @@ -78,6 +92,8 @@ =20 #define MC_TIMING_UPDATE BIT(0) =20 +#define MC_BROADCAST_CHANNEL ~0 + static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) { val =3D val * percents; @@ -92,6 +108,30 @@ icc_provider_to_tegra_mc(struct icc_provider *provider) return container_of(provider, struct tegra_mc, provider); } =20 +static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch, + unsigned long offset) +{ + if (!mc->bcast_ch_regs) + return 0; + + if (ch =3D=3D MC_BROADCAST_CHANNEL) + return readl_relaxed(mc->bcast_ch_regs + offset); + + return readl_relaxed(mc->ch_regs[ch] + offset); +} + +static inline void mc_ch_writel(const struct tegra_mc *mc, int ch, + u32 value, unsigned long offset) +{ + if (!mc->bcast_ch_regs) + return; + + if (ch =3D=3D MC_BROADCAST_CHANNEL) + writel_relaxed(value, mc->bcast_ch_regs + offset); + else + writel_relaxed(value, mc->ch_regs[ch] + offset); +} + static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset) { return readl_relaxed(mc->regs + offset); @@ -156,6 +196,7 @@ extern const struct tegra_mc_ops tegra30_mc_ops; extern const struct tegra_mc_ops tegra186_mc_ops; #endif =20 +irqreturn_t tegra30_mc_handle_irq(int irq, void *data); extern const char * const tegra_mc_status_names[32]; extern const char * const tegra_mc_error_names[8]; =20 diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index 4a84752403d8..62477e592bf5 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -16,6 +16,8 @@ #include #endif =20 +#include "mc.h" + #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0) #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16) #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8) @@ -173,6 +175,7 @@ const struct tegra_mc_ops tegra186_mc_ops =3D { .remove =3D tegra186_mc_remove, .resume =3D tegra186_mc_resume, .probe_device =3D tegra186_mc_probe_device, + .handle_irq =3D tegra30_mc_handle_irq, }; =20 #if defined(CONFIG_ARCH_TEGRA_186_SOC) @@ -905,6 +908,12 @@ const struct tegra_mc_soc tegra186_mc_soc =3D { .clients =3D tegra186_mc_clients, .num_address_bits =3D 40, .num_channels =3D 4, + .client_id_mask =3D 0xff, + .intmask =3D MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .ops =3D &tegra186_mc_ops, + .ch_intmask =3D 0x0000000f, + .global_intstatus_channel_shift =3D 0, }; #endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra19= 4.c index 94001174deaf..b2416ee3ac26 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1348,5 +1348,13 @@ const struct tegra_mc_soc tegra194_mc_soc =3D { .clients =3D tegra194_mc_clients, .num_address_bits =3D 40, .num_channels =3D 16, + .client_id_mask =3D 0xff, + .intmask =3D MC_INT_DECERR_ROUTE_SANITY | + MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .has_addr_hi_reg =3D true, .ops =3D &tegra186_mc_ops, + .ch_intmask =3D 0x00000f00, + .global_intstatus_channel_shift =3D 8, }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index 6335a132be2d..e23ebd421f17 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -98,5 +98,13 @@ const struct tegra_mc_soc tegra234_mc_soc =3D { .clients =3D tegra234_mc_clients, .num_address_bits =3D 40, .num_channels =3D 16, + .client_id_mask =3D 0x1ff, + .intmask =3D MC_INT_DECERR_ROUTE_SANITY | + MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .has_addr_hi_reg =3D true, .ops =3D &tegra186_mc_ops, + .ch_intmask =3D 0x0000ff00, + .global_intstatus_channel_shift =3D 8, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 40f1d02a1358..47ce6d434427 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -193,12 +193,15 @@ struct tegra_mc_soc { unsigned int num_address_bits; unsigned int atom_size; =20 - u8 client_id_mask; + u16 client_id_mask; u8 num_channels; =20 const struct tegra_smmu_soc *smmu; =20 u32 intmask; + u32 ch_intmask; + u32 global_intstatus_channel_shift; + bool has_addr_hi_reg; =20 const struct tegra_mc_reset_ops *reset_ops; const struct tegra_mc_reset *resets; --=20 2.35.1