From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88087C4332F for ; Fri, 6 May 2022 09:29:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1390558AbiEFJc6 (ORCPT ); Fri, 6 May 2022 05:32:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390516AbiEFJct (ORCPT ); Fri, 6 May 2022 05:32:49 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2806664BEA; Fri, 6 May 2022 02:29:05 -0700 (PDT) X-UUID: b1610854f8324c899ba198efa27878a2-20220506 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:2ed41862-285e-404f-9af6-fc10e78759b3,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9,CLOUDID:ba5c7416-2e53-443e-b81a-655c13977218,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: b1610854f8324c899ba198efa27878a2-20220506 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1417832059; Fri, 06 May 2022 17:29:00 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 6 May 2022 17:28:58 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:28:57 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , Steve Cho , , , , , , Subject: [PATCH v11, 01/17] media: mediatek: vcodec: Add vdec enable/disable hardware helpers Date: Fri, 6 May 2022 17:28:39 +0800 Message-ID: <20220506092855.22940-2-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Lock, power and clock are highly coupled operations. Adds vdec enable/disable hardware helpers and uses them. Signed-off-by: Yunfei Dong Reviewed-by: Tzung-Bi Shih Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/mtk_vcodec_dec_drv.c | 5 - .../mediatek/vcodec/mtk_vcodec_dec_pm.c | 166 +++++++++++------- .../mediatek/vcodec/mtk_vcodec_dec_pm.h | 6 +- .../platform/mediatek/vcodec/vdec_drv_if.c | 20 +-- .../platform/mediatek/vcodec/vdec_msg_queue.c | 2 + 5 files changed, 116 insertions(+), 83 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c b/= drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c index df7b25e9cbc8..a84df6596aaa 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c @@ -193,9 +193,6 @@ static int fops_vcodec_open(struct file *file) mtk_vcodec_dec_set_default_params(ctx); =20 if (v4l2_fh_is_singular(&ctx->fh)) { - ret =3D mtk_vcodec_dec_pw_on(dev, MTK_VDEC_LAT0); - if (ret < 0) - goto err_load_fw; /* * Does nothing if firmware was already loaded. */ @@ -252,8 +249,6 @@ static int fops_vcodec_release(struct file *file) v4l2_m2m_ctx_release(ctx->m2m_ctx); mtk_vcodec_dec_release(ctx); =20 - if (v4l2_fh_is_singular(&ctx->fh)) - mtk_vcodec_dec_pw_off(dev, MTK_VDEC_LAT0); v4l2_fh_del(&ctx->fh); v4l2_fh_exit(&ctx->fh); v4l2_ctrl_handler_free(&ctx->ctrl_hdl); diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.c b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.c index 7e0c2644bf7b..0fb7e5ba635b 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.c @@ -57,74 +57,31 @@ int mtk_vcodec_init_dec_clk(struct platform_device *pde= v, struct mtk_vcodec_pm * } EXPORT_SYMBOL_GPL(mtk_vcodec_init_dec_clk); =20 -int mtk_vcodec_dec_pw_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx) +static int mtk_vcodec_dec_pw_on(struct mtk_vcodec_pm *pm) { - struct mtk_vdec_hw_dev *subdev_dev; - struct mtk_vcodec_pm *pm; int ret; =20 - if (vdec_dev->vdec_pdata->is_subdev_supported) { - subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); - if (!subdev_dev) { - mtk_v4l2_err("Failed to get hw dev\n"); - return -EINVAL; - } - pm =3D &subdev_dev->pm; - } else { - pm =3D &vdec_dev->pm; - } - ret =3D pm_runtime_resume_and_get(pm->dev); if (ret) mtk_v4l2_err("pm_runtime_resume_and_get fail %d", ret); =20 return ret; } -EXPORT_SYMBOL_GPL(mtk_vcodec_dec_pw_on); =20 -void mtk_vcodec_dec_pw_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx) +static void mtk_vcodec_dec_pw_off(struct mtk_vcodec_pm *pm) { - struct mtk_vdec_hw_dev *subdev_dev; - struct mtk_vcodec_pm *pm; int ret; =20 - if (vdec_dev->vdec_pdata->is_subdev_supported) { - subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); - if (!subdev_dev) { - mtk_v4l2_err("Failed to get hw dev\n"); - return; - } - pm =3D &subdev_dev->pm; - } else { - pm =3D &vdec_dev->pm; - } - ret =3D pm_runtime_put_sync(pm->dev); if (ret) mtk_v4l2_err("pm_runtime_put_sync fail %d", ret); } -EXPORT_SYMBOL_GPL(mtk_vcodec_dec_pw_off); =20 -void mtk_vcodec_dec_clock_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx) +static void mtk_vcodec_dec_clock_on(struct mtk_vcodec_pm *pm) { - struct mtk_vdec_hw_dev *subdev_dev; - struct mtk_vcodec_pm *pm; struct mtk_vcodec_clk *dec_clk; int ret, i; =20 - if (vdec_dev->vdec_pdata->is_subdev_supported) { - subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); - if (!subdev_dev) { - mtk_v4l2_err("Failed to get hw dev\n"); - return; - } - pm =3D &subdev_dev->pm; - enable_irq(subdev_dev->dec_irq); - } else { - pm =3D &vdec_dev->pm; - enable_irq(vdec_dev->dec_irq); - } - dec_clk =3D &pm->vdec_clk; for (i =3D 0; i < dec_clk->clk_num; i++) { ret =3D clk_prepare_enable(dec_clk->clk_info[i].vcodec_clk); @@ -140,30 +97,119 @@ void mtk_vcodec_dec_clock_on(struct mtk_vcodec_dev *v= dec_dev, int hw_idx) for (i -=3D 1; i >=3D 0; i--) clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); } -EXPORT_SYMBOL_GPL(mtk_vcodec_dec_clock_on); =20 -void mtk_vcodec_dec_clock_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx) +static void mtk_vcodec_dec_clock_off(struct mtk_vcodec_pm *pm) { - struct mtk_vdec_hw_dev *subdev_dev; - struct mtk_vcodec_pm *pm; struct mtk_vcodec_clk *dec_clk; int i; =20 + dec_clk =3D &pm->vdec_clk; + for (i =3D dec_clk->clk_num - 1; i >=3D 0; i--) + clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); +} + +static void mtk_vcodec_dec_enable_irq(struct mtk_vcodec_dev *vdec_dev, int= hw_idx) +{ + struct mtk_vdec_hw_dev *subdev_dev; + + if (!test_bit(hw_idx, vdec_dev->subdev_bitmap)) + return; + if (vdec_dev->vdec_pdata->is_subdev_supported) { subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); - if (!subdev_dev) { + if (subdev_dev) + enable_irq(subdev_dev->dec_irq); + else + mtk_v4l2_err("Failed to get hw dev\n"); + } else { + enable_irq(vdec_dev->dec_irq); + } +} + +static void mtk_vcodec_dec_disable_irq(struct mtk_vcodec_dev *vdec_dev, in= t hw_idx) +{ + struct mtk_vdec_hw_dev *subdev_dev; + + if (!test_bit(hw_idx, vdec_dev->subdev_bitmap)) + return; + + if (vdec_dev->vdec_pdata->is_subdev_supported) { + subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); + if (subdev_dev) + disable_irq(subdev_dev->dec_irq); + else mtk_v4l2_err("Failed to get hw dev\n"); - return; - } - pm =3D &subdev_dev->pm; - disable_irq(subdev_dev->dec_irq); } else { - pm =3D &vdec_dev->pm; disable_irq(vdec_dev->dec_irq); } +} =20 - dec_clk =3D &pm->vdec_clk; - for (i =3D dec_clk->clk_num - 1; i >=3D 0; i--) - clk_disable_unprepare(dec_clk->clk_info[i].vcodec_clk); +static struct mtk_vcodec_pm *mtk_vcodec_dec_get_pm(struct mtk_vcodec_dev *= vdec_dev, + int hw_idx) +{ + struct mtk_vdec_hw_dev *subdev_dev; + + if (!test_bit(hw_idx, vdec_dev->subdev_bitmap)) + return NULL; + + if (vdec_dev->vdec_pdata->is_subdev_supported) { + subdev_dev =3D mtk_vcodec_get_hw_dev(vdec_dev, hw_idx); + if (subdev_dev) + return &subdev_dev->pm; + + mtk_v4l2_err("Failed to get hw dev\n"); + return NULL; + } + + return &vdec_dev->pm; +} + +static void mtk_vcodec_dec_child_dev_on(struct mtk_vcodec_dev *vdec_dev, + int hw_idx) +{ + struct mtk_vcodec_pm *pm; + + pm =3D mtk_vcodec_dec_get_pm(vdec_dev, hw_idx); + if (pm) { + mtk_vcodec_dec_pw_on(pm); + mtk_vcodec_dec_clock_on(pm); + } +} + +static void mtk_vcodec_dec_child_dev_off(struct mtk_vcodec_dev *vdec_dev, + int hw_idx) +{ + struct mtk_vcodec_pm *pm; + + pm =3D mtk_vcodec_dec_get_pm(vdec_dev, hw_idx); + if (pm) { + mtk_vcodec_dec_clock_off(pm); + mtk_vcodec_dec_pw_off(pm); + } +} + +void mtk_vcodec_dec_enable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx) +{ + mutex_lock(&ctx->dev->dec_mutex[hw_idx]); + + if (IS_VDEC_LAT_ARCH(ctx->dev->vdec_pdata->hw_arch) && + hw_idx =3D=3D MTK_VDEC_CORE) + mtk_vcodec_dec_child_dev_on(ctx->dev, MTK_VDEC_LAT0); + mtk_vcodec_dec_child_dev_on(ctx->dev, hw_idx); + + mtk_vcodec_dec_enable_irq(ctx->dev, hw_idx); +} +EXPORT_SYMBOL_GPL(mtk_vcodec_dec_enable_hardware); + +void mtk_vcodec_dec_disable_hardware(struct mtk_vcodec_ctx *ctx, int hw_id= x) +{ + mtk_vcodec_dec_disable_irq(ctx->dev, hw_idx); + + mtk_vcodec_dec_child_dev_off(ctx->dev, hw_idx); + if (IS_VDEC_LAT_ARCH(ctx->dev->vdec_pdata->hw_arch) && + hw_idx =3D=3D MTK_VDEC_CORE) + mtk_vcodec_dec_child_dev_off(ctx->dev, MTK_VDEC_LAT0); + + mutex_unlock(&ctx->dev->dec_mutex[hw_idx]); } -EXPORT_SYMBOL_GPL(mtk_vcodec_dec_clock_off); +EXPORT_SYMBOL_GPL(mtk_vcodec_dec_disable_hardware); diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.h b/d= rivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.h index 3cc721bbfaf6..dbcf3cabe6f3 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_pm.h @@ -11,9 +11,7 @@ =20 int mtk_vcodec_init_dec_clk(struct platform_device *pdev, struct mtk_vcode= c_pm *pm); =20 -int mtk_vcodec_dec_pw_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx); -void mtk_vcodec_dec_pw_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx); -void mtk_vcodec_dec_clock_on(struct mtk_vcodec_dev *vdec_dev, int hw_idx); -void mtk_vcodec_dec_clock_off(struct mtk_vcodec_dev *vdec_dev, int hw_idx); +void mtk_vcodec_dec_enable_hardware(struct mtk_vcodec_ctx *ctx, int hw_idx= ); +void mtk_vcodec_dec_disable_hardware(struct mtk_vcodec_ctx *ctx, int hw_id= x); =20 #endif /* _MTK_VCODEC_DEC_PM_H_ */ diff --git a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c b/drivers= /media/platform/mediatek/vcodec/vdec_drv_if.c index 05a5b240e906..c93dd0ea3537 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c @@ -38,11 +38,9 @@ int vdec_if_init(struct mtk_vcodec_ctx *ctx, unsigned in= t fourcc) return -EINVAL; } =20 - mtk_vdec_lock(ctx); - mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); + mtk_vcodec_dec_enable_hardware(ctx, ctx->hw_id); ret =3D ctx->dec_if->init(ctx); - mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); - mtk_vdec_unlock(ctx); + mtk_vcodec_dec_disable_hardware(ctx, ctx->hw_id); =20 return ret; } @@ -70,15 +68,11 @@ int vdec_if_decode(struct mtk_vcodec_ctx *ctx, struct m= tk_vcodec_mem *bs, if (!ctx->drv_handle) return -EIO; =20 - mtk_vdec_lock(ctx); - + mtk_vcodec_dec_enable_hardware(ctx, ctx->hw_id); mtk_vcodec_set_curr_ctx(ctx->dev, ctx, ctx->hw_id); - mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); ret =3D ctx->dec_if->decode(ctx->drv_handle, bs, fb, res_chg); - mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); mtk_vcodec_set_curr_ctx(ctx->dev, NULL, ctx->hw_id); - - mtk_vdec_unlock(ctx); + mtk_vcodec_dec_disable_hardware(ctx, ctx->hw_id); =20 return ret; } @@ -103,11 +97,9 @@ void vdec_if_deinit(struct mtk_vcodec_ctx *ctx) if (!ctx->drv_handle) return; =20 - mtk_vdec_lock(ctx); - mtk_vcodec_dec_clock_on(ctx->dev, ctx->hw_id); + mtk_vcodec_dec_enable_hardware(ctx, ctx->hw_id); ctx->dec_if->deinit(ctx->drv_handle); - mtk_vcodec_dec_clock_off(ctx->dev, ctx->hw_id); - mtk_vdec_unlock(ctx); + mtk_vcodec_dec_disable_hardware(ctx, ctx->hw_id); =20 ctx->drv_handle =3D NULL; } diff --git a/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.c b/driv= ers/media/platform/mediatek/vcodec/vdec_msg_queue.c index 4b062a8128b4..ae500980ad45 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.c +++ b/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.c @@ -212,11 +212,13 @@ static void vdec_msg_queue_core_work(struct work_stru= ct *work) return; =20 ctx =3D lat_buf->ctx; + mtk_vcodec_dec_enable_hardware(ctx, MTK_VDEC_CORE); mtk_vcodec_set_curr_ctx(dev, ctx, MTK_VDEC_CORE); =20 lat_buf->core_decode(lat_buf); =20 mtk_vcodec_set_curr_ctx(dev, NULL, MTK_VDEC_CORE); + mtk_vcodec_dec_disable_hardware(ctx, MTK_VDEC_CORE); vdec_msg_queue_qbuf(&ctx->msg_queue.lat_ctx, lat_buf); =20 if (!list_empty(&ctx->msg_queue.lat_ctx.ready_queue)) { --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EAC9C43217 for ; Fri, 6 May 2022 09:29:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1390562AbiEFJdC (ORCPT ); Fri, 6 May 2022 05:33:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390519AbiEFJcu (ORCPT ); Fri, 6 May 2022 05:32:50 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3D2A64BF1; Fri, 6 May 2022 02:29:06 -0700 (PDT) X-UUID: 905d5a915421414f9510006cab382a83-20220506 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:f71b9c54-6e6e-4da4-8578-55b20c3621c0,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:3,FILE:0,RULE:Release_Ham,AC TION:release,TS:-17 X-CID-INFO: VERSION:1.1.4,REQID:f71b9c54-6e6e-4da4-8578-55b20c3621c0,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:3,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:-17 X-CID-META: VersionHash:faefae9,CLOUDID:df06d4b2-56b5-4c9e-8d83-0070b288eb6a,C OID:IGNORED,Recheck:0,SF:28|100|17|19|48|101|20,TC:nil,Content:0,EDM:-3,Fi le:nil,QS:0,BEC:nil X-UUID: 905d5a915421414f9510006cab382a83-20220506 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1404850981; Fri, 06 May 2022 17:29:02 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 6 May 2022 17:29:01 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:28:58 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 02/17] media: mediatek: vcodec: Using firmware type to separate different firmware architecture Date: Fri, 6 May 2022 17:28:40 +0800 Message-ID: <20220506092855.22940-3-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" MT8173 platform use vpu firmware, mt8183/mt8192 will use scp firmware instead, using chip name is not reasonable to separate different firmware architecture. Using firmware type is much better. Signed-off-by: Yunfei Dong Reviewed-by: Tzung-Bi Shih Reviewed-by: AngeloGioacchino Del Regno --- .../mediatek/vcodec/mtk_vcodec_dec_stateful.c | 1 - .../mediatek/vcodec/mtk_vcodec_dec_stateless.c | 2 -- .../media/platform/mediatek/vcodec/mtk_vcodec_drv.h | 13 ------------- .../platform/mediatek/vcodec/mtk_vcodec_enc_drv.c | 5 ----- .../media/platform/mediatek/vcodec/mtk_vcodec_fw.c | 6 ++++++ .../media/platform/mediatek/vcodec/mtk_vcodec_fw.h | 1 + .../media/platform/mediatek/vcodec/vdec_vpu_if.c | 4 ++-- .../media/platform/mediatek/vcodec/venc_vpu_if.c | 2 +- 8 files changed, 10 insertions(+), 24 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful= .c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful.c index 04ca43c77e5f..7966c132be8f 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful.c @@ -613,7 +613,6 @@ static struct vb2_ops mtk_vdec_frame_vb2_ops =3D { }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata =3D { - .chip =3D MTK_MT8173, .init_vdec_params =3D mtk_init_vdec_params, .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_frame_vb2_ops, diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateles= s.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c index 23d997ac114d..5aebf88f997b 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c @@ -343,7 +343,6 @@ static struct vb2_ops mtk_vdec_request_vb2_ops =3D { }; =20 const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata =3D { - .chip =3D MTK_MT8183, .init_vdec_params =3D mtk_init_vdec_params, .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, @@ -362,7 +361,6 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { =20 /* This platform data is used for one lat and one core architecture. */ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdata =3D { - .chip =3D MTK_MT8192, .init_vdec_params =3D mtk_init_vdec_params, .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index 813901c4be5e..bb7b8e914d24 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -332,13 +332,6 @@ struct mtk_vcodec_ctx { struct vdec_msg_queue msg_queue; }; =20 -enum mtk_chip { - MTK_MT8173, - MTK_MT8183, - MTK_MT8192, - MTK_MT8195, -}; - /* * enum mtk_vdec_hw_arch - Used to separate different hardware architecture */ @@ -364,7 +357,6 @@ enum mtk_vdec_hw_arch { * @vdec_framesizes: supported video decoder frame sizes * @num_framesizes: count of video decoder frame sizes * - * @chip: chip this decoder is compatible with * @hw_arch: hardware arch is used to separate pure_sin_core and lat_sin_c= ore * * @is_subdev_supported: whether support parent-node architecture(subdev) @@ -387,7 +379,6 @@ struct mtk_vcodec_dec_pdata { const struct mtk_codec_framesizes *vdec_framesizes; const int num_framesizes; =20 - enum mtk_chip chip; enum mtk_vdec_hw_arch hw_arch; =20 bool is_subdev_supported; @@ -397,8 +388,6 @@ struct mtk_vcodec_dec_pdata { /** * struct mtk_vcodec_enc_pdata - compatible data for each IC * - * @chip: chip this encoder is compatible with - * * @uses_ext: whether the encoder uses the extended firmware messaging for= mat * @min_bitrate: minimum supported encoding bitrate * @max_bitrate: maximum supported encoding bitrate @@ -409,8 +398,6 @@ struct mtk_vcodec_dec_pdata { * @core_id: stand for h264 or vp8 encode index */ struct mtk_vcodec_enc_pdata { - enum mtk_chip chip; - bool uses_ext; unsigned long min_bitrate; unsigned long max_bitrate; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c b/= drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c index 5172cfe0db4a..95e8c29ccc65 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_enc_drv.c @@ -376,7 +376,6 @@ static int mtk_vcodec_probe(struct platform_device *pde= v) } =20 static const struct mtk_vcodec_enc_pdata mt8173_avc_pdata =3D { - .chip =3D MTK_MT8173, .capture_formats =3D mtk_video_formats_capture_h264, .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), .output_formats =3D mtk_video_formats_output, @@ -387,7 +386,6 @@ static const struct mtk_vcodec_enc_pdata mt8173_avc_pda= ta =3D { }; =20 static const struct mtk_vcodec_enc_pdata mt8173_vp8_pdata =3D { - .chip =3D MTK_MT8173, .capture_formats =3D mtk_video_formats_capture_vp8, .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_vp8), .output_formats =3D mtk_video_formats_output, @@ -398,7 +396,6 @@ static const struct mtk_vcodec_enc_pdata mt8173_vp8_pda= ta =3D { }; =20 static const struct mtk_vcodec_enc_pdata mt8183_pdata =3D { - .chip =3D MTK_MT8183, .uses_ext =3D true, .capture_formats =3D mtk_video_formats_capture_h264, .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), @@ -410,7 +407,6 @@ static const struct mtk_vcodec_enc_pdata mt8183_pdata = =3D { }; =20 static const struct mtk_vcodec_enc_pdata mt8192_pdata =3D { - .chip =3D MTK_MT8192, .uses_ext =3D true, .capture_formats =3D mtk_video_formats_capture_h264, .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), @@ -422,7 +418,6 @@ static const struct mtk_vcodec_enc_pdata mt8192_pdata = =3D { }; =20 static const struct mtk_vcodec_enc_pdata mt8195_pdata =3D { - .chip =3D MTK_MT8195, .uses_ext =3D true, .capture_formats =3D mtk_video_formats_capture_h264, .num_capture_formats =3D ARRAY_SIZE(mtk_video_formats_capture_h264), diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw.c b/drive= rs/media/platform/mediatek/vcodec/mtk_vcodec_fw.c index 94b39ae5c2e1..556e54aadac9 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw.c @@ -65,3 +65,9 @@ int mtk_vcodec_fw_ipi_send(struct mtk_vcodec_fw *fw, int = id, void *buf, return fw->ops->ipi_send(fw, id, buf, len, wait); } EXPORT_SYMBOL_GPL(mtk_vcodec_fw_ipi_send); + +int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw) +{ + return fw->type; +} +EXPORT_SYMBOL_GPL(mtk_vcodec_fw_get_type); diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw.h b/drive= rs/media/platform/mediatek/vcodec/mtk_vcodec_fw.h index 15ab6b8e3ae2..16824114657f 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw.h @@ -39,5 +39,6 @@ int mtk_vcodec_fw_ipi_register(struct mtk_vcodec_fw *fw, = int id, const char *name, void *priv); int mtk_vcodec_fw_ipi_send(struct mtk_vcodec_fw *fw, int id, void *buf, unsigned int len, unsigned int wait); +int mtk_vcodec_fw_get_type(struct mtk_vcodec_fw *fw); =20 #endif /* _MTK_VCODEC_FW_H_ */ diff --git a/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.c b/drivers= /media/platform/mediatek/vcodec/vdec_vpu_if.c index dd35d2c5f920..7210061c772f 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.c @@ -33,8 +33,8 @@ static void handle_init_ack_msg(const struct vdec_vpu_ipi= _init_ack *msg) */ vpu->inst_id =3D 0xdeadbeef; =20 - /* Firmware version field does not exist on MT8173. */ - if (vpu->ctx->dev->vdec_pdata->chip =3D=3D MTK_MT8173) + /* VPU firmware does not contain a version field. */ + if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) =3D=3D VPU) return; =20 /* Check firmware version. */ diff --git a/drivers/media/platform/mediatek/vcodec/venc_vpu_if.c b/drivers= /media/platform/mediatek/vcodec/venc_vpu_if.c index e7899d8a3e4e..d3570c4c177d 100644 --- a/drivers/media/platform/mediatek/vcodec/venc_vpu_if.c +++ b/drivers/media/platform/mediatek/vcodec/venc_vpu_if.c @@ -18,7 +18,7 @@ static void handle_enc_init_msg(struct venc_vpu_inst *vpu= , const void *data) msg->vpu_inst_addr); =20 /* Firmware version field value is unspecified on MT8173. */ - if (vpu->ctx->dev->venc_pdata->chip =3D=3D MTK_MT8173) + if (mtk_vcodec_fw_get_type(vpu->ctx->dev->fw_handler) =3D=3D VPU) return; =20 /* Check firmware version. */ --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 492ECC433F5 for ; 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Fri, 06 May 2022 17:29:04 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 6 May 2022 17:29:03 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 6 May 2022 17:29:02 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:01 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 03/17] media: mediatek: vcodec: get capture queue buffer size from scp Date: Fri, 6 May 2022 17:28:41 +0800 Message-ID: <20220506092855.22940-4-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Different capture buffer format has different buffer size, need to get real buffer size according to buffer type from scp. Signed-off-by: Yunfei Dong --- .../platform/mediatek/vcodec/vdec_ipi_msg.h | 36 ++++++++++++++ .../platform/mediatek/vcodec/vdec_vpu_if.c | 49 +++++++++++++++++++ .../platform/mediatek/vcodec/vdec_vpu_if.h | 13 +++++ 3 files changed, 98 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/vdec_ipi_msg.h b/driver= s/media/platform/mediatek/vcodec/vdec_ipi_msg.h index bf54d6d9a857..47070be2a991 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_ipi_msg.h +++ b/drivers/media/platform/mediatek/vcodec/vdec_ipi_msg.h @@ -20,6 +20,7 @@ enum vdec_ipi_msgid { AP_IPIMSG_DEC_RESET =3D 0xA004, AP_IPIMSG_DEC_CORE =3D 0xA005, AP_IPIMSG_DEC_CORE_END =3D 0xA006, + AP_IPIMSG_DEC_GET_PARAM =3D 0xA007, =20 VPU_IPIMSG_DEC_INIT_ACK =3D 0xB000, VPU_IPIMSG_DEC_START_ACK =3D 0xB001, @@ -28,6 +29,7 @@ enum vdec_ipi_msgid { VPU_IPIMSG_DEC_RESET_ACK =3D 0xB004, VPU_IPIMSG_DEC_CORE_ACK =3D 0xB005, VPU_IPIMSG_DEC_CORE_END_ACK =3D 0xB006, + VPU_IPIMSG_DEC_GET_PARAM_ACK =3D 0xB007, }; =20 /** @@ -114,4 +116,38 @@ struct vdec_vpu_ipi_init_ack { uint32_t inst_id; }; =20 +/** + * struct vdec_ap_ipi_get_param - for AP_IPIMSG_DEC_GET_PARAM + * @msg_id : AP_IPIMSG_DEC_GET_PARAM + * @inst_id : instance ID. Used if the ABI version >=3D 2. + * @data : picture information + * @param_type : get param type + * @codec_type : Codec fourcc + */ +struct vdec_ap_ipi_get_param { + u32 msg_id; + u32 inst_id; + u32 data[4]; + u32 param_type; + u32 codec_type; +}; + +/** + * struct vdec_vpu_ipi_get_param_ack - for VPU_IPIMSG_DEC_GET_PARAM_ACK + * @msg_id : VPU_IPIMSG_DEC_GET_PARAM_ACK + * @status : VPU execution result + * @ap_inst_addr : AP vcodec_vpu_inst instance address + * @data : picture information from SCP. + * @param_type : get param type + * @reserved : reserved param + */ +struct vdec_vpu_ipi_get_param_ack { + u32 msg_id; + s32 status; + u64 ap_inst_addr; + u32 data[4]; + u32 param_type; + u32 reserved; +}; + #endif diff --git a/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.c b/drivers= /media/platform/mediatek/vcodec/vdec_vpu_if.c index 7210061c772f..35f4d5583084 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.c @@ -6,6 +6,7 @@ =20 #include "mtk_vcodec_drv.h" #include "mtk_vcodec_util.h" +#include "vdec_drv_if.h" #include "vdec_ipi_msg.h" #include "vdec_vpu_if.h" #include "mtk_vcodec_fw.h" @@ -54,6 +55,26 @@ static void handle_init_ack_msg(const struct vdec_vpu_ip= i_init_ack *msg) } } =20 +static void handle_get_param_msg_ack(const struct vdec_vpu_ipi_get_param_a= ck *msg) +{ + struct vdec_vpu_inst *vpu =3D (struct vdec_vpu_inst *) + (unsigned long)msg->ap_inst_addr; + + mtk_vcodec_debug(vpu, "+ ap_inst_addr =3D 0x%llx", msg->ap_inst_addr); + + /* param_type is enum vdec_get_param_type */ + switch (msg->param_type) { + case GET_PARAM_PIC_INFO: + vpu->fb_sz[0] =3D msg->data[0]; + vpu->fb_sz[1] =3D msg->data[1]; + break; + default: + mtk_vcodec_err(vpu, "invalid get param type=3D%d", msg->param_type); + vpu->failure =3D 1; + break; + } +} + /* * vpu_dec_ipi_handler - Handler for VPU ipi message. * @@ -89,6 +110,9 @@ static void vpu_dec_ipi_handler(void *data, unsigned int= len, void *priv) case VPU_IPIMSG_DEC_CORE_END_ACK: break; =20 + case VPU_IPIMSG_DEC_GET_PARAM_ACK: + handle_get_param_msg_ack(data); + break; default: mtk_vcodec_err(vpu, "invalid msg=3D%X", msg->msg_id); break; @@ -217,6 +241,31 @@ int vpu_dec_start(struct vdec_vpu_inst *vpu, uint32_t = *data, unsigned int len) return err; } =20 +int vpu_dec_get_param(struct vdec_vpu_inst *vpu, uint32_t *data, + unsigned int len, unsigned int param_type) +{ + struct vdec_ap_ipi_get_param msg; + int err; + + mtk_vcodec_debug_enter(vpu); + + if (len > ARRAY_SIZE(msg.data)) { + mtk_vcodec_err(vpu, "invalid len =3D %d\n", len); + return -EINVAL; + } + + memset(&msg, 0, sizeof(msg)); + msg.msg_id =3D AP_IPIMSG_DEC_GET_PARAM; + msg.inst_id =3D vpu->inst_id; + memcpy(msg.data, data, sizeof(unsigned int) * len); + msg.param_type =3D param_type; + msg.codec_type =3D vpu->codec_type; + + err =3D vcodec_vpu_send_msg(vpu, (void *)&msg, sizeof(msg)); + mtk_vcodec_debug(vpu, "- ret=3D%d", err); + return err; +} + int vpu_dec_core(struct vdec_vpu_inst *vpu) { return vcodec_send_ap_ipi(vpu, AP_IPIMSG_DEC_CORE); diff --git a/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.h b/drivers= /media/platform/mediatek/vcodec/vdec_vpu_if.h index 4cb3c7f5a3ad..fe6815d31e50 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.h +++ b/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.h @@ -28,6 +28,7 @@ struct mtk_vcodec_ctx; * @wq : wait queue to wait VPU message ack * @handler : ipi handler for each decoder * @codec_type : use codec type to separate different codecs + * @fb_sz : frame buffer size of each plane */ struct vdec_vpu_inst { int id; @@ -42,6 +43,7 @@ struct vdec_vpu_inst { wait_queue_head_t wq; mtk_vcodec_ipi_handler handler; unsigned int codec_type; + unsigned int fb_sz[2]; }; =20 /** @@ -104,4 +106,15 @@ int vpu_dec_core(struct vdec_vpu_inst *vpu); */ int vpu_dec_core_end(struct vdec_vpu_inst *vpu); =20 +/** + * vpu_dec_get_param - get param from scp + * + * @vpu : instance for vdec_vpu_inst + * @data: meta data to pass bitstream info to VPU decoder + * @len : meta data length + * @param_type : get param type + */ +int vpu_dec_get_param(struct vdec_vpu_inst *vpu, uint32_t *data, + unsigned int len, unsigned int param_type); + #endif --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35812C433EF for ; Fri, 6 May 2022 09:29:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1390570AbiEFJdP (ORCPT ); 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charset="utf-8" Supported max resolution for different platforms are not the same: 2K or 4K, getting it according to dec_capability. Signed-off-by: Yunfei Dong Reviewed-by: Tzung-Bi Shih Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/vcodec/mtk_vcodec_dec.c | 44 ++++++++++--------- .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 4 ++ 2 files changed, 28 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c index 130ecef2e766..e42d5c17d90e 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c @@ -152,13 +152,15 @@ void mtk_vcodec_dec_set_default_params(struct mtk_vco= dec_ctx *ctx) q_data->coded_height =3D DFT_CFG_HEIGHT; q_data->fmt =3D ctx->dev->vdec_pdata->default_cap_fmt; q_data->field =3D V4L2_FIELD_NONE; + ctx->max_width =3D MTK_VDEC_MAX_W; + ctx->max_height =3D MTK_VDEC_MAX_H; =20 v4l_bound_align_image(&q_data->coded_width, MTK_VDEC_MIN_W, - MTK_VDEC_MAX_W, 4, + ctx->max_width, 4, &q_data->coded_height, MTK_VDEC_MIN_H, - MTK_VDEC_MAX_H, 5, 6); + ctx->max_height, 5, 6); =20 q_data->sizeimage[0] =3D q_data->coded_width * q_data->coded_height; q_data->bytesperline[0] =3D q_data->coded_width; @@ -217,7 +219,7 @@ static int vidioc_vdec_subscribe_evt(struct v4l2_fh *fh, } } =20 -static int vidioc_try_fmt(struct v4l2_format *f, +static int vidioc_try_fmt(struct mtk_vcodec_ctx *ctx, struct v4l2_format *= f, const struct mtk_video_fmt *fmt) { struct v4l2_pix_format_mplane *pix_fmt_mp =3D &f->fmt.pix_mp; @@ -225,9 +227,9 @@ static int vidioc_try_fmt(struct v4l2_format *f, pix_fmt_mp->field =3D V4L2_FIELD_NONE; =20 pix_fmt_mp->width =3D - clamp(pix_fmt_mp->width, MTK_VDEC_MIN_W, MTK_VDEC_MAX_W); + clamp(pix_fmt_mp->width, MTK_VDEC_MIN_W, ctx->max_width); pix_fmt_mp->height =3D - clamp(pix_fmt_mp->height, MTK_VDEC_MIN_H, MTK_VDEC_MAX_H); + clamp(pix_fmt_mp->height, MTK_VDEC_MIN_H, ctx->max_height); =20 if (f->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { pix_fmt_mp->num_planes =3D 1; @@ -245,16 +247,16 @@ static int vidioc_try_fmt(struct v4l2_format *f, tmp_h =3D pix_fmt_mp->height; v4l_bound_align_image(&pix_fmt_mp->width, MTK_VDEC_MIN_W, - MTK_VDEC_MAX_W, 6, + ctx->max_width, 6, &pix_fmt_mp->height, MTK_VDEC_MIN_H, - MTK_VDEC_MAX_H, 6, 9); + ctx->max_height, 6, 9); =20 if (pix_fmt_mp->width < tmp_w && - (pix_fmt_mp->width + 64) <=3D MTK_VDEC_MAX_W) + (pix_fmt_mp->width + 64) <=3D ctx->max_width) pix_fmt_mp->width +=3D 64; if (pix_fmt_mp->height < tmp_h && - (pix_fmt_mp->height + 64) <=3D MTK_VDEC_MAX_H) + (pix_fmt_mp->height + 64) <=3D ctx->max_height) pix_fmt_mp->height +=3D 64; =20 mtk_v4l2_debug(0, @@ -294,7 +296,7 @@ static int vidioc_try_fmt_vid_cap_mplane(struct file *f= ile, void *priv, fmt =3D mtk_vdec_find_format(f, dec_pdata); } =20 - return vidioc_try_fmt(f, fmt); + return vidioc_try_fmt(ctx, f, fmt); } =20 static int vidioc_try_fmt_vid_out_mplane(struct file *file, void *priv, @@ -317,7 +319,7 @@ static int vidioc_try_fmt_vid_out_mplane(struct file *f= ile, void *priv, return -EINVAL; } =20 - return vidioc_try_fmt(f, fmt); + return vidioc_try_fmt(ctx, f, fmt); } =20 static int vidioc_vdec_g_selection(struct file *file, void *priv, @@ -444,8 +446,14 @@ static int vidioc_vdec_s_fmt(struct file *file, void *= priv, if (fmt =3D=3D NULL) return -EINVAL; =20 + if (!(ctx->dev->dec_capability & VCODEC_CAPABILITY_4K_DISABLED)) { + mtk_v4l2_debug(3, "4K is enabled"); + ctx->max_width =3D VCODEC_DEC_4K_CODED_WIDTH; + ctx->max_height =3D VCODEC_DEC_4K_CODED_HEIGHT; + } + q_data->fmt =3D fmt; - vidioc_try_fmt(f, q_data->fmt); + vidioc_try_fmt(ctx, f, q_data->fmt); if (f->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { q_data->sizeimage[0] =3D pix_mp->plane_fmt[0].sizeimage; q_data->coded_width =3D pix_mp->width; @@ -529,14 +537,9 @@ static int vidioc_enum_framesizes(struct file *file, v= oid *priv, =20 fsize->type =3D V4L2_FRMSIZE_TYPE_STEPWISE; fsize->stepwise =3D dec_pdata->vdec_framesizes[i].stepwise; - if (!(ctx->dev->dec_capability & - VCODEC_CAPABILITY_4K_DISABLED)) { - mtk_v4l2_debug(3, "4K is enabled"); - fsize->stepwise.max_width =3D - VCODEC_DEC_4K_CODED_WIDTH; - fsize->stepwise.max_height =3D - VCODEC_DEC_4K_CODED_HEIGHT; - } + + fsize->stepwise.max_width =3D ctx->max_width; + fsize->stepwise.max_height =3D ctx->max_height; mtk_v4l2_debug(1, "%x, %d %d %d %d %d %d", ctx->dev->dec_capability, fsize->stepwise.min_width, @@ -545,6 +548,7 @@ static int vidioc_enum_framesizes(struct file *file, vo= id *priv, fsize->stepwise.min_height, fsize->stepwise.max_height, fsize->stepwise.step_height); + return 0; } =20 diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index bb7b8e914d24..6d27e4d41ede 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -284,6 +284,8 @@ struct vdec_pic_info { * mtk_video_dec_buf. * @hw_id: hardware index used to identify different hardware. * + * @max_width: hardware supported max width + * @max_height: hardware supported max height * @msg_queue: msg queue used to store lat buffer information. */ struct mtk_vcodec_ctx { @@ -329,6 +331,8 @@ struct mtk_vcodec_ctx { struct mutex lock; int hw_id; =20 + unsigned int max_width; + unsigned int max_height; struct vdec_msg_queue msg_queue; }; =20 --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89115C433F5 for ; Fri, 6 May 2022 09:29:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350749AbiEFJd1 (ORCPT ); Fri, 6 May 2022 05:33:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390538AbiEFJcx (ORCPT ); Fri, 6 May 2022 05:32:53 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0648565430; Fri, 6 May 2022 02:29:09 -0700 (PDT) X-UUID: bda17264ed9f43929bc036bd0b451ece-20220506 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:d162a79d-01fb-4991-aadd-c1439e0d3be2,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:100,FILE:0,RULE:Release_Ham, ACTION:release,TS:80 X-CID-INFO: VERSION:1.1.4,REQID:d162a79d-01fb-4991-aadd-c1439e0d3be2,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:100,FILE:0,RULE:Spam_GS981B3D, ACTION:quarantine,TS:80 X-CID-META: VersionHash:faefae9,CLOUDID:1e5e7416-2e53-443e-b81a-655c13977218,C OID:9b02348ab250,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: bda17264ed9f43929bc036bd0b451ece-20220506 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1337607451; Fri, 06 May 2022 17:29:07 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 6 May 2022 17:29:06 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 6 May 2022 17:29:05 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:04 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 05/17] media: mediatek: vcodec: set each plane bytesused in buf prepare Date: Fri, 6 May 2022 17:28:43 +0800 Message-ID: <20220506092855.22940-6-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" call vb2_set_plane_payload to set each plane bytesused in buf prepare, need not to set independently for stateless and statefull architectures. Signed-off-by: Yunfei Dong --- .../platform/mediatek/vcodec/mtk_vcodec_dec.c | 2 ++ .../mediatek/vcodec/mtk_vcodec_dec_stateful.c | 5 ----- .../vcodec/mtk_vcodec_dec_stateless.c | 19 ------------------- 3 files changed, 2 insertions(+), 24 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c index e42d5c17d90e..c1c3f439d7d1 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c @@ -741,6 +741,8 @@ int vb2ops_vdec_buf_prepare(struct vb2_buffer *vb) i, vb2_plane_size(vb, i), q_data->sizeimage[i]); } + if (!V4L2_TYPE_IS_OUTPUT(vb->type)) + vb2_set_plane_payload(vb, i, q_data->sizeimage[i]); } =20 return 0; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful= .c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful.c index 7966c132be8f..e7fd39180123 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful.c @@ -90,11 +90,6 @@ static struct vb2_buffer *get_display_buffer(struct mtk_= vcodec_ctx *ctx) vb =3D &dstbuf->m2m_buf.vb; mutex_lock(&ctx->lock); if (dstbuf->used) { - vb2_set_plane_payload(&vb->vb2_buf, 0, ctx->picinfo.fb_sz[0]); - if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 2) - vb2_set_plane_payload(&vb->vb2_buf, 1, - ctx->picinfo.fb_sz[1]); - mtk_v4l2_debug(2, "[%d]status=3D%x queue id=3D%d to done_list %d", ctx->id, disp_frame_buffer->status, vb->vb2_buf.index, dstbuf->queued_in_vb2); diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateles= s.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c index 5aebf88f997b..4df7b158ec5e 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c @@ -108,23 +108,6 @@ static const struct mtk_codec_framesizes mtk_vdec_fram= esizes[] =3D { =20 #define NUM_SUPPORTED_FRAMESIZE ARRAY_SIZE(mtk_vdec_framesizes) =20 -static void mtk_vdec_stateless_set_dst_payload(struct mtk_vcodec_ctx *ctx, - struct vdec_fb *fb) -{ - struct mtk_video_dec_buf *vdec_frame_buf =3D - container_of(fb, struct mtk_video_dec_buf, frame_buffer); - struct vb2_v4l2_buffer *vb =3D &vdec_frame_buf->m2m_buf.vb; - unsigned int cap_y_size =3D ctx->q_data[MTK_Q_DATA_DST].sizeimage[0]; - - vb2_set_plane_payload(&vb->vb2_buf, 0, cap_y_size); - if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 2) { - unsigned int cap_c_size =3D - ctx->q_data[MTK_Q_DATA_DST].sizeimage[1]; - - vb2_set_plane_payload(&vb->vb2_buf, 1, cap_c_size); - } -} - static struct vdec_fb *vdec_get_cap_buffer(struct mtk_vcodec_ctx *ctx, struct vb2_v4l2_buffer *vb2_v4l2) { @@ -220,8 +203,6 @@ static void mtk_vdec_worker(struct work_struct *work) } } =20 - mtk_vdec_stateless_set_dst_payload(ctx, dst_buf); - v4l2_m2m_buf_done_and_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx, ret ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); =20 --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CC0AC433EF for ; Fri, 6 May 2022 09:29:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1390572AbiEFJde (ORCPT ); Fri, 6 May 2022 05:33:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390566AbiEFJc6 (ORCPT ); Fri, 6 May 2022 05:32:58 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A73C64BF6; Fri, 6 May 2022 02:29:13 -0700 (PDT) X-UUID: d08435e27aa34bdfa8764ebfb74c3d09-20220506 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:da4b1d5b-ece3-4c34-9834-dcff08008b5f,OB:0,LO B:0,IP:0,URL:8,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-12 X-CID-META: VersionHash:faefae9,CLOUDID:f508d4b2-56b5-4c9e-8d83-0070b288eb6a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: d08435e27aa34bdfa8764ebfb74c3d09-20220506 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2115896311; Fri, 06 May 2022 17:29:08 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 6 May 2022 17:29:07 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 6 May 2022 17:29:07 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:05 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 06/17] media: mediatek: vcodec: Refactor get and put capture buffer flow Date: Fri, 6 May 2022 17:28:44 +0800 Message-ID: <20220506092855.22940-7-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For lat and core decode in parallel, need to get capture buffer when core start to decode and put capture buffer to display list when core decode done. Signed-off-by: Yunfei Dong --- .../vcodec/mtk_vcodec_dec_stateless.c | 88 +++++++++++++------ .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 6 +- .../mediatek/vcodec/vdec/vdec_h264_req_if.c | 11 ++- .../platform/mediatek/vcodec/vdec_msg_queue.h | 2 + 4 files changed, 80 insertions(+), 27 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateles= s.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c index 4df7b158ec5e..c61df1f51185 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c @@ -108,20 +108,50 @@ static const struct mtk_codec_framesizes mtk_vdec_fra= mesizes[] =3D { =20 #define NUM_SUPPORTED_FRAMESIZE ARRAY_SIZE(mtk_vdec_framesizes) =20 -static struct vdec_fb *vdec_get_cap_buffer(struct mtk_vcodec_ctx *ctx, - struct vb2_v4l2_buffer *vb2_v4l2) +static void mtk_vdec_stateless_cap_to_disp(struct mtk_vcodec_ctx *ctx, int= error, + struct media_request *src_buf_req) { - struct mtk_video_dec_buf *framebuf =3D - container_of(vb2_v4l2, struct mtk_video_dec_buf, m2m_buf.vb); - struct vdec_fb *pfb =3D &framebuf->frame_buffer; - struct vb2_buffer *dst_buf =3D &vb2_v4l2->vb2_buf; + struct vb2_v4l2_buffer *vb2_dst; + enum vb2_buffer_state state; =20 - pfb->base_y.va =3D NULL; + if (error) + state =3D VB2_BUF_STATE_ERROR; + else + state =3D VB2_BUF_STATE_DONE; + + vb2_dst =3D v4l2_m2m_dst_buf_remove(ctx->m2m_ctx); + v4l2_m2m_buf_done(vb2_dst, state); + + mtk_v4l2_debug(2, "free frame buffer id:%d to done list", + vb2_dst->vb2_buf.index); + + if (src_buf_req) + v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl); +} + +static struct vdec_fb *vdec_get_cap_buffer(struct mtk_vcodec_ctx *ctx) +{ + struct mtk_video_dec_buf *framebuf; + struct vb2_v4l2_buffer *vb2_v4l2; + struct vb2_buffer *dst_buf; + struct vdec_fb *pfb; + + vb2_v4l2 =3D v4l2_m2m_next_dst_buf(ctx->m2m_ctx); + if (!vb2_v4l2) { + mtk_v4l2_debug(1, "[%d] dst_buf empty!!", ctx->id); + return NULL; + } + + dst_buf =3D &vb2_v4l2->vb2_buf; + framebuf =3D container_of(vb2_v4l2, struct mtk_video_dec_buf, m2m_buf.vb); + + pfb =3D &framebuf->frame_buffer; + pfb->base_y.va =3D vb2_plane_vaddr(dst_buf, 0); pfb->base_y.dma_addr =3D vb2_dma_contig_plane_dma_addr(dst_buf, 0); pfb->base_y.size =3D ctx->q_data[MTK_Q_DATA_DST].sizeimage[0]; =20 if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 2) { - pfb->base_c.va =3D NULL; + pfb->base_c.va =3D vb2_plane_vaddr(dst_buf, 1); pfb->base_c.dma_addr =3D vb2_dma_contig_plane_dma_addr(dst_buf, 1); pfb->base_c.size =3D ctx->q_data[MTK_Q_DATA_DST].sizeimage[1]; @@ -145,12 +175,12 @@ static void mtk_vdec_worker(struct work_struct *work) struct mtk_vcodec_ctx *ctx =3D container_of(work, struct mtk_vcodec_ctx, decode_work); struct mtk_vcodec_dev *dev =3D ctx->dev; - struct vb2_v4l2_buffer *vb2_v4l2_src, *vb2_v4l2_dst; + struct vb2_v4l2_buffer *vb2_v4l2_src; struct vb2_buffer *vb2_src; struct mtk_vcodec_mem *bs_src; struct mtk_video_dec_buf *dec_buf_src; struct media_request *src_buf_req; - struct vdec_fb *dst_buf; + enum vb2_buffer_state state; bool res_chg =3D false; int ret; =20 @@ -161,13 +191,6 @@ static void mtk_vdec_worker(struct work_struct *work) return; } =20 - vb2_v4l2_dst =3D v4l2_m2m_next_dst_buf(ctx->m2m_ctx); - if (!vb2_v4l2_dst) { - v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); - mtk_v4l2_debug(1, "[%d] no available destination buffer", ctx->id); - return; - } - vb2_src =3D &vb2_v4l2_src->vb2_buf; dec_buf_src =3D container_of(vb2_v4l2_src, struct mtk_video_dec_buf, m2m_buf.vb); @@ -176,9 +199,15 @@ static void mtk_vdec_worker(struct work_struct *work) mtk_v4l2_debug(3, "[%d] (%d) id=3D%d, vb=3D%p", ctx->id, vb2_src->vb2_queue->type, vb2_src->index, vb2_src); =20 - bs_src->va =3D NULL; + bs_src->va =3D vb2_plane_vaddr(vb2_src, 0); bs_src->dma_addr =3D vb2_dma_contig_plane_dma_addr(vb2_src, 0); bs_src->size =3D (size_t)vb2_src->planes[0].bytesused; + if (!bs_src->va) { + v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); + mtk_v4l2_err("[%d] id=3D%d source buffer is NULL", ctx->id, + vb2_src->index); + return; + } =20 mtk_v4l2_debug(3, "[%d] Bitstream VA=3D%p DMA=3D%pad Size=3D%zx vb=3D%p", ctx->id, bs_src->va, &bs_src->dma_addr, bs_src->size, vb2_src); @@ -189,9 +218,7 @@ static void mtk_vdec_worker(struct work_struct *work) else mtk_v4l2_err("vb2 buffer media request is NULL"); =20 - dst_buf =3D vdec_get_cap_buffer(ctx, vb2_v4l2_dst); - v4l2_m2m_buf_copy_metadata(vb2_v4l2_src, vb2_v4l2_dst, true); - ret =3D vdec_if_decode(ctx, bs_src, dst_buf, &res_chg); + ret =3D vdec_if_decode(ctx, bs_src, NULL, &res_chg); if (ret) { mtk_v4l2_err(" <=3D=3D=3D[%d], src_buf[%d] sz=3D0x%zx pts=3D%llu vdec_if= _decode() ret=3D%d res_chg=3D%d=3D=3D=3D>", ctx->id, vb2_src->index, bs_src->size, @@ -203,10 +230,17 @@ static void mtk_vdec_worker(struct work_struct *work) } } =20 - v4l2_m2m_buf_done_and_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx, - ret ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); - - v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl); + state =3D ret ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE; + if (!IS_VDEC_LAT_ARCH(dev->vdec_pdata->hw_arch) || + ctx->current_codec =3D=3D V4L2_PIX_FMT_VP8_FRAME || ret) { + v4l2_m2m_buf_done_and_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx, state); + if (src_buf_req) + v4l2_ctrl_request_complete(src_buf_req, &ctx->ctrl_hdl); + } else { + v4l2_m2m_src_buf_remove(ctx->m2m_ctx); + v4l2_m2m_buf_done(vb2_v4l2_src, state); + v4l2_m2m_job_finish(dev->m2m_dev_dec, ctx->m2m_ctx); + } } =20 static void vb2ops_vdec_stateless_buf_queue(struct vb2_buffer *vb) @@ -336,6 +370,8 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata = =3D { .uses_stateless_api =3D true, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, + .get_cap_buffer =3D vdec_get_cap_buffer, .is_subdev_supported =3D false, .hw_arch =3D MTK_VDEC_PURE_SINGLE_CORE, }; @@ -354,6 +390,8 @@ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pdat= a =3D { .uses_stateless_api =3D true, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, + .cap_to_disp =3D mtk_vdec_stateless_cap_to_disp, + .get_cap_buffer =3D vdec_get_cap_buffer, .is_subdev_supported =3D true, .hw_arch =3D MTK_VDEC_LAT_SINGLE_CORE, }; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index 6d27e4d41ede..c06463142182 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -350,7 +350,8 @@ enum mtk_vdec_hw_arch { * @ctrls_setup: init vcodec dec ctrls * @worker: worker to start a decode job * @flush_decoder: function that flushes the decoder - * + * @get_cap_buffer: get capture buffer from capture queue + * @cap_to_disp: put capture buffer to disp list for lat and core arch * @vdec_vb2_ops: struct vb2_ops * * @vdec_formats: supported video decoder formats @@ -372,6 +373,9 @@ struct mtk_vcodec_dec_pdata { int (*ctrls_setup)(struct mtk_vcodec_ctx *ctx); void (*worker)(struct work_struct *work); int (*flush_decoder)(struct mtk_vcodec_ctx *ctx); + struct vdec_fb *(*get_cap_buffer)(struct mtk_vcodec_ctx *ctx); + void (*cap_to_disp)(struct mtk_vcodec_ctx *ctx, int error, + struct media_request *src_buf_req); =20 struct vb2_ops *vdec_vb2_ops; =20 diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_if.c= b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_if.c index 43542de11e9c..27119aa31dd9 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_if.c @@ -670,12 +670,15 @@ static void vdec_h264_slice_deinit(void *h_vdec) } =20 static int vdec_h264_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs, - struct vdec_fb *fb, bool *res_chg) + struct vdec_fb *unused, bool *res_chg) { struct vdec_h264_slice_inst *inst =3D h_vdec; const struct v4l2_ctrl_h264_decode_params *dec_params =3D get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); struct vdec_vpu_inst *vpu =3D &inst->vpu; + struct mtk_video_dec_buf *src_buf_info; + struct mtk_video_dec_buf *dst_buf_info; + struct vdec_fb *fb; u32 data[2]; u64 y_fb_dma; u64 c_fb_dma; @@ -685,6 +688,10 @@ static int vdec_h264_slice_decode(void *h_vdec, struct= mtk_vcodec_mem *bs, if (!bs) return vpu_dec_reset(vpu); =20 + fb =3D inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx); + src_buf_info =3D container_of(bs, struct mtk_video_dec_buf, bs_buffer); + dst_buf_info =3D container_of(fb, struct mtk_video_dec_buf, frame_buffer); + y_fb_dma =3D fb ? (u64)fb->base_y.dma_addr : 0; c_fb_dma =3D fb ? (u64)fb->base_c.dma_addr : 0; =20 @@ -696,6 +703,8 @@ static int vdec_h264_slice_decode(void *h_vdec, struct = mtk_vcodec_mem *bs, inst->vsi_ctx.dec.c_fb_dma =3D c_fb_dma; inst->vsi_ctx.dec.vdec_fb_va =3D (u64)(uintptr_t)fb; =20 + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, + &dst_buf_info->m2m_buf.vb, true); get_vdec_decode_parameters(inst); data[0] =3D bs->size; /* diff --git a/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.h b/driv= ers/media/platform/mediatek/vcodec/vdec_msg_queue.h index b6ba66d3e026..c43d427f5f54 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.h +++ b/drivers/media/platform/mediatek/vcodec/vdec_msg_queue.h @@ -43,6 +43,7 @@ struct vdec_msg_queue_ctx { * @wdma_err_addr: wdma error address used for lat hardware * @slice_bc_addr: slice bc address used for lat hardware * @ts_info: need to set timestamp from output to capture + * @src_buf_req: output buffer media request object * * @private_data: shared information used to lat and core hardware * @ctx: mtk vcodec context information @@ -54,6 +55,7 @@ struct vdec_lat_buf { struct mtk_vcodec_mem wdma_err_addr; struct mtk_vcodec_mem slice_bc_addr; struct vb2_v4l2_buffer ts_info; + struct media_request *src_buf_req; =20 void *private_data; struct mtk_vcodec_ctx *ctx; --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D162DC433F5 for ; Fri, 6 May 2022 09:31:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1390674AbiEFJeD (ORCPT ); Fri, 6 May 2022 05:34:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390602AbiEFJde (ORCPT ); Fri, 6 May 2022 05:33:34 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D6416541E; Fri, 6 May 2022 02:29:17 -0700 (PDT) X-UUID: 6db572ecc3b24c4c990b3ac77f375bc8-20220506 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:fbaac1ab-ef2b-491b-8909-602d98ac5676,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:eb5f7416-2e53-443e-b81a-655c13977218,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 6db572ecc3b24c4c990b3ac77f375bc8-20220506 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1363247103; Fri, 06 May 2022 17:29:10 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 6 May 2022 17:29:09 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:07 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , Steve Cho , , , , , , Subject: [PATCH v11, 07/17] media: mediatek: vcodec: Refactor supported vdec formats and framesizes Date: Fri, 6 May 2022 17:28:45 +0800 Message-ID: <20220506092855.22940-8-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Supported output and capture format types for mt8192 are different with mt8183. Redefine parameters to store them. Signed-off-by: Yunfei Dong Reviewed-by: AngeloGioacchino Del Regno --- .../media/platform/mediatek/vcodec/mtk_vcodec_dec.c | 8 ++++---- .../mediatek/vcodec/mtk_vcodec_dec_stateful.c | 13 ++++++++----- .../mediatek/vcodec/mtk_vcodec_dec_stateless.c | 13 +++++++------ .../media/platform/mediatek/vcodec/mtk_vcodec_drv.h | 13 +++++++++++-- 4 files changed, 30 insertions(+), 17 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c index c1c3f439d7d1..1fb49a779c5d 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c @@ -26,7 +26,7 @@ mtk_vdec_find_format(struct v4l2_format *f, const struct mtk_video_fmt *fmt; unsigned int k; =20 - for (k =3D 0; k < dec_pdata->num_formats; k++) { + for (k =3D 0; k < *dec_pdata->num_formats; k++) { fmt =3D &dec_pdata->vdec_formats[k]; if (fmt->fourcc =3D=3D f->fmt.pix_mp.pixelformat) return fmt; @@ -531,7 +531,7 @@ static int vidioc_enum_framesizes(struct file *file, vo= id *priv, if (fsize->index !=3D 0) return -EINVAL; =20 - for (i =3D 0; i < dec_pdata->num_framesizes; ++i) { + for (i =3D 0; i < *dec_pdata->num_framesizes; ++i) { if (fsize->pixel_format !=3D dec_pdata->vdec_framesizes[i].fourcc) continue; =20 @@ -563,7 +563,7 @@ static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, void= *priv, const struct mtk_video_fmt *fmt; int i, j =3D 0; =20 - for (i =3D 0; i < dec_pdata->num_formats; i++) { + for (i =3D 0; i < *dec_pdata->num_formats; i++) { if (output_queue && dec_pdata->vdec_formats[i].type !=3D MTK_FMT_DEC) continue; @@ -576,7 +576,7 @@ static int vidioc_enum_fmt(struct v4l2_fmtdesc *f, void= *priv, ++j; } =20 - if (i =3D=3D dec_pdata->num_formats) + if (i =3D=3D *dec_pdata->num_formats) return -EINVAL; =20 fmt =3D &dec_pdata->vdec_formats[i]; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful= .c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful.c index e7fd39180123..9c7e6145cebb 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateful.c @@ -37,7 +37,9 @@ static const struct mtk_video_fmt mtk_video_formats[] =3D= { }, }; =20 -#define NUM_FORMATS ARRAY_SIZE(mtk_video_formats) +static const unsigned int num_supported_formats =3D + ARRAY_SIZE(mtk_video_formats); + #define DEFAULT_OUT_FMT_IDX 0 #define DEFAULT_CAP_FMT_IDX 3 =20 @@ -59,7 +61,8 @@ static const struct mtk_codec_framesizes mtk_vdec_framesi= zes[] =3D { }, }; =20 -#define NUM_SUPPORTED_FRAMESIZE ARRAY_SIZE(mtk_vdec_framesizes) +static const unsigned int num_supported_framesize =3D + ARRAY_SIZE(mtk_vdec_framesizes); =20 /* * This function tries to clean all display buffers, the buffers will retu= rn @@ -230,7 +233,7 @@ static void mtk_vdec_update_fmt(struct mtk_vcodec_ctx *= ctx, unsigned int k; =20 dst_q_data =3D &ctx->q_data[MTK_Q_DATA_DST]; - for (k =3D 0; k < NUM_FORMATS; k++) { + for (k =3D 0; k < num_supported_formats; k++) { fmt =3D &mtk_video_formats[k]; if (fmt->fourcc =3D=3D pixelformat) { mtk_v4l2_debug(1, "Update cap fourcc(%d -> %d)", @@ -612,11 +615,11 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8173_pdata= =3D { .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_frame_vb2_ops, .vdec_formats =3D mtk_video_formats, - .num_formats =3D NUM_FORMATS, + .num_formats =3D &num_supported_formats, .default_out_fmt =3D &mtk_video_formats[DEFAULT_OUT_FMT_IDX], .default_cap_fmt =3D &mtk_video_formats[DEFAULT_CAP_FMT_IDX], .vdec_framesizes =3D mtk_vdec_framesizes, - .num_framesizes =3D NUM_SUPPORTED_FRAMESIZE, + .num_framesizes =3D &num_supported_framesize, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, .is_subdev_supported =3D false, diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateles= s.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c index c61df1f51185..0034b2ee9259 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c @@ -94,7 +94,8 @@ static const struct mtk_video_fmt mtk_video_formats[] =3D= { }, }; =20 -#define NUM_FORMATS ARRAY_SIZE(mtk_video_formats) +static const unsigned int num_supported_formats =3D ARRAY_SIZE(mtk_video_f= ormats); + #define DEFAULT_OUT_FMT_IDX 0 #define DEFAULT_CAP_FMT_IDX 1 =20 @@ -106,7 +107,7 @@ static const struct mtk_codec_framesizes mtk_vdec_frame= sizes[] =3D { }, }; =20 -#define NUM_SUPPORTED_FRAMESIZE ARRAY_SIZE(mtk_vdec_framesizes) +static const unsigned int num_supported_framesize =3D ARRAY_SIZE(mtk_vdec_= framesizes); =20 static void mtk_vdec_stateless_cap_to_disp(struct mtk_vcodec_ctx *ctx, int= error, struct media_request *src_buf_req) @@ -362,11 +363,11 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata= =3D { .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, .vdec_formats =3D mtk_video_formats, - .num_formats =3D NUM_FORMATS, + .num_formats =3D &num_supported_formats, .default_out_fmt =3D &mtk_video_formats[DEFAULT_OUT_FMT_IDX], .default_cap_fmt =3D &mtk_video_formats[DEFAULT_CAP_FMT_IDX], .vdec_framesizes =3D mtk_vdec_framesizes, - .num_framesizes =3D NUM_SUPPORTED_FRAMESIZE, + .num_framesizes =3D &num_supported_framesize, .uses_stateless_api =3D true, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, @@ -382,11 +383,11 @@ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pd= ata =3D { .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, .vdec_formats =3D mtk_video_formats, - .num_formats =3D NUM_FORMATS, + .num_formats =3D &num_supported_formats, .default_out_fmt =3D &mtk_video_formats[DEFAULT_OUT_FMT_IDX], .default_cap_fmt =3D &mtk_video_formats[DEFAULT_CAP_FMT_IDX], .vdec_framesizes =3D mtk_vdec_framesizes, - .num_framesizes =3D NUM_SUPPORTED_FRAMESIZE, + .num_framesizes =3D &num_supported_framesize, .uses_stateless_api =3D true, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index c06463142182..d74a9e0e74fe 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -344,6 +344,15 @@ enum mtk_vdec_hw_arch { MTK_VDEC_LAT_SINGLE_CORE, }; =20 +/* + * struct mtk_vdec_format_types - Structure used to get supported + * format types according to decoder capability + */ +enum mtk_vdec_format_types { + MTK_VDEC_FORMAT_MM21 =3D 0x20, + MTK_VDEC_FORMAT_H264_SLICE =3D 0x100, +}; + /** * struct mtk_vcodec_dec_pdata - compatible data for each IC * @init_vdec_params: init vdec params @@ -380,12 +389,12 @@ struct mtk_vcodec_dec_pdata { struct vb2_ops *vdec_vb2_ops; =20 const struct mtk_video_fmt *vdec_formats; - const int num_formats; + const int *num_formats; const struct mtk_video_fmt *default_out_fmt; const struct mtk_video_fmt *default_cap_fmt; =20 const struct mtk_codec_framesizes *vdec_framesizes; - const int num_framesizes; + const int *num_framesizes; =20 enum mtk_vdec_hw_arch hw_arch; =20 --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A95CBC433EF for ; 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charset="utf-8" Getting supported output and capture queue format types according to decoder capability. Signed-off-by: Yunfei Dong Reviewed-by: AngeloGioacchino Del Regno --- .../vcodec/mtk_vcodec_dec_stateless.c | 118 +++++++++++++----- 1 file changed, 84 insertions(+), 34 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateles= s.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c index 0034b2ee9259..5101322f4fe9 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c @@ -81,34 +81,23 @@ static const struct mtk_stateless_control mtk_stateless= _controls[] =3D { =20 #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls) =20 -static const struct mtk_video_fmt mtk_video_formats[] =3D { - { - .fourcc =3D V4L2_PIX_FMT_H264_SLICE, - .type =3D MTK_FMT_DEC, - .num_planes =3D 1, - }, - { - .fourcc =3D V4L2_PIX_FMT_MM21, - .type =3D MTK_FMT_FRAME, - .num_planes =3D 2, - }, -}; - -static const unsigned int num_supported_formats =3D ARRAY_SIZE(mtk_video_f= ormats); - -#define DEFAULT_OUT_FMT_IDX 0 -#define DEFAULT_CAP_FMT_IDX 1 - -static const struct mtk_codec_framesizes mtk_vdec_framesizes[] =3D { - { - .fourcc =3D V4L2_PIX_FMT_H264_SLICE, - .stepwise =3D { MTK_VDEC_MIN_W, MTK_VDEC_MAX_W, 16, - MTK_VDEC_MIN_H, MTK_VDEC_MAX_H, 16 }, - }, +static struct mtk_video_fmt mtk_video_formats[2]; +static struct mtk_codec_framesizes mtk_vdec_framesizes[1]; + +static struct mtk_video_fmt default_out_format; +static struct mtk_video_fmt default_cap_format; +static unsigned int num_formats; +static unsigned int num_framesizes; + +static struct v4l2_frmsize_stepwise stepwise_fhd =3D { + .min_width =3D MTK_VDEC_MIN_W, + .max_width =3D MTK_VDEC_MAX_W, + .step_width =3D 16, + .min_height =3D MTK_VDEC_MIN_H, + .max_height =3D MTK_VDEC_MAX_H, + .step_height =3D 16 }; =20 -static const unsigned int num_supported_framesize =3D ARRAY_SIZE(mtk_vdec_= framesizes); - static void mtk_vdec_stateless_cap_to_disp(struct mtk_vcodec_ctx *ctx, int= error, struct media_request *src_buf_req) { @@ -323,6 +312,62 @@ const struct media_device_ops mtk_vcodec_media_ops =3D= { .req_queue =3D v4l2_m2m_request_queue, }; =20 +static void mtk_vcodec_add_formats(unsigned int fourcc, + struct mtk_vcodec_ctx *ctx) +{ + struct mtk_vcodec_dev *dev =3D ctx->dev; + const struct mtk_vcodec_dec_pdata *pdata =3D dev->vdec_pdata; + int count_formats =3D *pdata->num_formats; + int count_framesizes =3D *pdata->num_framesizes; + + switch (fourcc) { + case V4L2_PIX_FMT_H264_SLICE: + mtk_video_formats[count_formats].fourcc =3D fourcc; + mtk_video_formats[count_formats].type =3D MTK_FMT_DEC; + mtk_video_formats[count_formats].num_planes =3D 1; + + mtk_vdec_framesizes[count_framesizes].fourcc =3D fourcc; + mtk_vdec_framesizes[count_framesizes].stepwise =3D stepwise_fhd; + num_framesizes++; + break; + case V4L2_PIX_FMT_MM21: + mtk_video_formats[count_formats].fourcc =3D fourcc; + mtk_video_formats[count_formats].type =3D MTK_FMT_FRAME; + mtk_video_formats[count_formats].num_planes =3D 2; + break; + default: + mtk_v4l2_err("Can not add unsupported format type"); + return; + } + + num_formats++; + mtk_v4l2_debug(3, "num_formats: %d num_frames:%d dec_capability: 0x%x", + count_formats, count_framesizes, ctx->dev->dec_capability); +} + +static void mtk_vcodec_get_supported_formats(struct mtk_vcodec_ctx *ctx) +{ + int cap_format_count =3D 0, out_format_count =3D 0; + + if (num_formats && num_framesizes) + return; + + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MM21) { + mtk_vcodec_add_formats(V4L2_PIX_FMT_MM21, ctx); + cap_format_count++; + } + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_H264_SLICE) { + mtk_vcodec_add_formats(V4L2_PIX_FMT_H264_SLICE, ctx); + out_format_count++; + } + + if (cap_format_count) + default_cap_format =3D mtk_video_formats[cap_format_count - 1]; + if (out_format_count) + default_out_format =3D + mtk_video_formats[cap_format_count + out_format_count - 1]; +} + static void mtk_init_vdec_params(struct mtk_vcodec_ctx *ctx) { struct vb2_queue *src_vq; @@ -330,6 +375,11 @@ static void mtk_init_vdec_params(struct mtk_vcodec_ctx= *ctx) src_vq =3D v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); =20 + if (!ctx->dev->vdec_pdata->is_subdev_supported) + ctx->dev->dec_capability |=3D + MTK_VDEC_FORMAT_H264_SLICE | MTK_VDEC_FORMAT_MM21; + mtk_vcodec_get_supported_formats(ctx); + /* Support request api for output plane */ src_vq->supports_requests =3D true; src_vq->requires_requests =3D true; @@ -363,11 +413,11 @@ const struct mtk_vcodec_dec_pdata mtk_vdec_8183_pdata= =3D { .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, .vdec_formats =3D mtk_video_formats, - .num_formats =3D &num_supported_formats, - .default_out_fmt =3D &mtk_video_formats[DEFAULT_OUT_FMT_IDX], - .default_cap_fmt =3D &mtk_video_formats[DEFAULT_CAP_FMT_IDX], + .num_formats =3D &num_formats, + .default_out_fmt =3D &default_out_format, + .default_cap_fmt =3D &default_cap_format, .vdec_framesizes =3D mtk_vdec_framesizes, - .num_framesizes =3D &num_supported_framesize, + .num_framesizes =3D &num_framesizes, .uses_stateless_api =3D true, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, @@ -383,11 +433,11 @@ const struct mtk_vcodec_dec_pdata mtk_lat_sig_core_pd= ata =3D { .ctrls_setup =3D mtk_vcodec_dec_ctrls_setup, .vdec_vb2_ops =3D &mtk_vdec_request_vb2_ops, .vdec_formats =3D mtk_video_formats, - .num_formats =3D &num_supported_formats, - .default_out_fmt =3D &mtk_video_formats[DEFAULT_OUT_FMT_IDX], - .default_cap_fmt =3D &mtk_video_formats[DEFAULT_CAP_FMT_IDX], + .num_formats =3D &num_formats, + .default_out_fmt =3D &default_out_format, + .default_cap_fmt =3D &default_cap_format, .vdec_framesizes =3D mtk_vdec_framesizes, - .num_framesizes =3D &num_supported_framesize, + .num_framesizes =3D &num_framesizes, .uses_stateless_api =3D true, .worker =3D mtk_vdec_worker, .flush_decoder =3D mtk_vdec_flush_decoder, --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 998C0C433EF for ; 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Fri, 06 May 2022 17:29:13 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 6 May 2022 17:29:13 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 6 May 2022 17:29:12 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:11 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 09/17] media: mediatek: vcodec: Add format to support MT21C Date: Fri, 6 May 2022 17:28:47 +0800 Message-ID: <20220506092855.22940-10-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Needs to use mediatek compressed mode for mt8192 decoder. Signed-off-by: Yunfei Dong Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c | 7 ++++++- drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateles= s.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c index 5101322f4fe9..d5c69f94d28e 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c @@ -81,7 +81,7 @@ static const struct mtk_stateless_control mtk_stateless_c= ontrols[] =3D { =20 #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls) =20 -static struct mtk_video_fmt mtk_video_formats[2]; +static struct mtk_video_fmt mtk_video_formats[3]; static struct mtk_codec_framesizes mtk_vdec_framesizes[1]; =20 static struct mtk_video_fmt default_out_format; @@ -331,6 +331,7 @@ static void mtk_vcodec_add_formats(unsigned int fourcc, num_framesizes++; break; case V4L2_PIX_FMT_MM21: + case V4L2_PIX_FMT_MT21C: mtk_video_formats[count_formats].fourcc =3D fourcc; mtk_video_formats[count_formats].type =3D MTK_FMT_FRAME; mtk_video_formats[count_formats].num_planes =3D 2; @@ -356,6 +357,10 @@ static void mtk_vcodec_get_supported_formats(struct mt= k_vcodec_ctx *ctx) mtk_vcodec_add_formats(V4L2_PIX_FMT_MM21, ctx); cap_format_count++; } + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_MT21C) { + mtk_vcodec_add_formats(V4L2_PIX_FMT_MT21C, ctx); + cap_format_count++; + } if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_H264_SLICE) { mtk_vcodec_add_formats(V4L2_PIX_FMT_H264_SLICE, ctx); out_format_count++; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index d74a9e0e74fe..75a1c6df6594 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -350,6 +350,7 @@ enum mtk_vdec_hw_arch { */ enum mtk_vdec_format_types { MTK_VDEC_FORMAT_MM21 =3D 0x20, + MTK_VDEC_FORMAT_MT21C =3D 0x40, MTK_VDEC_FORMAT_H264_SLICE =3D 0x100, }; =20 --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F073CC43217 for ; Fri, 6 May 2022 09:31:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1390778AbiEFJeL (ORCPT ); Fri, 6 May 2022 05:34:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390605AbiEFJde (ORCPT ); Fri, 6 May 2022 05:33:34 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 472CD66219; Fri, 6 May 2022 02:29:19 -0700 (PDT) X-UUID: 8955e15b644c4dcc99f26396c56b28dd-20220506 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:d4146c87-d8b1-4fc7-9202-35d9e463e93b,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:3,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:3 X-CID-INFO: VERSION:1.1.4,REQID:d4146c87-d8b1-4fc7-9202-35d9e463e93b,OB:0,LOB: 0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:3,FILE:0,RULE:Release_Ham,ACTION :release,TS:3 X-CID-META: VersionHash:faefae9,CLOUDID:59617416-2e53-443e-b81a-655c13977218,C OID:IGNORED,Recheck:0,SF:28|100|17|19|48|101|20,TC:nil,Content:0,EDM:-3,Fi le:nil,QS:0,BEC:nil X-UUID: 8955e15b644c4dcc99f26396c56b28dd-20220506 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1671895477; Fri, 06 May 2022 17:29:15 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 6 May 2022 17:29:14 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:12 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 10/17] media: mediatek: vcodec: disable vp8 4K capability Date: Fri, 6 May 2022 17:28:48 +0800 Message-ID: <20220506092855.22940-11-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" For vp8 not support 4K, need to disable it. Signed-off-by: Yunfei Dong --- drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c index 1fb49a779c5d..dab6acb3158c 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c @@ -446,7 +446,8 @@ static int vidioc_vdec_s_fmt(struct file *file, void *p= riv, if (fmt =3D=3D NULL) return -EINVAL; =20 - if (!(ctx->dev->dec_capability & VCODEC_CAPABILITY_4K_DISABLED)) { + if (!(ctx->dev->dec_capability & VCODEC_CAPABILITY_4K_DISABLED) && + fmt->fourcc !=3D V4L2_PIX_FMT_VP8_FRAME) { mtk_v4l2_debug(3, "4K is enabled"); ctx->max_width =3D VCODEC_DEC_4K_CODED_WIDTH; ctx->max_height =3D VCODEC_DEC_4K_CODED_HEIGHT; --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34961C433FE for ; Fri, 6 May 2022 09:31:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345717AbiEFJe4 (ORCPT ); Fri, 6 May 2022 05:34:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390612AbiEFJdg (ORCPT ); Fri, 6 May 2022 05:33:36 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22ACB674E9; Fri, 6 May 2022 02:29:22 -0700 (PDT) X-UUID: 77f838065e8b43a6870a54dd7ddb2dbb-20220506 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:aaada35a-3c05-4717-8b3f-7cb99412e659,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9,CLOUDID:86627416-2e53-443e-b81a-655c13977218,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 77f838065e8b43a6870a54dd7ddb2dbb-20220506 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1129063676; Fri, 06 May 2022 17:29:17 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 6 May 2022 17:29:16 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 6 May 2022 17:29:15 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:14 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 11/17] media: mediatek: vcodec: Fix v4l2-compliance fail Date: Fri, 6 May 2022 17:28:49 +0800 Message-ID: <20220506092855.22940-12-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Need to use default pic info when get pic info fail. Signed-off-by: Yunfei Dong Reviewed-by: Steve Cho --- drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c index dab6acb3158c..0d9007339faf 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c @@ -485,11 +485,14 @@ static int vidioc_vdec_s_fmt(struct file *file, void = *priv, ctx->picinfo.pic_w =3D pix_mp->width; ctx->picinfo.pic_h =3D pix_mp->height; =20 + /* + * If get pic info fail, need to use the default pic info params, or + * v4l2-compliance will fail + */ ret =3D vdec_if_get_param(ctx, GET_PARAM_PIC_INFO, &ctx->picinfo); if (ret) { mtk_v4l2_err("[%d]Error!! Get GET_PARAM_PICTURE_INFO Fail", ctx->id); - return -EINVAL; } =20 ctx->last_decoded_picinfo =3D ctx->picinfo; --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEBCAC433F5 for ; Fri, 6 May 2022 09:31:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1390600AbiEFJfc (ORCPT ); Fri, 6 May 2022 05:35:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390621AbiEFJdg (ORCPT ); Fri, 6 May 2022 05:33:36 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30FB767D03; Fri, 6 May 2022 02:29:24 -0700 (PDT) X-UUID: c007c45b05c84c60ac4cbd6369f2868a-20220506 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:fce8fda6-1581-47f0-a0eb-02e3fb7f5dd5,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:85627416-2e53-443e-b81a-655c13977218,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: c007c45b05c84c60ac4cbd6369f2868a-20220506 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1672336386; Fri, 06 May 2022 17:29:19 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 6 May 2022 17:29:18 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 6 May 2022 17:29:17 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:15 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 12/17] media: mediatek: vcodec: record capture queue format type Date: Fri, 6 May 2022 17:28:50 +0800 Message-ID: <20220506092855.22940-13-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The capture queue format type may be differ depending on platform: for stateless decoder drivers, we need to calculate the capture buffer size according to the capture queue format type in SCP. As a preparation for introducing drivers for stateless decoding, save the current capture queue type on a per vcodec context basis. Signed-off-by: Yunfei Dong Reviewed-by: AngeloGioacchino Del Regno --- drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c | 2 ++ drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c index 0d9007339faf..3859e4c651c6 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec.c @@ -475,6 +475,8 @@ static int vidioc_vdec_s_fmt(struct file *file, void *p= riv, } ctx->state =3D MTK_STATE_INIT; } + } else { + ctx->capture_fourcc =3D fmt->fourcc; } =20 /* diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index 75a1c6df6594..c047f421843b 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -274,6 +274,7 @@ struct vdec_pic_info { * to be used with encoder and stateful decoder. * @is_flushing: set to true if flushing is in progress. * @current_codec: current set input codec, in V4L2 pixel format + * @capture_fourcc: capture queue type in V4L2 pixel format * * @colorspace: enum v4l2_colorspace; supplemental to pixelformat * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding @@ -321,6 +322,7 @@ struct mtk_vcodec_ctx { bool is_flushing; =20 u32 current_codec; + u32 capture_fourcc; =20 enum v4l2_colorspace colorspace; enum v4l2_ycbcr_encoding ycbcr_enc; --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00FD7C433F5 for ; Fri, 6 May 2022 09:31:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351893AbiEFJfV (ORCPT ); Fri, 6 May 2022 05:35:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390600AbiEFJdq (ORCPT ); Fri, 6 May 2022 05:33:46 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3681B689AB; Fri, 6 May 2022 02:29:25 -0700 (PDT) X-UUID: ec42e1b85fa946b3b53c5e3bbe77af42-20220506 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:ad70bf77-359c-42a5-8cfc-81dc9323ccb7,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-20 X-CID-META: VersionHash:faefae9,CLOUDID:7a0dd4b2-56b5-4c9e-8d83-0070b288eb6a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: ec42e1b85fa946b3b53c5e3bbe77af42-20220506 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 346149370; Fri, 06 May 2022 17:29:20 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 6 May 2022 17:29:19 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 6 May 2022 17:29:19 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:17 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 13/17] media: mediatek: vcodec: Extract H264 common code Date: Fri, 6 May 2022 17:28:51 +0800 Message-ID: <20220506092855.22940-14-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Mt8192 can use some of common code with mt8183. Moves them to a new file in order to reuse. Signed-off-by: Yunfei Dong Reviewed-by: Nicolas Dufresne --- .../media/platform/mediatek/vcodec/Makefile | 1 + .../vcodec/vdec/vdec_h264_req_common.c | 310 +++++++++++++ .../vcodec/vdec/vdec_h264_req_common.h | 274 +++++++++++ .../mediatek/vcodec/vdec/vdec_h264_req_if.c | 427 ++---------------- 4 files changed, 629 insertions(+), 383 deletions(-) create mode 100644 drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_r= eq_common.c create mode 100644 drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_r= eq_common.h diff --git a/drivers/media/platform/mediatek/vcodec/Makefile b/drivers/medi= a/platform/mediatek/vcodec/Makefile index 359619653a0e..3f41d748eee5 100644 --- a/drivers/media/platform/mediatek/vcodec/Makefile +++ b/drivers/media/platform/mediatek/vcodec/Makefile @@ -9,6 +9,7 @@ mtk-vcodec-dec-y :=3D vdec/vdec_h264_if.o \ vdec/vdec_vp8_if.o \ vdec/vdec_vp9_if.o \ vdec/vdec_h264_req_if.o \ + vdec/vdec_h264_req_common.o \ mtk_vcodec_dec_drv.o \ vdec_drv_if.o \ vdec_vpu_if.o \ diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_comm= on.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_common.c new file mode 100644 index 000000000000..bd0a486c00b3 --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_common.c @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Yunfei Dong + */ + +#include "vdec_h264_req_common.h" + +/* get used parameters for sps/pps */ +#define GET_MTK_VDEC_FLAG(cond, flag) \ + { dst_param->cond =3D ((src_param->flags & flag) ? (1) : (0)); } +#define GET_MTK_VDEC_PARAM(param) \ + { dst_param->param =3D src_param->param; } + +/* + * The firmware expects unused reflist entries to have the value 0x20. + */ +void mtk_vdec_h264_fixup_ref_list(u8 *ref_list, size_t num_valid) +{ + memset_io((void __iomem *)&ref_list[num_valid], 0x20, 32 - num_valid); +} + +void *mtk_vdec_h264_get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id) +{ + struct v4l2_ctrl *ctrl =3D v4l2_ctrl_find(&ctx->ctrl_hdl, id); + + if (!ctrl) + return ERR_PTR(-EINVAL); + + return ctrl->p_cur.p; +} + +void mtk_vdec_h264_fill_dpb_info(struct mtk_vcodec_ctx *ctx, + struct slice_api_h264_decode_param *decode_params, + struct mtk_h264_dpb_info *h264_dpb_info) +{ + const struct slice_h264_dpb_entry *dpb; + struct vb2_queue *vq; + struct vb2_buffer *vb; + struct vb2_v4l2_buffer *vb2_v4l2; + int index, vb2_index; + + vq =3D v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + + for (index =3D 0; index < V4L2_H264_NUM_DPB_ENTRIES; index++) { + dpb =3D &decode_params->dpb[index]; + if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) { + h264_dpb_info[index].reference_flag =3D 0; + continue; + } + + vb2_index =3D vb2_find_timestamp(vq, dpb->reference_ts, 0); + if (vb2_index < 0) { + dev_err(&ctx->dev->plat_dev->dev, + "Reference invalid: dpb_index(%d) reference_ts(%lld)", + index, dpb->reference_ts); + continue; + } + + /* 1 for short term reference, 2 for long term reference */ + if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)) + h264_dpb_info[index].reference_flag =3D 1; + else + h264_dpb_info[index].reference_flag =3D 2; + + vb =3D vq->bufs[vb2_index]; + vb2_v4l2 =3D container_of(vb, struct vb2_v4l2_buffer, vb2_buf); + h264_dpb_info[index].field =3D vb2_v4l2->field; + + h264_dpb_info[index].y_dma_addr =3D + vb2_dma_contig_plane_dma_addr(vb, 0); + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 2) + h264_dpb_info[index].c_dma_addr =3D + vb2_dma_contig_plane_dma_addr(vb, 1); + else + h264_dpb_info[index].c_dma_addr =3D + h264_dpb_info[index].y_dma_addr + + ctx->picinfo.fb_sz[0]; + } +} + +void mtk_vdec_h264_copy_sps_params(struct mtk_h264_sps_param *dst_param, + const struct v4l2_ctrl_h264_sps *src_param) +{ + GET_MTK_VDEC_PARAM(chroma_format_idc); + GET_MTK_VDEC_PARAM(bit_depth_luma_minus8); + GET_MTK_VDEC_PARAM(bit_depth_chroma_minus8); + GET_MTK_VDEC_PARAM(log2_max_frame_num_minus4); + GET_MTK_VDEC_PARAM(pic_order_cnt_type); + GET_MTK_VDEC_PARAM(log2_max_pic_order_cnt_lsb_minus4); + GET_MTK_VDEC_PARAM(max_num_ref_frames); + GET_MTK_VDEC_PARAM(pic_width_in_mbs_minus1); + GET_MTK_VDEC_PARAM(pic_height_in_map_units_minus1); + + GET_MTK_VDEC_FLAG(separate_colour_plane_flag, + V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE); + GET_MTK_VDEC_FLAG(qpprime_y_zero_transform_bypass_flag, + V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS); + GET_MTK_VDEC_FLAG(delta_pic_order_always_zero_flag, + V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO); + GET_MTK_VDEC_FLAG(frame_mbs_only_flag, + V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY); + GET_MTK_VDEC_FLAG(mb_adaptive_frame_field_flag, + V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); + GET_MTK_VDEC_FLAG(direct_8x8_inference_flag, + V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE); +} + +void mtk_vdec_h264_copy_pps_params(struct mtk_h264_pps_param *dst_param, + const struct v4l2_ctrl_h264_pps *src_param) +{ + GET_MTK_VDEC_PARAM(num_ref_idx_l0_default_active_minus1); + GET_MTK_VDEC_PARAM(num_ref_idx_l1_default_active_minus1); + GET_MTK_VDEC_PARAM(weighted_bipred_idc); + GET_MTK_VDEC_PARAM(pic_init_qp_minus26); + GET_MTK_VDEC_PARAM(chroma_qp_index_offset); + GET_MTK_VDEC_PARAM(second_chroma_qp_index_offset); + + GET_MTK_VDEC_FLAG(entropy_coding_mode_flag, + V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); + GET_MTK_VDEC_FLAG(pic_order_present_flag, + V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); + GET_MTK_VDEC_FLAG(weighted_pred_flag, + V4L2_H264_PPS_FLAG_WEIGHTED_PRED); + GET_MTK_VDEC_FLAG(deblocking_filter_control_present_flag, + V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); + GET_MTK_VDEC_FLAG(constrained_intra_pred_flag, + V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED); + GET_MTK_VDEC_FLAG(redundant_pic_cnt_present_flag, + V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT); + GET_MTK_VDEC_FLAG(transform_8x8_mode_flag, + V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE); + GET_MTK_VDEC_FLAG(scaling_matrix_present_flag, + V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT); +} + +void mtk_vdec_h264_copy_slice_hd_params(struct mtk_h264_slice_hd_param *ds= t_param, + const struct v4l2_ctrl_h264_slice_params *src_param, + const struct v4l2_ctrl_h264_decode_params *dec_param) +{ + int temp; + + GET_MTK_VDEC_PARAM(first_mb_in_slice); + GET_MTK_VDEC_PARAM(slice_type); + GET_MTK_VDEC_PARAM(cabac_init_idc); + GET_MTK_VDEC_PARAM(slice_qp_delta); + GET_MTK_VDEC_PARAM(disable_deblocking_filter_idc); + GET_MTK_VDEC_PARAM(slice_alpha_c0_offset_div2); + GET_MTK_VDEC_PARAM(slice_beta_offset_div2); + GET_MTK_VDEC_PARAM(num_ref_idx_l0_active_minus1); + GET_MTK_VDEC_PARAM(num_ref_idx_l1_active_minus1); + + dst_param->frame_num =3D dec_param->frame_num; + dst_param->pic_order_cnt_lsb =3D dec_param->pic_order_cnt_lsb; + + dst_param->delta_pic_order_cnt_bottom =3D + dec_param->delta_pic_order_cnt_bottom; + dst_param->delta_pic_order_cnt0 =3D + dec_param->delta_pic_order_cnt0; + dst_param->delta_pic_order_cnt1 =3D + dec_param->delta_pic_order_cnt1; + + temp =3D dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC; + dst_param->field_pic_flag =3D temp ? 1 : 0; + + temp =3D dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD; + dst_param->bottom_field_flag =3D temp ? 1 : 0; + + GET_MTK_VDEC_FLAG(direct_spatial_mv_pred_flag, + V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED); +} + +void mtk_vdec_h264_copy_scaling_matrix(struct slice_api_h264_scaling_matri= x *dst_matrix, + const struct v4l2_ctrl_h264_scaling_matrix *src_matrix) +{ + memcpy_toio((void __iomem *)dst_matrix->scaling_list_4x4, src_matrix->sca= ling_list_4x4, + sizeof(dst_matrix->scaling_list_4x4)); + + memcpy_toio((void __iomem *)dst_matrix->scaling_list_8x8, src_matrix->sca= ling_list_8x8, + sizeof(dst_matrix->scaling_list_8x8)); +} + +void +mtk_vdec_h264_copy_decode_params(struct slice_api_h264_decode_param *dst_p= arams, + const struct v4l2_ctrl_h264_decode_params *src_params, + const struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]) +{ + struct slice_h264_dpb_entry *dst_entry; + const struct v4l2_h264_dpb_entry *src_entry; + int i; + + for (i =3D 0; i < ARRAY_SIZE(dst_params->dpb); i++) { + dst_entry =3D &dst_params->dpb[i]; + src_entry =3D &dpb[i]; + + dst_entry->reference_ts =3D src_entry->reference_ts; + dst_entry->frame_num =3D src_entry->frame_num; + dst_entry->pic_num =3D src_entry->pic_num; + dst_entry->top_field_order_cnt =3D src_entry->top_field_order_cnt; + dst_entry->bottom_field_order_cnt =3D + src_entry->bottom_field_order_cnt; + dst_entry->flags =3D src_entry->flags; + } + + /* num_slices is a leftover from the old H.264 support and is ignored + * by the firmware. + */ + dst_params->num_slices =3D 0; + dst_params->nal_ref_idc =3D src_params->nal_ref_idc; + dst_params->top_field_order_cnt =3D src_params->top_field_order_cnt; + dst_params->bottom_field_order_cnt =3D src_params->bottom_field_order_cnt; + dst_params->flags =3D src_params->flags; +} + +static bool mtk_vdec_h264_dpb_entry_match(const struct v4l2_h264_dpb_entry= *a, + const struct v4l2_h264_dpb_entry *b) +{ + return a->top_field_order_cnt =3D=3D b->top_field_order_cnt && + a->bottom_field_order_cnt =3D=3D b->bottom_field_order_cnt; +} + +/* + * Move DPB entries of dec_param that refer to a frame already existing in= dpb + * into the already existing slot in dpb, and move other entries into new = slots. + * + * This function is an adaptation of the similarly-named function in + * hantro_h264.c. + */ +void mtk_vdec_h264_update_dpb(const struct v4l2_ctrl_h264_decode_params *d= ec_param, + struct v4l2_h264_dpb_entry *dpb) +{ + DECLARE_BITMAP(new, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; + DECLARE_BITMAP(in_use, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; + DECLARE_BITMAP(used, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; + unsigned int i, j; + + /* Disable all entries by default, and mark the ones in use. */ + for (i =3D 0; i < ARRAY_SIZE(dec_param->dpb); i++) { + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) + set_bit(i, in_use); + dpb[i].flags &=3D ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; + } + + /* Try to match new DPB entries with existing ones by their POCs. */ + for (i =3D 0; i < ARRAY_SIZE(dec_param->dpb); i++) { + const struct v4l2_h264_dpb_entry *ndpb =3D &dec_param->dpb[i]; + + if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) + continue; + + /* + * To cut off some comparisons, iterate only on target DPB + * entries were already used. + */ + for_each_set_bit(j, in_use, ARRAY_SIZE(dec_param->dpb)) { + struct v4l2_h264_dpb_entry *cdpb; + + cdpb =3D &dpb[j]; + if (!mtk_vdec_h264_dpb_entry_match(cdpb, ndpb)) + continue; + + *cdpb =3D *ndpb; + set_bit(j, used); + /* Don't reiterate on this one. */ + clear_bit(j, in_use); + break; + } + + if (j =3D=3D ARRAY_SIZE(dec_param->dpb)) + set_bit(i, new); + } + + /* For entries that could not be matched, use remaining free slots. */ + for_each_set_bit(i, new, ARRAY_SIZE(dec_param->dpb)) { + const struct v4l2_h264_dpb_entry *ndpb =3D &dec_param->dpb[i]; + struct v4l2_h264_dpb_entry *cdpb; + + /* + * Both arrays are of the same sizes, so there is no way + * we can end up with no space in target array, unless + * something is buggy. + */ + j =3D find_first_zero_bit(used, ARRAY_SIZE(dec_param->dpb)); + if (WARN_ON(j >=3D ARRAY_SIZE(dec_param->dpb))) + return; + + cdpb =3D &dpb[j]; + *cdpb =3D *ndpb; + set_bit(j, used); + } +} + +unsigned int mtk_vdec_h264_get_mv_buf_size(unsigned int width, unsigned in= t height) +{ + int unit_size =3D (width / MB_UNIT_LEN) * (height / MB_UNIT_LEN) + 8; + + return HW_MB_STORE_SZ * unit_size; +} + +int mtk_vdec_h264_find_start_code(unsigned char *data, unsigned int data_s= z) +{ + if (data_sz > 3 && data[0] =3D=3D 0 && data[1] =3D=3D 0 && data[2] =3D=3D= 1) + return 3; + + if (data_sz > 4 && data[0] =3D=3D 0 && data[1] =3D=3D 0 && data[2] =3D=3D= 0 && + data[3] =3D=3D 1) + return 4; + + return -1; +} diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_comm= on.h b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_common.h new file mode 100644 index 000000000000..0113f380b491 --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_common.h @@ -0,0 +1,274 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Yunfei Dong + */ + +#ifndef _VDEC_H264_REQ_COMMON_H_ +#define _VDEC_H264_REQ_COMMON_H_ + +#include +#include +#include +#include +#include + +#include "../mtk_vcodec_drv.h" + +#define NAL_NON_IDR_SLICE 0x01 +#define NAL_IDR_SLICE 0x05 +#define NAL_TYPE(value) ((value) & 0x1F) + +#define BUF_PREDICTION_SZ (64 * 4096) +#define MB_UNIT_LEN 16 + +/* motion vector size (bytes) for every macro block */ +#define HW_MB_STORE_SZ 64 + +#define H264_MAX_MV_NUM 32 + +/** + * struct mtk_h264_dpb_info - h264 dpb information + * + * @y_dma_addr: Y bitstream physical address + * @c_dma_addr: CbCr bitstream physical address + * @reference_flag: reference picture flag (short/long term reference pict= ure) + * @field: field picture flag + */ +struct mtk_h264_dpb_info { + dma_addr_t y_dma_addr; + dma_addr_t c_dma_addr; + int reference_flag; + int field; +}; + +/* + * struct mtk_h264_sps_param - parameters for sps + */ +struct mtk_h264_sps_param { + unsigned char chroma_format_idc; + unsigned char bit_depth_luma_minus8; + unsigned char bit_depth_chroma_minus8; + unsigned char log2_max_frame_num_minus4; + unsigned char pic_order_cnt_type; + unsigned char log2_max_pic_order_cnt_lsb_minus4; + unsigned char max_num_ref_frames; + unsigned char separate_colour_plane_flag; + unsigned short pic_width_in_mbs_minus1; + unsigned short pic_height_in_map_units_minus1; + unsigned int max_frame_nums; + unsigned char qpprime_y_zero_transform_bypass_flag; + unsigned char delta_pic_order_always_zero_flag; + unsigned char frame_mbs_only_flag; + unsigned char mb_adaptive_frame_field_flag; + unsigned char direct_8x8_inference_flag; + unsigned char reserved[3]; +}; + +/* + * struct mtk_h264_pps_param - parameters for pps + */ +struct mtk_h264_pps_param { + unsigned char num_ref_idx_l0_default_active_minus1; + unsigned char num_ref_idx_l1_default_active_minus1; + unsigned char weighted_bipred_idc; + char pic_init_qp_minus26; + char chroma_qp_index_offset; + char second_chroma_qp_index_offset; + unsigned char entropy_coding_mode_flag; + unsigned char pic_order_present_flag; + unsigned char deblocking_filter_control_present_flag; + unsigned char constrained_intra_pred_flag; + unsigned char weighted_pred_flag; + unsigned char redundant_pic_cnt_present_flag; + unsigned char transform_8x8_mode_flag; + unsigned char scaling_matrix_present_flag; + unsigned char reserved[2]; +}; + +/* + * struct mtk_h264_slice_hd_param - parameters for slice header + */ +struct mtk_h264_slice_hd_param { + unsigned int first_mb_in_slice; + unsigned int field_pic_flag; + unsigned int slice_type; + unsigned int frame_num; + int pic_order_cnt_lsb; + int delta_pic_order_cnt_bottom; + unsigned int bottom_field_flag; + unsigned int direct_spatial_mv_pred_flag; + int delta_pic_order_cnt0; + int delta_pic_order_cnt1; + unsigned int cabac_init_idc; + int slice_qp_delta; + unsigned int disable_deblocking_filter_idc; + int slice_alpha_c0_offset_div2; + int slice_beta_offset_div2; + unsigned int num_ref_idx_l0_active_minus1; + unsigned int num_ref_idx_l1_active_minus1; + unsigned int reserved; +}; + +/* + * struct slice_api_h264_scaling_matrix - parameters for scaling list + */ +struct slice_api_h264_scaling_matrix { + unsigned char scaling_list_4x4[6][16]; + unsigned char scaling_list_8x8[6][64]; +}; + +/* + * struct slice_h264_dpb_entry - each dpb information + */ +struct slice_h264_dpb_entry { + unsigned long long reference_ts; + unsigned short frame_num; + unsigned short pic_num; + /* Note that field is indicated by v4l2_buffer.field */ + int top_field_order_cnt; + int bottom_field_order_cnt; + unsigned int flags; +}; + +/* + * struct slice_api_h264_decode_param - parameters for decode. + */ +struct slice_api_h264_decode_param { + struct slice_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]; + unsigned short num_slices; + unsigned short nal_ref_idc; + unsigned char ref_pic_list_p0[32]; + unsigned char ref_pic_list_b0[32]; + unsigned char ref_pic_list_b1[32]; + int top_field_order_cnt; + int bottom_field_order_cnt; + unsigned int flags; +}; + +/** + * struct h264_fb - h264 decode frame buffer information + * + * @vdec_fb_va: virtual address of struct vdec_fb + * @y_fb_dma: dma address of Y frame buffer (luma) + * @c_fb_dma: dma address of C frame buffer (chroma) + * @poc: picture order count of frame buffer + * @reserved: for 8 bytes alignment + */ +struct h264_fb { + u64 vdec_fb_va; + u64 y_fb_dma; + u64 c_fb_dma; + s32 poc; + u32 reserved; +}; + +/** + * mtk_vdec_h264_fixup_ref_list - fixup unused reference to 0x20. + * + * @ref_list: reference picture list + * @num_valid: used reference number + */ +void mtk_vdec_h264_fixup_ref_list(u8 *ref_list, size_t num_valid); + +/** + * mtk_vdec_h264_get_ctrl_ptr - get each CID contrl address. + * + * @ctx: v4l2 ctx + * @id: CID control ID + * + * Return: returns CID ctrl address. + */ +void *mtk_vdec_h264_get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id); + +/** + * mtk_vdec_h264_fill_dpb_info - get each CID contrl address. + * + * @ctx: v4l2 ctx + * @decode_params: slice decode params + * @h264_dpb_info: dpb buffer information + */ +void mtk_vdec_h264_fill_dpb_info(struct mtk_vcodec_ctx *ctx, + struct slice_api_h264_decode_param *decode_params, + struct mtk_h264_dpb_info *h264_dpb_info); + +/** + * mtk_vdec_h264_copy_sps_params - get sps params. + * + * @dst_param: sps params for hw decoder + * @src_param: sps params from user driver + */ +void mtk_vdec_h264_copy_sps_params(struct mtk_h264_sps_param *dst_param, + const struct v4l2_ctrl_h264_sps *src_param); + +/** + * mtk_vdec_h264_copy_pps_params - get pps params. + * + * @dst_param: pps params for hw decoder + * @src_param: pps params from user driver + */ +void mtk_vdec_h264_copy_pps_params(struct mtk_h264_pps_param *dst_param, + const struct v4l2_ctrl_h264_pps *src_param); + +/** + * mtk_vdec_h264_copy_slice_hd_params - get slice header params. + * + * @dst_param: slice params for hw decoder + * @src_param: slice params from user driver + * @dec_param: decode params from user driver + */ +void mtk_vdec_h264_copy_slice_hd_params(struct mtk_h264_slice_hd_param *ds= t_param, + const struct v4l2_ctrl_h264_slice_params *src_param, + const struct v4l2_ctrl_h264_decode_params *dec_param); + +/** + * mtk_vdec_h264_copy_scaling_matrix - get each CID contrl address. + * + * @dst_matrix: scaling list params for hw decoder + * @src_matrix: scaling list params from user driver + */ +void mtk_vdec_h264_copy_scaling_matrix(struct slice_api_h264_scaling_matri= x *dst_matrix, + const struct v4l2_ctrl_h264_scaling_matrix *src_matrix); + +/** + * mtk_vdec_h264_copy_decode_params - get decode params. + * + * @dst_params: dst params for hw decoder + * @src_params: decode params from user driver + * @dpb: dpb information + */ +void +mtk_vdec_h264_copy_decode_params(struct slice_api_h264_decode_param *dst_p= arams, + const struct v4l2_ctrl_h264_decode_params *src_params, + const struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]); + +/** + * mtk_vdec_h264_update_dpb - updata dpb list. + * + * @dec_param: v4l2 control decode params + * @dpb: dpb entry informaton + */ +void mtk_vdec_h264_update_dpb(const struct v4l2_ctrl_h264_decode_params *d= ec_param, + struct v4l2_h264_dpb_entry *dpb); + +/** + * mtk_vdec_h264_find_start_code - find h264 start code using sofeware. + * + * @data: input buffer address + * @data_sz: input buffer size + * + * Return: returns start code position. + */ +int mtk_vdec_h264_find_start_code(unsigned char *data, unsigned int data_s= z); + +/** + * mtk_vdec_h264_get_mv_buf_size - get mv buffer size. + * + * @width: picture width + * @height: picture height + * + * Return: returns mv buffer size. + */ +unsigned int mtk_vdec_h264_get_mv_buf_size(unsigned int width, unsigned in= t height); + +#endif diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_if.c= b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_if.c index 27119aa31dd9..b055ceea481d 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_if.c @@ -12,109 +12,7 @@ #include "../vdec_drv_base.h" #include "../vdec_drv_if.h" #include "../vdec_vpu_if.h" - -#define BUF_PREDICTION_SZ (64 * 4096) -#define MB_UNIT_LEN 16 - -/* get used parameters for sps/pps */ -#define GET_MTK_VDEC_FLAG(cond, flag) \ - { dst_param->cond =3D ((src_param->flags & (flag)) ? (1) : (0)); } -#define GET_MTK_VDEC_PARAM(param) \ - { dst_param->param =3D src_param->param; } -/* motion vector size (bytes) for every macro block */ -#define HW_MB_STORE_SZ 64 - -#define H264_MAX_FB_NUM 17 -#define H264_MAX_MV_NUM 32 -#define HDR_PARSING_BUF_SZ 1024 - -/** - * struct mtk_h264_dpb_info - h264 dpb information - * @y_dma_addr: Y bitstream physical address - * @c_dma_addr: CbCr bitstream physical address - * @reference_flag: reference picture flag (short/long term reference pict= ure) - * @field: field picture flag - */ -struct mtk_h264_dpb_info { - dma_addr_t y_dma_addr; - dma_addr_t c_dma_addr; - int reference_flag; - int field; -}; - -/* - * struct mtk_h264_sps_param - parameters for sps - */ -struct mtk_h264_sps_param { - unsigned char chroma_format_idc; - unsigned char bit_depth_luma_minus8; - unsigned char bit_depth_chroma_minus8; - unsigned char log2_max_frame_num_minus4; - unsigned char pic_order_cnt_type; - unsigned char log2_max_pic_order_cnt_lsb_minus4; - unsigned char max_num_ref_frames; - unsigned char separate_colour_plane_flag; - unsigned short pic_width_in_mbs_minus1; - unsigned short pic_height_in_map_units_minus1; - unsigned int max_frame_nums; - unsigned char qpprime_y_zero_transform_bypass_flag; - unsigned char delta_pic_order_always_zero_flag; - unsigned char frame_mbs_only_flag; - unsigned char mb_adaptive_frame_field_flag; - unsigned char direct_8x8_inference_flag; - unsigned char reserved[3]; -}; - -/* - * struct mtk_h264_pps_param - parameters for pps - */ -struct mtk_h264_pps_param { - unsigned char num_ref_idx_l0_default_active_minus1; - unsigned char num_ref_idx_l1_default_active_minus1; - unsigned char weighted_bipred_idc; - char pic_init_qp_minus26; - char chroma_qp_index_offset; - char second_chroma_qp_index_offset; - unsigned char entropy_coding_mode_flag; - unsigned char pic_order_present_flag; - unsigned char deblocking_filter_control_present_flag; - unsigned char constrained_intra_pred_flag; - unsigned char weighted_pred_flag; - unsigned char redundant_pic_cnt_present_flag; - unsigned char transform_8x8_mode_flag; - unsigned char scaling_matrix_present_flag; - unsigned char reserved[2]; -}; - -struct slice_api_h264_scaling_matrix { - unsigned char scaling_list_4x4[6][16]; - unsigned char scaling_list_8x8[6][64]; -}; - -struct slice_h264_dpb_entry { - unsigned long long reference_ts; - unsigned short frame_num; - unsigned short pic_num; - /* Note that field is indicated by v4l2_buffer.field */ - int top_field_order_cnt; - int bottom_field_order_cnt; - unsigned int flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ -}; - -/* - * struct slice_api_h264_decode_param - parameters for decode. - */ -struct slice_api_h264_decode_param { - struct slice_h264_dpb_entry dpb[16]; - unsigned short num_slices; - unsigned short nal_ref_idc; - unsigned char ref_pic_list_p0[32]; - unsigned char ref_pic_list_b0[32]; - unsigned char ref_pic_list_b1[32]; - int top_field_order_cnt; - int bottom_field_order_cnt; - unsigned int flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ -}; +#include "vdec_h264_req_common.h" =20 /* * struct mtk_h264_dec_slice_param - parameters for decode current frame @@ -127,22 +25,6 @@ struct mtk_h264_dec_slice_param { struct mtk_h264_dpb_info h264_dpb_info[16]; }; =20 -/** - * struct h264_fb - h264 decode frame buffer information - * @vdec_fb_va : virtual address of struct vdec_fb - * @y_fb_dma : dma address of Y frame buffer (luma) - * @c_fb_dma : dma address of C frame buffer (chroma) - * @poc : picture order count of frame buffer - * @reserved : for 8 bytes alignment - */ -struct h264_fb { - u64 vdec_fb_va; - u64 y_fb_dma; - u64 c_fb_dma; - s32 poc; - u32 reserved; -}; - /** * struct vdec_h264_dec_info - decode information * @dpb_sz : decoding picture buffer size @@ -212,265 +94,45 @@ struct vdec_h264_slice_inst { struct v4l2_h264_dpb_entry dpb[16]; }; =20 -static void *get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int id) -{ - struct v4l2_ctrl *ctrl =3D v4l2_ctrl_find(&ctx->ctrl_hdl, id); - - return ctrl->p_cur.p; -} - -static void get_h264_dpb_list(struct vdec_h264_slice_inst *inst, - struct mtk_h264_dec_slice_param *slice_param) -{ - struct vb2_queue *vq; - struct vb2_buffer *vb; - struct vb2_v4l2_buffer *vb2_v4l2; - u64 index; - - vq =3D v4l2_m2m_get_vq(inst->ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MP= LANE); - - for (index =3D 0; index < ARRAY_SIZE(slice_param->decode_params.dpb); ind= ex++) { - const struct slice_h264_dpb_entry *dpb; - int vb2_index; - - dpb =3D &slice_param->decode_params.dpb[index]; - if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) { - slice_param->h264_dpb_info[index].reference_flag =3D 0; - continue; - } - - vb2_index =3D vb2_find_timestamp(vq, dpb->reference_ts, 0); - if (vb2_index < 0) { - mtk_vcodec_err(inst, "Reference invalid: dpb_index(%lld) reference_ts(%= lld)", - index, dpb->reference_ts); - continue; - } - /* 1 for short term reference, 2 for long term reference */ - if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)) - slice_param->h264_dpb_info[index].reference_flag =3D 1; - else - slice_param->h264_dpb_info[index].reference_flag =3D 2; - - vb =3D vq->bufs[vb2_index]; - vb2_v4l2 =3D container_of(vb, struct vb2_v4l2_buffer, vb2_buf); - slice_param->h264_dpb_info[index].field =3D vb2_v4l2->field; - - slice_param->h264_dpb_info[index].y_dma_addr =3D - vb2_dma_contig_plane_dma_addr(vb, 0); - if (inst->ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 2) { - slice_param->h264_dpb_info[index].c_dma_addr =3D - vb2_dma_contig_plane_dma_addr(vb, 1); - } - } -} - -static void get_h264_sps_parameters(struct mtk_h264_sps_param *dst_param, - const struct v4l2_ctrl_h264_sps *src_param) -{ - GET_MTK_VDEC_PARAM(chroma_format_idc); - GET_MTK_VDEC_PARAM(bit_depth_luma_minus8); - GET_MTK_VDEC_PARAM(bit_depth_chroma_minus8); - GET_MTK_VDEC_PARAM(log2_max_frame_num_minus4); - GET_MTK_VDEC_PARAM(pic_order_cnt_type); - GET_MTK_VDEC_PARAM(log2_max_pic_order_cnt_lsb_minus4); - GET_MTK_VDEC_PARAM(max_num_ref_frames); - GET_MTK_VDEC_PARAM(pic_width_in_mbs_minus1); - GET_MTK_VDEC_PARAM(pic_height_in_map_units_minus1); - - GET_MTK_VDEC_FLAG(separate_colour_plane_flag, - V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE); - GET_MTK_VDEC_FLAG(qpprime_y_zero_transform_bypass_flag, - V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS); - GET_MTK_VDEC_FLAG(delta_pic_order_always_zero_flag, - V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO); - GET_MTK_VDEC_FLAG(frame_mbs_only_flag, - V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY); - GET_MTK_VDEC_FLAG(mb_adaptive_frame_field_flag, - V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); - GET_MTK_VDEC_FLAG(direct_8x8_inference_flag, - V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE); -} - -static void get_h264_pps_parameters(struct mtk_h264_pps_param *dst_param, - const struct v4l2_ctrl_h264_pps *src_param) +static int get_vdec_decode_parameters(struct vdec_h264_slice_inst *inst) { - GET_MTK_VDEC_PARAM(num_ref_idx_l0_default_active_minus1); - GET_MTK_VDEC_PARAM(num_ref_idx_l1_default_active_minus1); - GET_MTK_VDEC_PARAM(weighted_bipred_idc); - GET_MTK_VDEC_PARAM(pic_init_qp_minus26); - GET_MTK_VDEC_PARAM(chroma_qp_index_offset); - GET_MTK_VDEC_PARAM(second_chroma_qp_index_offset); - - GET_MTK_VDEC_FLAG(entropy_coding_mode_flag, - V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); - GET_MTK_VDEC_FLAG(pic_order_present_flag, - V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); - GET_MTK_VDEC_FLAG(weighted_pred_flag, - V4L2_H264_PPS_FLAG_WEIGHTED_PRED); - GET_MTK_VDEC_FLAG(deblocking_filter_control_present_flag, - V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); - GET_MTK_VDEC_FLAG(constrained_intra_pred_flag, - V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED); - GET_MTK_VDEC_FLAG(redundant_pic_cnt_present_flag, - V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT); - GET_MTK_VDEC_FLAG(transform_8x8_mode_flag, - V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE); - GET_MTK_VDEC_FLAG(scaling_matrix_present_flag, - V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT); -} - -static void -get_h264_scaling_matrix(struct slice_api_h264_scaling_matrix *dst_matrix, - const struct v4l2_ctrl_h264_scaling_matrix *src_matrix) -{ - memcpy(dst_matrix->scaling_list_4x4, src_matrix->scaling_list_4x4, - sizeof(dst_matrix->scaling_list_4x4)); - - memcpy(dst_matrix->scaling_list_8x8, src_matrix->scaling_list_8x8, - sizeof(dst_matrix->scaling_list_8x8)); -} - -static void -get_h264_decode_parameters(struct slice_api_h264_decode_param *dst_params, - const struct v4l2_ctrl_h264_decode_params *src_params, - const struct v4l2_h264_dpb_entry dpb[V4L2_H264_NUM_DPB_ENTRIES]) -{ - int i; - - for (i =3D 0; i < ARRAY_SIZE(dst_params->dpb); i++) { - struct slice_h264_dpb_entry *dst_entry =3D &dst_params->dpb[i]; - const struct v4l2_h264_dpb_entry *src_entry =3D &dpb[i]; - - dst_entry->reference_ts =3D src_entry->reference_ts; - dst_entry->frame_num =3D src_entry->frame_num; - dst_entry->pic_num =3D src_entry->pic_num; - dst_entry->top_field_order_cnt =3D src_entry->top_field_order_cnt; - dst_entry->bottom_field_order_cnt =3D - src_entry->bottom_field_order_cnt; - dst_entry->flags =3D src_entry->flags; - } - - /* - * num_slices is a leftover from the old H.264 support and is ignored - * by the firmware. - */ - dst_params->num_slices =3D 0; - dst_params->nal_ref_idc =3D src_params->nal_ref_idc; - dst_params->top_field_order_cnt =3D src_params->top_field_order_cnt; - dst_params->bottom_field_order_cnt =3D src_params->bottom_field_order_cnt; - dst_params->flags =3D src_params->flags; -} - -static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a, - const struct v4l2_h264_dpb_entry *b) -{ - return a->top_field_order_cnt =3D=3D b->top_field_order_cnt && - a->bottom_field_order_cnt =3D=3D b->bottom_field_order_cnt; -} - -/* - * Move DPB entries of dec_param that refer to a frame already existing in= dpb - * into the already existing slot in dpb, and move other entries into new = slots. - * - * This function is an adaptation of the similarly-named function in - * hantro_h264.c. - */ -static void update_dpb(const struct v4l2_ctrl_h264_decode_params *dec_para= m, - struct v4l2_h264_dpb_entry *dpb) -{ - DECLARE_BITMAP(new, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; - DECLARE_BITMAP(in_use, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; - DECLARE_BITMAP(used, ARRAY_SIZE(dec_param->dpb)) =3D { 0, }; - unsigned int i, j; - - /* Disable all entries by default, and mark the ones in use. */ - for (i =3D 0; i < ARRAY_SIZE(dec_param->dpb); i++) { - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) - set_bit(i, in_use); - dpb[i].flags &=3D ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE; - } - - /* Try to match new DPB entries with existing ones by their POCs. */ - for (i =3D 0; i < ARRAY_SIZE(dec_param->dpb); i++) { - const struct v4l2_h264_dpb_entry *ndpb =3D &dec_param->dpb[i]; - - if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) - continue; - - /* - * To cut off some comparisons, iterate only on target DPB - * entries were already used. - */ - for_each_set_bit(j, in_use, ARRAY_SIZE(dec_param->dpb)) { - struct v4l2_h264_dpb_entry *cdpb; - - cdpb =3D &dpb[j]; - if (!dpb_entry_match(cdpb, ndpb)) - continue; - - *cdpb =3D *ndpb; - set_bit(j, used); - /* Don't reiterate on this one. */ - clear_bit(j, in_use); - break; - } - - if (j =3D=3D ARRAY_SIZE(dec_param->dpb)) - set_bit(i, new); - } - - /* For entries that could not be matched, use remaining free slots. */ - for_each_set_bit(i, new, ARRAY_SIZE(dec_param->dpb)) { - const struct v4l2_h264_dpb_entry *ndpb =3D &dec_param->dpb[i]; - struct v4l2_h264_dpb_entry *cdpb; - - /* - * Both arrays are of the same sizes, so there is no way - * we can end up with no space in target array, unless - * something is buggy. - */ - j =3D find_first_zero_bit(used, ARRAY_SIZE(dec_param->dpb)); - if (WARN_ON(j >=3D ARRAY_SIZE(dec_param->dpb))) - return; - - cdpb =3D &dpb[j]; - *cdpb =3D *ndpb; - set_bit(j, used); - } -} - -/* - * The firmware expects unused reflist entries to have the value 0x20. - */ -static void fixup_ref_list(u8 *ref_list, size_t num_valid) -{ - memset(&ref_list[num_valid], 0x20, 32 - num_valid); -} - -static void get_vdec_decode_parameters(struct vdec_h264_slice_inst *inst) -{ - const struct v4l2_ctrl_h264_decode_params *dec_params =3D - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); - const struct v4l2_ctrl_h264_sps *sps =3D - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS); - const struct v4l2_ctrl_h264_pps *pps =3D - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS); - const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix =3D - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MATRIX); + const struct v4l2_ctrl_h264_decode_params *dec_params; + const struct v4l2_ctrl_h264_sps *sps; + const struct v4l2_ctrl_h264_pps *pps; + const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; struct mtk_h264_dec_slice_param *slice_param =3D &inst->h264_slice_param; struct v4l2_h264_reflist_builder reflist_builder; u8 *p0_reflist =3D slice_param->decode_params.ref_pic_list_p0; u8 *b0_reflist =3D slice_param->decode_params.ref_pic_list_b0; u8 *b1_reflist =3D slice_param->decode_params.ref_pic_list_b1; =20 - update_dpb(dec_params, inst->dpb); + dec_params =3D + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PAR= AMS); + if (IS_ERR(dec_params)) + return PTR_ERR(dec_params); + + sps =3D mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS= ); + if (IS_ERR(sps)) + return PTR_ERR(sps); + + pps =3D mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS= ); + if (IS_ERR(pps)) + return PTR_ERR(pps); =20 - get_h264_sps_parameters(&slice_param->sps, sps); - get_h264_pps_parameters(&slice_param->pps, pps); - get_h264_scaling_matrix(&slice_param->scaling_matrix, scaling_matrix); - get_h264_decode_parameters(&slice_param->decode_params, dec_params, - inst->dpb); - get_h264_dpb_list(inst, slice_param); + scaling_matrix =3D + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MA= TRIX); + if (IS_ERR(scaling_matrix)) + return PTR_ERR(scaling_matrix); + + mtk_vdec_h264_update_dpb(dec_params, inst->dpb); + + mtk_vdec_h264_copy_sps_params(&slice_param->sps, sps); + mtk_vdec_h264_copy_pps_params(&slice_param->pps, pps); + mtk_vdec_h264_copy_scaling_matrix(&slice_param->scaling_matrix, scaling_m= atrix); + mtk_vdec_h264_copy_decode_params(&slice_param->decode_params, + dec_params, inst->dpb); + mtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params, + slice_param->h264_dpb_info); =20 /* Build the reference lists */ v4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, @@ -478,19 +140,14 @@ static void get_vdec_decode_parameters(struct vdec_h2= 64_slice_inst *inst) v4l2_h264_build_p_ref_list(&reflist_builder, p0_reflist); v4l2_h264_build_b_ref_lists(&reflist_builder, b0_reflist, b1_reflist); /* Adapt the built lists to the firmware's expectations */ - fixup_ref_list(p0_reflist, reflist_builder.num_valid); - fixup_ref_list(b0_reflist, reflist_builder.num_valid); - fixup_ref_list(b1_reflist, reflist_builder.num_valid); + mtk_vdec_h264_fixup_ref_list(p0_reflist, reflist_builder.num_valid); + mtk_vdec_h264_fixup_ref_list(b0_reflist, reflist_builder.num_valid); + mtk_vdec_h264_fixup_ref_list(b1_reflist, reflist_builder.num_valid); =20 memcpy(&inst->vsi_ctx.h264_slice_params, slice_param, sizeof(inst->vsi_ctx.h264_slice_params)); -} =20 -static unsigned int get_mv_buf_size(unsigned int width, unsigned int heigh= t) -{ - int unit_size =3D (width / MB_UNIT_LEN) * (height / MB_UNIT_LEN) + 8; - - return HW_MB_STORE_SZ * unit_size; + return 0; } =20 static int allocate_predication_buf(struct vdec_h264_slice_inst *inst) @@ -525,7 +182,7 @@ static int alloc_mv_buf(struct vdec_h264_slice_inst *in= st, int i; int err; struct mtk_vcodec_mem *mem =3D NULL; - unsigned int buf_sz =3D get_mv_buf_size(pic->buf_w, pic->buf_h); + unsigned int buf_sz =3D mtk_vdec_h264_get_mv_buf_size(pic->buf_w, pic->bu= f_h); =20 mtk_v4l2_debug(3, "size =3D 0x%x", buf_sz); for (i =3D 0; i < H264_MAX_MV_NUM; i++) { @@ -674,7 +331,7 @@ static int vdec_h264_slice_decode(void *h_vdec, struct = mtk_vcodec_mem *bs, { struct vdec_h264_slice_inst *inst =3D h_vdec; const struct v4l2_ctrl_h264_decode_params *dec_params =3D - get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PAR= AMS); struct vdec_vpu_inst *vpu =3D &inst->vpu; struct mtk_video_dec_buf *src_buf_info; struct mtk_video_dec_buf *dst_buf_info; @@ -684,6 +341,7 @@ static int vdec_h264_slice_decode(void *h_vdec, struct = mtk_vcodec_mem *bs, u64 c_fb_dma; int err; =20 + inst->num_nalu++; /* bs NULL means flush decoder */ if (!bs) return vpu_dec_reset(vpu); @@ -696,7 +354,7 @@ static int vdec_h264_slice_decode(void *h_vdec, struct = mtk_vcodec_mem *bs, c_fb_dma =3D fb ? (u64)fb->base_c.dma_addr : 0; =20 mtk_vcodec_debug(inst, "+ [%d] FB y_dma=3D%llx c_dma=3D%llx va=3D%p", - ++inst->num_nalu, y_fb_dma, c_fb_dma, fb); + inst->num_nalu, y_fb_dma, c_fb_dma, fb); =20 inst->vsi_ctx.dec.bs_dma =3D (uint64_t)bs->dma_addr; inst->vsi_ctx.dec.y_fb_dma =3D y_fb_dma; @@ -705,7 +363,10 @@ static int vdec_h264_slice_decode(void *h_vdec, struct= mtk_vcodec_mem *bs, =20 v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, &dst_buf_info->m2m_buf.vb, true); - get_vdec_decode_parameters(inst); + err =3D get_vdec_decode_parameters(inst); + if (err) + goto err_free_fb_out; + data[0] =3D bs->size; /* * Reconstruct the first byte of the NAL unit, as the firmware requests --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 985F1C433F5 for ; Fri, 6 May 2022 09:31:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1390663AbiEFJfO (ORCPT ); Fri, 6 May 2022 05:35:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390634AbiEFJdr (ORCPT ); Fri, 6 May 2022 05:33:47 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1469068F87; Fri, 6 May 2022 02:29:28 -0700 (PDT) X-UUID: 81a87f969375415891e134bcaa5aeecf-20220506 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:2ee91d52-bdf4-4a82-a9de-62d47495b785,OB:40,L OB:20,IP:0,URL:8,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham ,ACTION:release,TS:83 X-CID-INFO: VERSION:1.1.4,REQID:2ee91d52-bdf4-4a82-a9de-62d47495b785,OB:40,LOB :20,IP:0,URL:8,TC:0,Content:-20,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D ,ACTION:quarantine,TS:83 X-CID-META: VersionHash:faefae9,CLOUDID:c5647416-2e53-443e-b81a-655c13977218,C OID:18c2b7eb8f1c,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: 81a87f969375415891e134bcaa5aeecf-20220506 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 314497746; Fri, 06 May 2022 17:29:22 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 6 May 2022 17:29:20 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:19 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , Steve Cho , , , , , , Subject: [PATCH v11, 14/17] media: mediatek: vcodec: support stateless H.264 decoding for mt8192 Date: Fri, 6 May 2022 17:28:52 +0800 Message-ID: <20220506092855.22940-15-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Adds h264 lat and core architecture driver for mt8192, and the decode mode is frame based for stateless decoder. Signed-off-by: Yunfei Dong --- .../media/platform/mediatek/vcodec/Makefile | 1 + .../vcodec/vdec/vdec_h264_req_multi_if.c | 629 ++++++++++++++++++ .../platform/mediatek/vcodec/vdec_drv_if.c | 9 +- .../platform/mediatek/vcodec/vdec_drv_if.h | 1 + .../platform/mediatek/vcodec/vdec_vpu_if.h | 2 + include/linux/remoteproc/mtk_scp.h | 2 + 6 files changed, 643 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_r= eq_multi_if.c diff --git a/drivers/media/platform/mediatek/vcodec/Makefile b/drivers/medi= a/platform/mediatek/vcodec/Makefile index 3f41d748eee5..22edb1c86598 100644 --- a/drivers/media/platform/mediatek/vcodec/Makefile +++ b/drivers/media/platform/mediatek/vcodec/Makefile @@ -10,6 +10,7 @@ mtk-vcodec-dec-y :=3D vdec/vdec_h264_if.o \ vdec/vdec_vp9_if.o \ vdec/vdec_h264_req_if.o \ vdec/vdec_h264_req_common.o \ + vdec/vdec_h264_req_multi_if.o \ mtk_vcodec_dec_drv.o \ vdec_drv_if.o \ vdec_vpu_if.o \ diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_mult= i_if.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_multi_if= .c new file mode 100644 index 000000000000..024dae1ddee0 --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_h264_req_multi_if.c @@ -0,0 +1,629 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Yunfei Dong + */ + +#include +#include +#include +#include +#include + +#include "../mtk_vcodec_util.h" +#include "../mtk_vcodec_dec.h" +#include "../mtk_vcodec_intr.h" +#include "../vdec_drv_base.h" +#include "../vdec_drv_if.h" +#include "../vdec_vpu_if.h" +#include "vdec_h264_req_common.h" + +/** + * enum vdec_h264_core_dec_err_type - core decode error type + * + * @TRANS_BUFFER_FULL: trans buffer is full + * @SLICE_HEADER_FULL: slice header buffer is full + */ +enum vdec_h264_core_dec_err_type { + TRANS_BUFFER_FULL =3D 1, + SLICE_HEADER_FULL, +}; + +/** + * struct vdec_h264_slice_lat_dec_param - parameters for decode current f= rame + * + * @sps: h264 sps syntax parameters + * @pps: h264 pps syntax parameters + * @slice_header: h264 slice header syntax parameters + * @scaling_matrix: h264 scaling list parameters + * @decode_params: decoder parameters of each frame used for hardware deco= de + * @h264_dpb_info: dpb reference list + */ +struct vdec_h264_slice_lat_dec_param { + struct mtk_h264_sps_param sps; + struct mtk_h264_pps_param pps; + struct mtk_h264_slice_hd_param slice_header; + struct slice_api_h264_scaling_matrix scaling_matrix; + struct slice_api_h264_decode_param decode_params; + struct mtk_h264_dpb_info h264_dpb_info[V4L2_H264_NUM_DPB_ENTRIES]; +}; + +/** + * struct vdec_h264_slice_info - decode information + * + * @nal_info: nal info of current picture + * @timeout: Decode timeout: 1 timeout, 0 no timeount + * @bs_buf_size: bitstream size + * @bs_buf_addr: bitstream buffer dma address + * @y_fb_dma: Y frame buffer dma address + * @c_fb_dma: C frame buffer dma address + * @vdec_fb_va: VDEC frame buffer struct virtual address + * @crc: Used to check whether hardware's status is right + */ +struct vdec_h264_slice_info { + u16 nal_info; + u16 timeout; + u32 bs_buf_size; + u64 bs_buf_addr; + u64 y_fb_dma; + u64 c_fb_dma; + u64 vdec_fb_va; + u32 crc[8]; +}; + +/** + * struct vdec_h264_slice_vsi - shared memory for decode information excha= nge + * between SCP and Host. + * + * @wdma_err_addr: wdma error dma address + * @wdma_start_addr: wdma start dma address + * @wdma_end_addr: wdma end dma address + * @slice_bc_start_addr: slice bc start dma address + * @slice_bc_end_addr: slice bc end dma address + * @row_info_start_addr: row info start dma address + * @row_info_end_addr: row info end dma address + * @trans_start: trans start dma address + * @trans_end: trans end dma address + * @wdma_end_addr_offset: wdma end address offset + * + * @mv_buf_dma: HW working motion vector buffer + * dma address (AP-W, VPU-R) + * @dec: decode information (AP-R, VPU-W) + * @h264_slice_params: decode parameters for hw used + */ +struct vdec_h264_slice_vsi { + /* LAT dec addr */ + u64 wdma_err_addr; + u64 wdma_start_addr; + u64 wdma_end_addr; + u64 slice_bc_start_addr; + u64 slice_bc_end_addr; + u64 row_info_start_addr; + u64 row_info_end_addr; + u64 trans_start; + u64 trans_end; + u64 wdma_end_addr_offset; + + u64 mv_buf_dma[H264_MAX_MV_NUM]; + struct vdec_h264_slice_info dec; + struct vdec_h264_slice_lat_dec_param h264_slice_params; +}; + +/** + * struct vdec_h264_slice_share_info - shared information used to exchange + * message between lat and core + * + * @sps: sequence header information from user space + * @dec_params: decoder params from user space + * @h264_slice_params: decoder params used for hardware + * @trans_start: trans start dma address + * @trans_end: trans end dma address + * @nal_info: nal info of current picture + */ +struct vdec_h264_slice_share_info { + struct v4l2_ctrl_h264_sps sps; + struct v4l2_ctrl_h264_decode_params dec_params; + struct vdec_h264_slice_lat_dec_param h264_slice_params; + u64 trans_start; + u64 trans_end; + u16 nal_info; +}; + +/** + * struct vdec_h264_slice_inst - h264 decoder instance + * + * @slice_dec_num: how many picture be decoded + * @ctx: point to mtk_vcodec_ctx + * @pred_buf: HW working predication buffer + * @mv_buf: HW working motion vector buffer + * @vpu: VPU instance + * @vsi: vsi used for lat + * @vsi_core: vsi used for core + * + * @resolution_changed:resolution changed + * @realloc_mv_buf: reallocate mv buffer + * @cap_num_planes: number of capture queue plane + * + * @dpb: decoded picture buffer used to store reference + * buffer information + *@is_field_bitstream: is field bitstream + */ +struct vdec_h264_slice_inst { + unsigned int slice_dec_num; + struct mtk_vcodec_ctx *ctx; + struct mtk_vcodec_mem pred_buf; + struct mtk_vcodec_mem mv_buf[H264_MAX_MV_NUM]; + struct vdec_vpu_inst vpu; + struct vdec_h264_slice_vsi *vsi; + struct vdec_h264_slice_vsi *vsi_core; + + unsigned int resolution_changed; + unsigned int realloc_mv_buf; + unsigned int cap_num_planes; + + struct v4l2_h264_dpb_entry dpb[16]; + bool is_field_bitstream; +}; + +static int vdec_h264_slice_fill_decode_parameters(struct vdec_h264_slice_i= nst *inst, + struct vdec_h264_slice_share_info *share_info) +{ + struct vdec_h264_slice_lat_dec_param *slice_param =3D &inst->vsi->h264_sl= ice_params; + const struct v4l2_ctrl_h264_decode_params *dec_params; + const struct v4l2_ctrl_h264_scaling_matrix *src_matrix; + const struct v4l2_ctrl_h264_sps *sps; + const struct v4l2_ctrl_h264_pps *pps; + + dec_params =3D + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_DECODE_PAR= AMS); + if (IS_ERR(dec_params)) + return PTR_ERR(dec_params); + + src_matrix =3D + mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SCALING_MA= TRIX); + if (IS_ERR(src_matrix)) + return PTR_ERR(src_matrix); + + sps =3D mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_SPS= ); + if (IS_ERR(sps)) + return PTR_ERR(sps); + + pps =3D mtk_vdec_h264_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_H264_PPS= ); + if (IS_ERR(pps)) + return PTR_ERR(pps); + + if (dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) { + mtk_vcodec_err(inst, "No support for H.264 field decoding."); + inst->is_field_bitstream =3D true; + return -EINVAL; + } + + mtk_vdec_h264_copy_sps_params(&slice_param->sps, sps); + mtk_vdec_h264_copy_pps_params(&slice_param->pps, pps); + mtk_vdec_h264_copy_scaling_matrix(&slice_param->scaling_matrix, src_matri= x); + + memcpy(&share_info->sps, sps, sizeof(*sps)); + memcpy(&share_info->dec_params, dec_params, sizeof(*dec_params)); + + return 0; +} + +static void vdec_h264_slice_fill_decode_reflist(struct vdec_h264_slice_ins= t *inst, + struct vdec_h264_slice_lat_dec_param *slice_param, + struct vdec_h264_slice_share_info *share_info) +{ + struct v4l2_ctrl_h264_decode_params *dec_params =3D &share_info->dec_para= ms; + struct v4l2_ctrl_h264_sps *sps =3D &share_info->sps; + struct v4l2_h264_reflist_builder reflist_builder; + u8 *p0_reflist =3D slice_param->decode_params.ref_pic_list_p0; + u8 *b0_reflist =3D slice_param->decode_params.ref_pic_list_b0; + u8 *b1_reflist =3D slice_param->decode_params.ref_pic_list_b1; + + mtk_vdec_h264_update_dpb(dec_params, inst->dpb); + + mtk_vdec_h264_copy_decode_params(&slice_param->decode_params, dec_params, + inst->dpb); + mtk_vdec_h264_fill_dpb_info(inst->ctx, &slice_param->decode_params, + slice_param->h264_dpb_info); + + mtk_v4l2_debug(3, "cur poc =3D %d\n", dec_params->bottom_field_order_cnt); + /* Build the reference lists */ + v4l2_h264_init_reflist_builder(&reflist_builder, dec_params, sps, + inst->dpb); + v4l2_h264_build_p_ref_list(&reflist_builder, p0_reflist); + v4l2_h264_build_b_ref_lists(&reflist_builder, b0_reflist, b1_reflist); + + /* Adapt the built lists to the firmware's expectations */ + mtk_vdec_h264_fixup_ref_list(p0_reflist, reflist_builder.num_valid); + mtk_vdec_h264_fixup_ref_list(b0_reflist, reflist_builder.num_valid); + mtk_vdec_h264_fixup_ref_list(b1_reflist, reflist_builder.num_valid); +} + +static int vdec_h264_slice_alloc_mv_buf(struct vdec_h264_slice_inst *inst, + struct vdec_pic_info *pic) +{ + unsigned int buf_sz =3D mtk_vdec_h264_get_mv_buf_size(pic->buf_w, pic->bu= f_h); + struct mtk_vcodec_mem *mem; + int i, err; + + mtk_v4l2_debug(3, "size =3D 0x%x", buf_sz); + for (i =3D 0; i < H264_MAX_MV_NUM; i++) { + mem =3D &inst->mv_buf[i]; + if (mem->va) + mtk_vcodec_mem_free(inst->ctx, mem); + mem->size =3D buf_sz; + err =3D mtk_vcodec_mem_alloc(inst->ctx, mem); + if (err) { + mtk_vcodec_err(inst, "failed to allocate mv buf"); + return err; + } + } + + return 0; +} + +static void vdec_h264_slice_free_mv_buf(struct vdec_h264_slice_inst *inst) +{ + int i; + struct mtk_vcodec_mem *mem; + + for (i =3D 0; i < H264_MAX_MV_NUM; i++) { + mem =3D &inst->mv_buf[i]; + if (mem->va) + mtk_vcodec_mem_free(inst->ctx, mem); + } +} + +static void vdec_h264_slice_get_pic_info(struct vdec_h264_slice_inst *inst) +{ + struct mtk_vcodec_ctx *ctx =3D inst->ctx; + u32 data[3]; + + data[0] =3D ctx->picinfo.pic_w; + data[1] =3D ctx->picinfo.pic_h; + data[2] =3D ctx->capture_fourcc; + vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO); + + ctx->picinfo.buf_w =3D ALIGN(ctx->picinfo.pic_w, VCODEC_DEC_ALIGNED_64); + ctx->picinfo.buf_h =3D ALIGN(ctx->picinfo.pic_h, VCODEC_DEC_ALIGNED_64); + ctx->picinfo.fb_sz[0] =3D inst->vpu.fb_sz[0]; + ctx->picinfo.fb_sz[1] =3D inst->vpu.fb_sz[1]; + inst->cap_num_planes =3D + ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes; + + mtk_vcodec_debug(inst, "pic(%d, %d), buf(%d, %d)", + ctx->picinfo.pic_w, ctx->picinfo.pic_h, + ctx->picinfo.buf_w, ctx->picinfo.buf_h); + mtk_vcodec_debug(inst, "Y/C(%d, %d)", ctx->picinfo.fb_sz[0], + ctx->picinfo.fb_sz[1]); + + if (ctx->last_decoded_picinfo.pic_w !=3D ctx->picinfo.pic_w || + ctx->last_decoded_picinfo.pic_h !=3D ctx->picinfo.pic_h) { + inst->resolution_changed =3D true; + if (ctx->last_decoded_picinfo.buf_w !=3D ctx->picinfo.buf_w || + ctx->last_decoded_picinfo.buf_h !=3D ctx->picinfo.buf_h) + inst->realloc_mv_buf =3D true; + + mtk_v4l2_debug(1, "resChg: (%d %d) : old(%d, %d) -> new(%d, %d)", + inst->resolution_changed, + inst->realloc_mv_buf, + ctx->last_decoded_picinfo.pic_w, + ctx->last_decoded_picinfo.pic_h, + ctx->picinfo.pic_w, ctx->picinfo.pic_h); + } +} + +static void vdec_h264_slice_get_crop_info(struct vdec_h264_slice_inst *ins= t, + struct v4l2_rect *cr) +{ + cr->left =3D 0; + cr->top =3D 0; + cr->width =3D inst->ctx->picinfo.pic_w; + cr->height =3D inst->ctx->picinfo.pic_h; + + mtk_vcodec_debug(inst, "l=3D%d, t=3D%d, w=3D%d, h=3D%d", + cr->left, cr->top, cr->width, cr->height); +} + +static int vdec_h264_slice_init(struct mtk_vcodec_ctx *ctx) +{ + struct vdec_h264_slice_inst *inst; + int err, vsi_size; + + inst =3D kzalloc(sizeof(*inst), GFP_KERNEL); + if (!inst) + return -ENOMEM; + + inst->ctx =3D ctx; + + inst->vpu.id =3D SCP_IPI_VDEC_LAT; + inst->vpu.core_id =3D SCP_IPI_VDEC_CORE; + inst->vpu.ctx =3D ctx; + inst->vpu.codec_type =3D ctx->current_codec; + inst->vpu.capture_type =3D ctx->capture_fourcc; + + err =3D vpu_dec_init(&inst->vpu); + if (err) { + mtk_vcodec_err(inst, "vdec_h264 init err=3D%d", err); + goto error_free_inst; + } + + vsi_size =3D round_up(sizeof(struct vdec_h264_slice_vsi), VCODEC_DEC_ALIG= NED_64); + inst->vsi =3D inst->vpu.vsi; + inst->vsi_core =3D + (struct vdec_h264_slice_vsi *)(((char *)inst->vpu.vsi) + vsi_size); + inst->resolution_changed =3D true; + inst->realloc_mv_buf =3D true; + + mtk_vcodec_debug(inst, "lat struct size =3D %d,%d,%d,%d vsi: %d\n", + (int)sizeof(struct mtk_h264_sps_param), + (int)sizeof(struct mtk_h264_pps_param), + (int)sizeof(struct vdec_h264_slice_lat_dec_param), + (int)sizeof(struct mtk_h264_dpb_info), + vsi_size); + mtk_vcodec_debug(inst, "lat H264 instance >> %p, codec_type =3D 0x%x", + inst, inst->vpu.codec_type); + + ctx->drv_handle =3D inst; + return 0; + +error_free_inst: + kfree(inst); + return err; +} + +static void vdec_h264_slice_deinit(void *h_vdec) +{ + struct vdec_h264_slice_inst *inst =3D h_vdec; + + mtk_vcodec_debug_enter(inst); + + vpu_dec_deinit(&inst->vpu); + vdec_h264_slice_free_mv_buf(inst); + vdec_msg_queue_deinit(&inst->ctx->msg_queue, inst->ctx); + + kfree(inst); +} + +static int vdec_h264_slice_core_decode(struct vdec_lat_buf *lat_buf) +{ + struct vdec_fb *fb; + u64 vdec_fb_va; + u64 y_fb_dma, c_fb_dma; + int err, timeout, i; + struct mtk_vcodec_ctx *ctx =3D lat_buf->ctx; + struct vdec_h264_slice_inst *inst =3D ctx->drv_handle; + struct vb2_v4l2_buffer *vb2_v4l2; + struct vdec_h264_slice_share_info *share_info =3D lat_buf->private_data; + struct mtk_vcodec_mem *mem; + struct vdec_vpu_inst *vpu =3D &inst->vpu; + + mtk_vcodec_debug(inst, "[h264-core] vdec_h264 core decode"); + memcpy_toio((void __iomem *)&inst->vsi_core->h264_slice_params, + &share_info->h264_slice_params, + sizeof(share_info->h264_slice_params)); + + fb =3D ctx->dev->vdec_pdata->get_cap_buffer(ctx); + y_fb_dma =3D fb ? (u64)fb->base_y.dma_addr : 0; + vdec_fb_va =3D (unsigned long)fb; + + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 1) + c_fb_dma =3D + y_fb_dma + inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h; + else + c_fb_dma =3D fb ? (u64)fb->base_c.dma_addr : 0; + + mtk_vcodec_debug(inst, "[h264-core] y/c addr =3D 0x%llx 0x%llx", y_fb_dma, + c_fb_dma); + + inst->vsi_core->dec.y_fb_dma =3D y_fb_dma; + inst->vsi_core->dec.c_fb_dma =3D c_fb_dma; + inst->vsi_core->dec.vdec_fb_va =3D vdec_fb_va; + inst->vsi_core->dec.nal_info =3D share_info->nal_info; + inst->vsi_core->wdma_start_addr =3D + lat_buf->ctx->msg_queue.wdma_addr.dma_addr; + inst->vsi_core->wdma_end_addr =3D + lat_buf->ctx->msg_queue.wdma_addr.dma_addr + + lat_buf->ctx->msg_queue.wdma_addr.size; + inst->vsi_core->wdma_err_addr =3D lat_buf->wdma_err_addr.dma_addr; + inst->vsi_core->slice_bc_start_addr =3D lat_buf->slice_bc_addr.dma_addr; + inst->vsi_core->slice_bc_end_addr =3D lat_buf->slice_bc_addr.dma_addr + + lat_buf->slice_bc_addr.size; + inst->vsi_core->trans_start =3D share_info->trans_start; + inst->vsi_core->trans_end =3D share_info->trans_end; + for (i =3D 0; i < H264_MAX_MV_NUM; i++) { + mem =3D &inst->mv_buf[i]; + inst->vsi_core->mv_buf_dma[i] =3D mem->dma_addr; + } + + vb2_v4l2 =3D v4l2_m2m_next_dst_buf(ctx->m2m_ctx); + v4l2_m2m_buf_copy_metadata(&lat_buf->ts_info, vb2_v4l2, true); + + vdec_h264_slice_fill_decode_reflist(inst, &inst->vsi_core->h264_slice_par= ams, + share_info); + + err =3D vpu_dec_core(vpu); + if (err) { + mtk_vcodec_err(inst, "core decode err=3D%d", err); + goto vdec_dec_end; + } + + /* wait decoder done interrupt */ + timeout =3D mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE); + if (timeout) + mtk_vcodec_err(inst, "core decode timeout: pic_%d", + ctx->decoded_frame_cnt); + inst->vsi_core->dec.timeout =3D !!timeout; + + vpu_dec_core_end(vpu); + mtk_vcodec_debug(inst, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0= x%x", + ctx->decoded_frame_cnt, + inst->vsi_core->dec.crc[0], inst->vsi_core->dec.crc[1], + inst->vsi_core->dec.crc[2], inst->vsi_core->dec.crc[3], + inst->vsi_core->dec.crc[4], inst->vsi_core->dec.crc[5], + inst->vsi_core->dec.crc[6], inst->vsi_core->dec.crc[7]); + +vdec_dec_end: + vdec_msg_queue_update_ube_rptr(&lat_buf->ctx->msg_queue, share_info->tran= s_end); + ctx->dev->vdec_pdata->cap_to_disp(ctx, !!err, lat_buf->src_buf_req); + mtk_vcodec_debug(inst, "core decode done err=3D%d", err); + ctx->decoded_frame_cnt++; + return 0; +} + +static int vdec_h264_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem = *bs, + struct vdec_fb *fb, bool *res_chg) +{ + struct vdec_h264_slice_inst *inst =3D h_vdec; + struct vdec_vpu_inst *vpu =3D &inst->vpu; + struct mtk_video_dec_buf *src_buf_info; + int nal_start_idx, err, timeout =3D 0, i; + unsigned int data[2]; + struct vdec_lat_buf *lat_buf; + struct vdec_h264_slice_share_info *share_info; + unsigned char *buf; + struct mtk_vcodec_mem *mem; + + if (vdec_msg_queue_init(&inst->ctx->msg_queue, inst->ctx, + vdec_h264_slice_core_decode, + sizeof(*share_info))) + return -ENOMEM; + + /* bs NULL means flush decoder */ + if (!bs) { + vdec_msg_queue_wait_lat_buf_full(&inst->ctx->msg_queue); + return vpu_dec_reset(vpu); + } + + if (inst->is_field_bitstream) + return -EINVAL; + + lat_buf =3D vdec_msg_queue_dqbuf(&inst->ctx->msg_queue.lat_ctx); + if (!lat_buf) { + mtk_vcodec_err(inst, "failed to get lat buffer"); + return -EINVAL; + } + share_info =3D lat_buf->private_data; + src_buf_info =3D container_of(bs, struct mtk_video_dec_buf, bs_buffer); + + buf =3D (unsigned char *)bs->va; + nal_start_idx =3D mtk_vdec_h264_find_start_code(buf, bs->size); + if (nal_start_idx < 0) { + err =3D -EINVAL; + goto err_free_fb_out; + } + + inst->vsi->dec.nal_info =3D buf[nal_start_idx]; + inst->vsi->dec.bs_buf_addr =3D (u64)bs->dma_addr; + inst->vsi->dec.bs_buf_size =3D bs->size; + + lat_buf->src_buf_req =3D src_buf_info->m2m_buf.vb.vb2_buf.req_obj.req; + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, &lat_buf->ts_info, = true); + + err =3D vdec_h264_slice_fill_decode_parameters(inst, share_info); + if (err) + goto err_free_fb_out; + + *res_chg =3D inst->resolution_changed; + if (inst->resolution_changed) { + mtk_vcodec_debug(inst, "- resolution changed -"); + if (inst->realloc_mv_buf) { + err =3D vdec_h264_slice_alloc_mv_buf(inst, &inst->ctx->picinfo); + inst->realloc_mv_buf =3D false; + if (err) + goto err_free_fb_out; + } + inst->resolution_changed =3D false; + } + for (i =3D 0; i < H264_MAX_MV_NUM; i++) { + mem =3D &inst->mv_buf[i]; + inst->vsi->mv_buf_dma[i] =3D mem->dma_addr; + } + inst->vsi->wdma_start_addr =3D lat_buf->ctx->msg_queue.wdma_addr.dma_addr; + inst->vsi->wdma_end_addr =3D lat_buf->ctx->msg_queue.wdma_addr.dma_addr + + lat_buf->ctx->msg_queue.wdma_addr.size; + inst->vsi->wdma_err_addr =3D lat_buf->wdma_err_addr.dma_addr; + inst->vsi->slice_bc_start_addr =3D lat_buf->slice_bc_addr.dma_addr; + inst->vsi->slice_bc_end_addr =3D lat_buf->slice_bc_addr.dma_addr + + lat_buf->slice_bc_addr.size; + + inst->vsi->trans_end =3D inst->ctx->msg_queue.wdma_rptr_addr; + inst->vsi->trans_start =3D inst->ctx->msg_queue.wdma_wptr_addr; + mtk_vcodec_debug(inst, "lat:trans(0x%llx 0x%llx) err:0x%llx", + inst->vsi->wdma_start_addr, + inst->vsi->wdma_end_addr, + inst->vsi->wdma_err_addr); + + mtk_vcodec_debug(inst, "slice(0x%llx 0x%llx) rprt((0x%llx 0x%llx))", + inst->vsi->slice_bc_start_addr, + inst->vsi->slice_bc_end_addr, + inst->vsi->trans_start, + inst->vsi->trans_end); + err =3D vpu_dec_start(vpu, data, 2); + if (err) { + mtk_vcodec_debug(inst, "lat decode err: %d", err); + goto err_dec_err; + } + + /* wait decoder done interrupt */ + timeout =3D mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0); + inst->vsi->dec.timeout =3D !!timeout; + + err =3D vpu_dec_end(vpu); + if (err =3D=3D SLICE_HEADER_FULL || timeout || err =3D=3D TRANS_BUFFER_FU= LL) { + err =3D -EINVAL; + goto err_dec_err; + } + + share_info->trans_end =3D inst->ctx->msg_queue.wdma_addr.dma_addr + + inst->vsi->wdma_end_addr_offset; + share_info->trans_start =3D inst->ctx->msg_queue.wdma_wptr_addr; + share_info->nal_info =3D inst->vsi->dec.nal_info; + vdec_msg_queue_update_ube_wptr(&lat_buf->ctx->msg_queue, + share_info->trans_end); + + memcpy_fromio(&share_info->h264_slice_params, + (void __iomem *)&inst->vsi->h264_slice_params, + sizeof(share_info->h264_slice_params)); + vdec_msg_queue_qbuf(&inst->ctx->dev->msg_queue_core_ctx, lat_buf); + + inst->slice_dec_num++; + return 0; + +err_dec_err: +err_free_fb_out: + vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf); + mtk_vcodec_err(inst, "slice dec number: %d err: %d", inst->slice_dec_num,= err); + return err; +} + +static int vdec_h264_slice_get_param(void *h_vdec, enum vdec_get_param_typ= e type, + void *out) +{ + struct vdec_h264_slice_inst *inst =3D h_vdec; + + switch (type) { + case GET_PARAM_PIC_INFO: + vdec_h264_slice_get_pic_info(inst); + break; + case GET_PARAM_DPB_SIZE: + *(unsigned int *)out =3D 6; + break; + case GET_PARAM_CROP_INFO: + vdec_h264_slice_get_crop_info(inst, out); + break; + default: + mtk_vcodec_err(inst, "invalid get parameter type=3D%d", type); + return -EINVAL; + } + return 0; +} + +const struct vdec_common_if vdec_h264_slice_multi_if =3D { + .init =3D vdec_h264_slice_init, + .decode =3D vdec_h264_slice_lat_decode, + .get_param =3D vdec_h264_slice_get_param, + .deinit =3D vdec_h264_slice_deinit, +}; diff --git a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c b/drivers= /media/platform/mediatek/vcodec/vdec_drv_if.c index c93dd0ea3537..75497c2e476f 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c @@ -16,11 +16,18 @@ =20 int vdec_if_init(struct mtk_vcodec_ctx *ctx, unsigned int fourcc) { + enum mtk_vdec_hw_arch hw_arch =3D ctx->dev->vdec_pdata->hw_arch; int ret =3D 0; =20 switch (fourcc) { case V4L2_PIX_FMT_H264_SLICE: - ctx->dec_if =3D &vdec_h264_slice_if; + if (!ctx->dev->vdec_pdata->is_subdev_supported) { + ctx->dec_if =3D &vdec_h264_slice_if; + ctx->hw_id =3D MTK_VDEC_CORE; + } else { + ctx->dec_if =3D &vdec_h264_slice_multi_if; + ctx->hw_id =3D IS_VDEC_LAT_ARCH(hw_arch) ? MTK_VDEC_LAT0 : MTK_VDEC_COR= E; + } break; case V4L2_PIX_FMT_H264: ctx->dec_if =3D &vdec_h264_if; diff --git a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h b/drivers= /media/platform/mediatek/vcodec/vdec_drv_if.h index d467e8af4a84..f00980ee5abf 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h +++ b/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h @@ -56,6 +56,7 @@ struct vdec_fb_node { =20 extern const struct vdec_common_if vdec_h264_if; extern const struct vdec_common_if vdec_h264_slice_if; +extern const struct vdec_common_if vdec_h264_slice_multi_if; extern const struct vdec_common_if vdec_vp8_if; extern const struct vdec_common_if vdec_vp9_if; =20 diff --git a/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.h b/drivers= /media/platform/mediatek/vcodec/vdec_vpu_if.h index fe6815d31e50..0436bba91457 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.h +++ b/drivers/media/platform/mediatek/vcodec/vdec_vpu_if.h @@ -28,6 +28,7 @@ struct mtk_vcodec_ctx; * @wq : wait queue to wait VPU message ack * @handler : ipi handler for each decoder * @codec_type : use codec type to separate different codecs + * @capture_type: used capture type to separate different capture format * @fb_sz : frame buffer size of each plane */ struct vdec_vpu_inst { @@ -43,6 +44,7 @@ struct vdec_vpu_inst { wait_queue_head_t wq; mtk_vcodec_ipi_handler handler; unsigned int codec_type; + unsigned int capture_type; unsigned int fb_sz[2]; }; =20 diff --git a/include/linux/remoteproc/mtk_scp.h b/include/linux/remoteproc/= mtk_scp.h index b47416f7aeb8..7c2b7cc9fe6c 100644 --- a/include/linux/remoteproc/mtk_scp.h +++ b/include/linux/remoteproc/mtk_scp.h @@ -41,6 +41,8 @@ enum scp_ipi_id { SCP_IPI_ISP_FRAME, SCP_IPI_FD_CMD, SCP_IPI_CROS_HOST_CMD, + SCP_IPI_VDEC_LAT, + SCP_IPI_VDEC_CORE, SCP_IPI_NS_SERVICE =3D 0xFF, SCP_IPI_MAX =3D 0x100, }; --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF563C433EF for ; Fri, 6 May 2022 09:31:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1390688AbiEFJfI (ORCPT ); Fri, 6 May 2022 05:35:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390680AbiEFJeD (ORCPT ); Fri, 6 May 2022 05:34:03 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26E5F68FB4; Fri, 6 May 2022 02:29:34 -0700 (PDT) X-UUID: 10937ad1fb0e439582b575c9f854ce68-20220506 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:595a22fc-e714-4c8c-9892-c562805eb389,OB:0,LO B:0,IP:0,URL:8,TC:0,Content:-20,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,AC TION:release,TS:-12 X-CID-META: VersionHash:faefae9,CLOUDID:f610d4b2-56b5-4c9e-8d83-0070b288eb6a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 10937ad1fb0e439582b575c9f854ce68-20220506 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1916945300; Fri, 06 May 2022 17:29:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 6 May 2022 17:29:28 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:21 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 15/17] media: mediatek: vcodec: support stateless VP8 decoding Date: Fri, 6 May 2022 17:28:53 +0800 Message-ID: <20220506092855.22940-16-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for VP8 decoding using the stateless API, as supported by MT8192. Signed-off-by: Yunfei Dong Reviewed-by: Nicolas Dufresne --- .../media/platform/mediatek/vcodec/Makefile | 1 + .../vcodec/mtk_vcodec_dec_stateless.c | 24 +- .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 1 + .../mediatek/vcodec/vdec/vdec_vp8_req_if.c | 437 ++++++++++++++++++ .../platform/mediatek/vcodec/vdec_drv_if.c | 4 + .../platform/mediatek/vcodec/vdec_drv_if.h | 1 + 6 files changed, 466 insertions(+), 2 deletions(-) create mode 100644 drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_re= q_if.c diff --git a/drivers/media/platform/mediatek/vcodec/Makefile b/drivers/medi= a/platform/mediatek/vcodec/Makefile index 22edb1c86598..b457daf2d196 100644 --- a/drivers/media/platform/mediatek/vcodec/Makefile +++ b/drivers/media/platform/mediatek/vcodec/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_VIDEO_MEDIATEK_VCODEC) +=3D mtk-vcodec-dec.o \ =20 mtk-vcodec-dec-y :=3D vdec/vdec_h264_if.o \ vdec/vdec_vp8_if.o \ + vdec/vdec_vp8_req_if.o \ vdec/vdec_vp9_if.o \ vdec/vdec_h264_req_if.o \ vdec/vdec_h264_req_common.o \ diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateles= s.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c index d5c69f94d28e..8517ed4efeb5 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c @@ -76,13 +76,28 @@ static const struct mtk_stateless_control mtk_stateless= _controls[] =3D { .max =3D V4L2_STATELESS_H264_START_CODE_ANNEX_B, }, .codec_type =3D V4L2_PIX_FMT_H264_SLICE, + }, + { + .cfg =3D { + .id =3D V4L2_CID_STATELESS_VP8_FRAME, + }, + .codec_type =3D V4L2_PIX_FMT_VP8_FRAME, + }, + { + .cfg =3D { + .id =3D V4L2_CID_MPEG_VIDEO_VP8_PROFILE, + .min =3D V4L2_MPEG_VIDEO_VP8_PROFILE_0, + .def =3D V4L2_MPEG_VIDEO_VP8_PROFILE_0, + .max =3D V4L2_MPEG_VIDEO_VP8_PROFILE_3, + }, + .codec_type =3D V4L2_PIX_FMT_VP8_FRAME, } }; =20 #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls) =20 -static struct mtk_video_fmt mtk_video_formats[3]; -static struct mtk_codec_framesizes mtk_vdec_framesizes[1]; +static struct mtk_video_fmt mtk_video_formats[4]; +static struct mtk_codec_framesizes mtk_vdec_framesizes[2]; =20 static struct mtk_video_fmt default_out_format; static struct mtk_video_fmt default_cap_format; @@ -322,6 +337,7 @@ static void mtk_vcodec_add_formats(unsigned int fourcc, =20 switch (fourcc) { case V4L2_PIX_FMT_H264_SLICE: + case V4L2_PIX_FMT_VP8_FRAME: mtk_video_formats[count_formats].fourcc =3D fourcc; mtk_video_formats[count_formats].type =3D MTK_FMT_DEC; mtk_video_formats[count_formats].num_planes =3D 1; @@ -365,6 +381,10 @@ static void mtk_vcodec_get_supported_formats(struct mt= k_vcodec_ctx *ctx) mtk_vcodec_add_formats(V4L2_PIX_FMT_H264_SLICE, ctx); out_format_count++; } + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP8_FRAME) { + mtk_vcodec_add_formats(V4L2_PIX_FMT_VP8_FRAME, ctx); + out_format_count++; + } =20 if (cap_format_count) default_cap_format =3D mtk_video_formats[cap_format_count - 1]; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index c047f421843b..2ba1c19f07b6 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -354,6 +354,7 @@ enum mtk_vdec_format_types { MTK_VDEC_FORMAT_MM21 =3D 0x20, MTK_VDEC_FORMAT_MT21C =3D 0x40, MTK_VDEC_FORMAT_H264_SLICE =3D 0x100, + MTK_VDEC_FORMAT_VP8_FRAME =3D 0x200, }; =20 /** diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_req_if.c = b/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_req_if.c new file mode 100644 index 000000000000..eef102f3f4f3 --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_req_if.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Yunfei Dong + */ + +#include +#include +#include +#include + +#include "../mtk_vcodec_util.h" +#include "../mtk_vcodec_dec.h" +#include "../mtk_vcodec_intr.h" +#include "../vdec_drv_base.h" +#include "../vdec_drv_if.h" +#include "../vdec_vpu_if.h" + +/* Decoding picture buffer size (3 reference frames plus current frame) */ +#define VP8_DPB_SIZE 4 + +/* HW working buffer size (bytes) */ +#define VP8_SEG_ID_SZ SZ_256K +#define VP8_PP_WRAPY_SZ SZ_64K +#define VP8_PP_WRAPC_SZ SZ_64K +#define VP8_VLD_PRED_SZ SZ_64K + +/** + * struct vdec_vp8_slice_info - decode misc information + * + * @vld_wrapper_dma: vld wrapper dma address + * @seg_id_buf_dma: seg id dma address + * @wrap_y_dma: wrap y dma address + * @wrap_c_dma: wrap y dma address + * @cur_y_fb_dma: current plane Y frame buffer dma address + * @cur_c_fb_dma: current plane C frame buffer dma address + * @bs_dma: bitstream dma address + * @bs_sz: bitstream size + * @resolution_changed:resolution change flag 1 - changed, 0 - not change + * @frame_header_type: current frame header type + * @wait_key_frame: wait key frame coming + * @crc: used to check whether hardware's status is right + * @reserved: reserved, currently unused + */ +struct vdec_vp8_slice_info { + u64 vld_wrapper_dma; + u64 seg_id_buf_dma; + u64 wrap_y_dma; + u64 wrap_c_dma; + u64 cur_y_fb_dma; + u64 cur_c_fb_dma; + u64 bs_dma; + u32 bs_sz; + u32 resolution_changed; + u32 frame_header_type; + u32 crc[8]; + u32 reserved; +}; + +/** + * struct vdec_vp8_slice_dpb_info - vp8 reference information + * + * @y_dma_addr: Y bitstream physical address + * @c_dma_addr: CbCr bitstream physical address + * @reference_flag: reference picture flag + * @reserved: 64bit align + */ +struct vdec_vp8_slice_dpb_info { + dma_addr_t y_dma_addr; + dma_addr_t c_dma_addr; + int reference_flag; + int reserved; +}; + +/** + * struct vdec_vp8_slice_vsi - VPU shared information + * + * @dec: decoding information + * @pic: picture information + * @vp8_dpb_info: reference buffer information + */ +struct vdec_vp8_slice_vsi { + struct vdec_vp8_slice_info dec; + struct vdec_pic_info pic; + struct vdec_vp8_slice_dpb_info vp8_dpb_info[3]; +}; + +/** + * struct vdec_vp8_slice_inst - VP8 decoder instance + * + * @seg_id_buf: seg buffer + * @wrap_y_buf: wrapper y buffer + * @wrap_c_buf: wrapper c buffer + * @vld_wrapper_buf: vld wrapper buffer + * @ctx: V4L2 context + * @vpu: VPU instance for decoder + * @vsi: VPU share information + */ +struct vdec_vp8_slice_inst { + struct mtk_vcodec_mem seg_id_buf; + struct mtk_vcodec_mem wrap_y_buf; + struct mtk_vcodec_mem wrap_c_buf; + struct mtk_vcodec_mem vld_wrapper_buf; + struct mtk_vcodec_ctx *ctx; + struct vdec_vpu_inst vpu; + struct vdec_vp8_slice_vsi *vsi; +}; + +static void *vdec_vp8_slice_get_ctrl_ptr(struct mtk_vcodec_ctx *ctx, int i= d) +{ + struct v4l2_ctrl *ctrl =3D v4l2_ctrl_find(&ctx->ctrl_hdl, id); + + if (!ctrl) + return ERR_PTR(-EINVAL); + + return ctrl->p_cur.p; +} + +static void vdec_vp8_slice_get_pic_info(struct vdec_vp8_slice_inst *inst) +{ + struct mtk_vcodec_ctx *ctx =3D inst->ctx; + unsigned int data[3]; + + data[0] =3D ctx->picinfo.pic_w; + data[1] =3D ctx->picinfo.pic_h; + data[2] =3D ctx->capture_fourcc; + vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO); + + ctx->picinfo.buf_w =3D ALIGN(ctx->picinfo.pic_w, 64); + ctx->picinfo.buf_h =3D ALIGN(ctx->picinfo.pic_h, 64); + ctx->picinfo.fb_sz[0] =3D inst->vpu.fb_sz[0]; + ctx->picinfo.fb_sz[1] =3D inst->vpu.fb_sz[1]; + + inst->vsi->pic.pic_w =3D ctx->picinfo.pic_w; + inst->vsi->pic.pic_h =3D ctx->picinfo.pic_h; + inst->vsi->pic.buf_w =3D ctx->picinfo.buf_w; + inst->vsi->pic.buf_h =3D ctx->picinfo.buf_h; + inst->vsi->pic.fb_sz[0] =3D ctx->picinfo.fb_sz[0]; + inst->vsi->pic.fb_sz[1] =3D ctx->picinfo.fb_sz[1]; + mtk_vcodec_debug(inst, "pic(%d, %d), buf(%d, %d)", + ctx->picinfo.pic_w, ctx->picinfo.pic_h, + ctx->picinfo.buf_w, ctx->picinfo.buf_h); + mtk_vcodec_debug(inst, "fb size: Y(%d), C(%d)", + ctx->picinfo.fb_sz[0], ctx->picinfo.fb_sz[1]); +} + +static int vdec_vp8_slice_alloc_working_buf(struct vdec_vp8_slice_inst *in= st) +{ + int err; + struct mtk_vcodec_mem *mem; + + mem =3D &inst->seg_id_buf; + mem->size =3D VP8_SEG_ID_SZ; + err =3D mtk_vcodec_mem_alloc(inst->ctx, mem); + if (err) { + mtk_vcodec_err(inst, "Cannot allocate working buffer"); + return err; + } + inst->vsi->dec.seg_id_buf_dma =3D (u64)mem->dma_addr; + + mem =3D &inst->wrap_y_buf; + mem->size =3D VP8_PP_WRAPY_SZ; + err =3D mtk_vcodec_mem_alloc(inst->ctx, mem); + if (err) { + mtk_vcodec_err(inst, "cannot allocate WRAP Y buffer"); + return err; + } + inst->vsi->dec.wrap_y_dma =3D (u64)mem->dma_addr; + + mem =3D &inst->wrap_c_buf; + mem->size =3D VP8_PP_WRAPC_SZ; + err =3D mtk_vcodec_mem_alloc(inst->ctx, mem); + if (err) { + mtk_vcodec_err(inst, "cannot allocate WRAP C buffer"); + return err; + } + inst->vsi->dec.wrap_c_dma =3D (u64)mem->dma_addr; + + mem =3D &inst->vld_wrapper_buf; + mem->size =3D VP8_VLD_PRED_SZ; + err =3D mtk_vcodec_mem_alloc(inst->ctx, mem); + if (err) { + mtk_vcodec_err(inst, "cannot allocate vld wrapper buffer"); + return err; + } + inst->vsi->dec.vld_wrapper_dma =3D (u64)mem->dma_addr; + + return 0; +} + +static void vdec_vp8_slice_free_working_buf(struct vdec_vp8_slice_inst *in= st) +{ + struct mtk_vcodec_mem *mem; + + mem =3D &inst->seg_id_buf; + if (mem->va) + mtk_vcodec_mem_free(inst->ctx, mem); + inst->vsi->dec.seg_id_buf_dma =3D 0; + + mem =3D &inst->wrap_y_buf; + if (mem->va) + mtk_vcodec_mem_free(inst->ctx, mem); + inst->vsi->dec.wrap_y_dma =3D 0; + + mem =3D &inst->wrap_c_buf; + if (mem->va) + mtk_vcodec_mem_free(inst->ctx, mem); + inst->vsi->dec.wrap_c_dma =3D 0; + + mem =3D &inst->vld_wrapper_buf; + if (mem->va) + mtk_vcodec_mem_free(inst->ctx, mem); + inst->vsi->dec.vld_wrapper_dma =3D 0; +} + +static u64 vdec_vp8_slice_get_ref_by_ts(const struct v4l2_ctrl_vp8_frame *= frame_header, + int index) +{ + switch (index) { + case 0: + return frame_header->last_frame_ts; + case 1: + return frame_header->golden_frame_ts; + case 2: + return frame_header->alt_frame_ts; + default: + break; + } + + return -1; +} + +static int vdec_vp8_slice_get_decode_parameters(struct vdec_vp8_slice_inst= *inst) +{ + const struct v4l2_ctrl_vp8_frame *frame_header; + struct mtk_vcodec_ctx *ctx =3D inst->ctx; + struct vb2_queue *vq; + struct vb2_buffer *vb; + u64 referenct_ts; + int index, vb2_index; + + frame_header =3D vdec_vp8_slice_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELES= S_VP8_FRAME); + if (IS_ERR(frame_header)) + return PTR_ERR(frame_header); + + vq =3D v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + for (index =3D 0; index < 3; index++) { + referenct_ts =3D vdec_vp8_slice_get_ref_by_ts(frame_header, index); + vb2_index =3D vb2_find_timestamp(vq, referenct_ts, 0); + if (vb2_index < 0) { + if (!V4L2_VP8_FRAME_IS_KEY_FRAME(frame_header)) + mtk_vcodec_err(inst, "reference invalid: index(%d) ts(%lld)", + index, referenct_ts); + inst->vsi->vp8_dpb_info[index].reference_flag =3D 0; + continue; + } + inst->vsi->vp8_dpb_info[index].reference_flag =3D 1; + + vb =3D vq->bufs[vb2_index]; + inst->vsi->vp8_dpb_info[index].y_dma_addr =3D + vb2_dma_contig_plane_dma_addr(vb, 0); + if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 2) + inst->vsi->vp8_dpb_info[index].c_dma_addr =3D + vb2_dma_contig_plane_dma_addr(vb, 1); + else + inst->vsi->vp8_dpb_info[index].c_dma_addr =3D + inst->vsi->vp8_dpb_info[index].y_dma_addr + + ctx->picinfo.fb_sz[0]; + } + + inst->vsi->dec.frame_header_type =3D frame_header->flags >> 1; + + return 0; +} + +static int vdec_vp8_slice_init(struct mtk_vcodec_ctx *ctx) +{ + struct vdec_vp8_slice_inst *inst; + int err; + + inst =3D kzalloc(sizeof(*inst), GFP_KERNEL); + if (!inst) + return -ENOMEM; + + inst->ctx =3D ctx; + + inst->vpu.id =3D SCP_IPI_VDEC_LAT; + inst->vpu.core_id =3D SCP_IPI_VDEC_CORE; + inst->vpu.ctx =3D ctx; + inst->vpu.codec_type =3D ctx->current_codec; + inst->vpu.capture_type =3D ctx->capture_fourcc; + + err =3D vpu_dec_init(&inst->vpu); + if (err) { + mtk_vcodec_err(inst, "vdec_vp8 init err=3D%d", err); + goto error_free_inst; + } + + inst->vsi =3D inst->vpu.vsi; + err =3D vdec_vp8_slice_alloc_working_buf(inst); + if (err) + goto error_deinit; + + mtk_vcodec_debug(inst, "vp8 struct size =3D %d vsi: %d\n", + (int)sizeof(struct v4l2_ctrl_vp8_frame), + (int)sizeof(struct vdec_vp8_slice_vsi)); + mtk_vcodec_debug(inst, "vp8:%p, codec_type =3D 0x%x vsi: 0x%p", + inst, inst->vpu.codec_type, inst->vpu.vsi); + + ctx->drv_handle =3D inst; + return 0; + +error_deinit: + vpu_dec_deinit(&inst->vpu); +error_free_inst: + kfree(inst); + return err; +} + +static int vdec_vp8_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs, + struct vdec_fb *fb, bool *res_chg) +{ + struct vdec_vp8_slice_inst *inst =3D h_vdec; + struct vdec_vpu_inst *vpu =3D &inst->vpu; + struct mtk_video_dec_buf *src_buf_info, *dst_buf_info; + unsigned int data; + u64 y_fb_dma, c_fb_dma; + int err, timeout; + + /* Resolution changes are never initiated by us */ + *res_chg =3D false; + + /* bs NULL means flush decoder */ + if (!bs) + return vpu_dec_reset(vpu); + + src_buf_info =3D container_of(bs, struct mtk_video_dec_buf, bs_buffer); + + fb =3D inst->ctx->dev->vdec_pdata->get_cap_buffer(inst->ctx); + dst_buf_info =3D container_of(fb, struct mtk_video_dec_buf, frame_buffer); + + y_fb_dma =3D fb ? (u64)fb->base_y.dma_addr : 0; + if (inst->ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes =3D=3D 1) + c_fb_dma =3D y_fb_dma + + inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h; + else + c_fb_dma =3D fb ? (u64)fb->base_c.dma_addr : 0; + + inst->vsi->dec.bs_dma =3D (u64)bs->dma_addr; + inst->vsi->dec.bs_sz =3D bs->size; + inst->vsi->dec.cur_y_fb_dma =3D y_fb_dma; + inst->vsi->dec.cur_c_fb_dma =3D c_fb_dma; + + mtk_vcodec_debug(inst, "frame[%d] bs(%zu 0x%llx) y/c(0x%llx 0x%llx)", + inst->ctx->decoded_frame_cnt, + bs->size, (u64)bs->dma_addr, + y_fb_dma, c_fb_dma); + + v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, + &dst_buf_info->m2m_buf.vb, true); + + err =3D vdec_vp8_slice_get_decode_parameters(inst); + if (err) + goto error; + + err =3D vpu_dec_start(vpu, &data, 1); + if (err) { + mtk_vcodec_debug(inst, "vp8 dec start err!"); + goto error; + } + + if (inst->vsi->dec.resolution_changed) { + mtk_vcodec_debug(inst, "- resolution_changed -"); + *res_chg =3D true; + return 0; + } + + /* wait decode done interrupt */ + timeout =3D mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED, + 50, MTK_VDEC_CORE); + + err =3D vpu_dec_end(vpu); + if (err || timeout) + mtk_vcodec_debug(inst, "vp8 dec error timeout:%d err: %d pic_%d", + timeout, err, inst->ctx->decoded_frame_cnt); + + mtk_vcodec_debug(inst, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0= x%x", + inst->ctx->decoded_frame_cnt, + inst->vsi->dec.crc[0], inst->vsi->dec.crc[1], + inst->vsi->dec.crc[2], inst->vsi->dec.crc[3], + inst->vsi->dec.crc[4], inst->vsi->dec.crc[5], + inst->vsi->dec.crc[6], inst->vsi->dec.crc[7]); + + inst->ctx->decoded_frame_cnt++; +error: + return err; +} + +static int vdec_vp8_slice_get_param(void *h_vdec, enum vdec_get_param_type= type, void *out) +{ + struct vdec_vp8_slice_inst *inst =3D h_vdec; + + switch (type) { + case GET_PARAM_PIC_INFO: + vdec_vp8_slice_get_pic_info(inst); + break; + case GET_PARAM_CROP_INFO: + mtk_vcodec_debug(inst, "No need to get vp8 crop information."); + break; + case GET_PARAM_DPB_SIZE: + *((unsigned int *)out) =3D VP8_DPB_SIZE; + break; + default: + mtk_vcodec_err(inst, "invalid get parameter type=3D%d", type); + return -EINVAL; + } + + return 0; +} + +static void vdec_vp8_slice_deinit(void *h_vdec) +{ + struct vdec_vp8_slice_inst *inst =3D h_vdec; + + mtk_vcodec_debug_enter(inst); + + vpu_dec_deinit(&inst->vpu); + vdec_vp8_slice_free_working_buf(inst); + kfree(inst); +} + +const struct vdec_common_if vdec_vp8_slice_if =3D { + .init =3D vdec_vp8_slice_init, + .decode =3D vdec_vp8_slice_decode, + .get_param =3D vdec_vp8_slice_get_param, + .deinit =3D vdec_vp8_slice_deinit, +}; diff --git a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c b/drivers= /media/platform/mediatek/vcodec/vdec_drv_if.c index 75497c2e476f..b709c7bae197 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c @@ -33,6 +33,10 @@ int vdec_if_init(struct mtk_vcodec_ctx *ctx, unsigned in= t fourcc) ctx->dec_if =3D &vdec_h264_if; ctx->hw_id =3D MTK_VDEC_CORE; break; + case V4L2_PIX_FMT_VP8_FRAME: + ctx->dec_if =3D &vdec_vp8_slice_if; + ctx->hw_id =3D MTK_VDEC_CORE; + break; case V4L2_PIX_FMT_VP8: ctx->dec_if =3D &vdec_vp8_if; ctx->hw_id =3D MTK_VDEC_CORE; diff --git a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h b/drivers= /media/platform/mediatek/vcodec/vdec_drv_if.h index f00980ee5abf..97f6e324e623 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h +++ b/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h @@ -58,6 +58,7 @@ extern const struct vdec_common_if vdec_h264_if; extern const struct vdec_common_if vdec_h264_slice_if; extern const struct vdec_common_if vdec_h264_slice_multi_if; extern const struct vdec_common_if vdec_vp8_if; +extern const struct vdec_common_if vdec_vp8_slice_if; extern const struct vdec_common_if vdec_vp9_if; =20 /** --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25590C4332F for ; Fri, 6 May 2022 09:31:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1390630AbiEFJfA (ORCPT ); Fri, 6 May 2022 05:35:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1390705AbiEFJeF (ORCPT ); Fri, 6 May 2022 05:34:05 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2E5869283; 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Fri, 6 May 2022 17:29:30 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:28 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 16/17] media: mediatek: vcodec: support stateless VP9 decoding Date: Fri, 6 May 2022 17:28:54 +0800 Message-ID: <20220506092855.22940-17-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for VP9 decoding using the stateless API, as supported by MT8192. And the drivers is lat and core architecture. Signed-off-by: Yunfei Dong Signed-off-by: George Sun --- .../media/platform/mediatek/vcodec/Kconfig | 1 + .../media/platform/mediatek/vcodec/Makefile | 1 + .../vcodec/mtk_vcodec_dec_stateless.c | 26 +- .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 1 + .../vcodec/vdec/vdec_vp9_req_lat_if.c | 2031 +++++++++++++++++ .../platform/mediatek/vcodec/vdec_drv_if.c | 4 + .../platform/mediatek/vcodec/vdec_drv_if.h | 1 + 7 files changed, 2062 insertions(+), 3 deletions(-) create mode 100644 drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_re= q_lat_if.c diff --git a/drivers/media/platform/mediatek/vcodec/Kconfig b/drivers/media= /platform/mediatek/vcodec/Kconfig index c5c76753c626..74b00eb1bc97 100644 --- a/drivers/media/platform/mediatek/vcodec/Kconfig +++ b/drivers/media/platform/mediatek/vcodec/Kconfig @@ -22,6 +22,7 @@ config VIDEO_MEDIATEK_VCODEC select VIDEO_MEDIATEK_VCODEC_VPU if VIDEO_MEDIATEK_VPU select VIDEO_MEDIATEK_VCODEC_SCP if MTK_SCP select V4L2_H264 + select V4L2_VP9 select MEDIA_CONTROLLER select MEDIA_CONTROLLER_REQUEST_API help diff --git a/drivers/media/platform/mediatek/vcodec/Makefile b/drivers/medi= a/platform/mediatek/vcodec/Makefile index b457daf2d196..93e7a343b5b0 100644 --- a/drivers/media/platform/mediatek/vcodec/Makefile +++ b/drivers/media/platform/mediatek/vcodec/Makefile @@ -9,6 +9,7 @@ mtk-vcodec-dec-y :=3D vdec/vdec_h264_if.o \ vdec/vdec_vp8_if.o \ vdec/vdec_vp8_req_if.o \ vdec/vdec_vp9_if.o \ + vdec/vdec_vp9_req_lat_if.o \ vdec/vdec_h264_req_if.o \ vdec/vdec_h264_req_common.o \ vdec/vdec_h264_req_multi_if.o \ diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateles= s.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c index 8517ed4efeb5..f1a77f0a8a81 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_stateless.c @@ -91,13 +91,28 @@ static const struct mtk_stateless_control mtk_stateless= _controls[] =3D { .max =3D V4L2_MPEG_VIDEO_VP8_PROFILE_3, }, .codec_type =3D V4L2_PIX_FMT_VP8_FRAME, - } + }, + { + .cfg =3D { + .id =3D V4L2_CID_STATELESS_VP9_FRAME, + }, + .codec_type =3D V4L2_PIX_FMT_VP9_FRAME, + }, + { + .cfg =3D { + .id =3D V4L2_CID_MPEG_VIDEO_VP9_PROFILE, + .min =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .def =3D V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .max =3D V4L2_MPEG_VIDEO_VP9_PROFILE_3, + }, + .codec_type =3D V4L2_PIX_FMT_VP9_FRAME, + }, }; =20 #define NUM_CTRLS ARRAY_SIZE(mtk_stateless_controls) =20 -static struct mtk_video_fmt mtk_video_formats[4]; -static struct mtk_codec_framesizes mtk_vdec_framesizes[2]; +static struct mtk_video_fmt mtk_video_formats[5]; +static struct mtk_codec_framesizes mtk_vdec_framesizes[3]; =20 static struct mtk_video_fmt default_out_format; static struct mtk_video_fmt default_cap_format; @@ -338,6 +353,7 @@ static void mtk_vcodec_add_formats(unsigned int fourcc, switch (fourcc) { case V4L2_PIX_FMT_H264_SLICE: case V4L2_PIX_FMT_VP8_FRAME: + case V4L2_PIX_FMT_VP9_FRAME: mtk_video_formats[count_formats].fourcc =3D fourcc; mtk_video_formats[count_formats].type =3D MTK_FMT_DEC; mtk_video_formats[count_formats].num_planes =3D 1; @@ -385,6 +401,10 @@ static void mtk_vcodec_get_supported_formats(struct mt= k_vcodec_ctx *ctx) mtk_vcodec_add_formats(V4L2_PIX_FMT_VP8_FRAME, ctx); out_format_count++; } + if (ctx->dev->dec_capability & MTK_VDEC_FORMAT_VP9_FRAME) { + mtk_vcodec_add_formats(V4L2_PIX_FMT_VP9_FRAME, ctx); + out_format_count++; + } =20 if (cap_format_count) default_cap_format =3D mtk_video_formats[cap_format_count - 1]; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/driv= ers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index 2ba1c19f07b6..a29041a0b7e0 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -355,6 +355,7 @@ enum mtk_vdec_format_types { MTK_VDEC_FORMAT_MT21C =3D 0x40, MTK_VDEC_FORMAT_H264_SLICE =3D 0x100, MTK_VDEC_FORMAT_VP8_FRAME =3D 0x200, + MTK_VDEC_FORMAT_VP9_FRAME =3D 0x400, }; =20 /** diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_i= f.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c new file mode 100644 index 000000000000..3ebdb3c29e0e --- /dev/null +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c @@ -0,0 +1,2031 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: George Sun + */ + +#include +#include +#include +#include + +#include "../mtk_vcodec_util.h" +#include "../mtk_vcodec_dec.h" +#include "../mtk_vcodec_intr.h" +#include "../vdec_drv_base.h" +#include "../vdec_drv_if.h" +#include "../vdec_vpu_if.h" + +/* reset_frame_context defined in VP9 spec */ +#define VP9_RESET_FRAME_CONTEXT_NONE0 0 +#define VP9_RESET_FRAME_CONTEXT_NONE1 1 +#define VP9_RESET_FRAME_CONTEXT_SPEC 2 +#define VP9_RESET_FRAME_CONTEXT_ALL 3 + +#define VP9_TILE_BUF_SIZE 4096 +#define VP9_PROB_BUF_SIZE 2560 +#define VP9_COUNTS_BUF_SIZE 16384 + +#define HDR_FLAG(x) (!!((hdr)->flags & V4L2_VP9_FRAME_FLAG_##x)) +#define LF_FLAG(x) (!!((lf)->flags & V4L2_VP9_LOOP_FILTER_FLAG_##x)) +#define SEG_FLAG(x) (!!((seg)->flags & V4L2_VP9_SEGMENTATION_FLAG_##x)) +#define VP9_BAND_6(band) ((band) =3D=3D 0 ? 3 : 6) + +/* + * struct vdec_vp9_slice_frame_ctx - vp9 prob tables footprint + */ +struct vdec_vp9_slice_frame_ctx { + struct { + u8 probs[6][3]; + u8 padding[2]; + } coef_probs[4][2][2][6]; + + u8 y_mode_prob[4][16]; + u8 switch_interp_prob[4][16]; + u8 seg[32]; /* ignore */ + u8 comp_inter_prob[16]; + u8 comp_ref_prob[16]; + u8 single_ref_prob[5][2]; + u8 single_ref_prob_padding[6]; + + u8 joint[3]; + u8 joint_padding[13]; + struct { + u8 sign; + u8 classes[10]; + u8 padding[5]; + } sign_classes[2]; + struct { + u8 class0[1]; + u8 bits[10]; + u8 padding[5]; + } class0_bits[2]; + struct { + u8 class0_fp[2][3]; + u8 fp[3]; + u8 class0_hp; + u8 hp; + u8 padding[5]; + } class0_fp_hp[2]; + + u8 uv_mode_prob[10][16]; + u8 uv_mode_prob_padding[2][16]; + + u8 partition_prob[16][4]; + + u8 inter_mode_probs[7][4]; + u8 skip_probs[4]; + + u8 tx_p8x8[2][4]; + u8 tx_p16x16[2][4]; + u8 tx_p32x32[2][4]; + u8 intra_inter_prob[8]; +}; + +/* + * struct vdec_vp9_slice_frame_counts - vp9 counts tables footprint + */ +struct vdec_vp9_slice_frame_counts { + union { + struct { + u32 band_0[3]; + u32 padding0[1]; + u32 band_1_5[5][6]; + u32 padding1[2]; + } eob_branch[4][2][2]; + u32 eob_branch_space[256 * 4]; + }; + + struct { + u32 band_0[3][4]; + u32 band_1_5[5][6][4]; + } coef_probs[4][2][2]; + + u32 intra_inter[4][2]; + u32 comp_inter[5][2]; + u32 comp_inter_padding[2]; + u32 comp_ref[5][2]; + u32 comp_ref_padding[2]; + u32 single_ref[5][2][2]; + u32 inter_mode[7][4]; + u32 y_mode[4][12]; + u32 uv_mode[10][10]; + u32 partition[16][4]; + u32 switchable_interp[4][4]; + + u32 tx_p8x8[2][2]; + u32 tx_p16x16[2][4]; + u32 tx_p32x32[2][4]; + + u32 skip[3][4]; + + u32 joint[4]; + + struct { + u32 sign[2]; + u32 class0[2]; + u32 classes[12]; + u32 bits[10][2]; + u32 padding[4]; + u32 class0_fp[2][4]; + u32 fp[4]; + u32 class0_hp[2]; + u32 hp[2]; + } mvcomp[2]; + + u32 reserved[126][4]; +}; + +/** + * struct vdec_vp9_slice_counts_map - vp9 counts tables to map + * v4l2_vp9_frame_symbol_counts + * @skip: skip counts. + * @y_mode: Y prediction mode counts. + * @filter: interpolation filter counts. + * @mv_joint: motion vector joint counts. + * @sign: motion vector sign counts. + * @classes: motion vector class counts. + * @class0: motion vector class0 bit counts. + * @bits: motion vector bits counts. + * @class0_fp: motion vector class0 fractional bit counts. + * @fp: motion vector fractional bit counts. + * @class0_hp: motion vector class0 high precision fractional bit counts. + * @hp: motion vector high precision fractional bit counts. + */ +struct vdec_vp9_slice_counts_map { + u32 skip[3][2]; + u32 y_mode[4][10]; + u32 filter[4][3]; + u32 sign[2][2]; + u32 classes[2][11]; + u32 class0[2][2]; + u32 bits[2][10][2]; + u32 class0_fp[2][2][4]; + u32 fp[2][4]; + u32 class0_hp[2][2]; + u32 hp[2][2]; +}; + +/* + * struct vdec_vp9_slice_uncompressed_header - vp9 uncompressed header syn= tax + * used for decoding + */ +struct vdec_vp9_slice_uncompressed_header { + u8 profile; + u8 last_frame_type; + u8 frame_type; + + u8 last_show_frame; + u8 show_frame; + u8 error_resilient_mode; + + u8 bit_depth; + u8 padding0[1]; + u16 last_frame_width; + u16 last_frame_height; + u16 frame_width; + u16 frame_height; + + u8 intra_only; + u8 reset_frame_context; + u8 ref_frame_sign_bias[4]; + u8 allow_high_precision_mv; + u8 interpolation_filter; + + u8 refresh_frame_context; + u8 frame_parallel_decoding_mode; + u8 frame_context_idx; + + /* loop_filter_params */ + u8 loop_filter_level; + u8 loop_filter_sharpness; + u8 loop_filter_delta_enabled; + s8 loop_filter_ref_deltas[4]; + s8 loop_filter_mode_deltas[2]; + + /* quantization_params */ + u8 base_q_idx; + s8 delta_q_y_dc; + s8 delta_q_uv_dc; + s8 delta_q_uv_ac; + + /* segmentation_params */ + u8 segmentation_enabled; + u8 segmentation_update_map; + u8 segmentation_tree_probs[7]; + u8 padding1[1]; + u8 segmentation_temporal_udpate; + u8 segmentation_pred_prob[3]; + u8 segmentation_update_data; + u8 segmentation_abs_or_delta_update; + u8 feature_enabled[8]; + s16 feature_value[8][4]; + + /* tile_info */ + u8 tile_cols_log2; + u8 tile_rows_log2; + u8 padding2[2]; + + u16 uncompressed_header_size; + u16 header_size_in_bytes; + + /* LAT OUT, CORE IN */ + u32 dequant[8][4]; +}; + +/* + * struct vdec_vp9_slice_compressed_header - vp9 compressed header syntax + * used for decoding. + */ +struct vdec_vp9_slice_compressed_header { + u8 tx_mode; + u8 ref_mode; + u8 comp_fixed_ref; + u8 comp_var_ref[2]; + u8 padding[3]; +}; + +/* + * struct vdec_vp9_slice_tiles - vp9 tile syntax + */ +struct vdec_vp9_slice_tiles { + u32 size[4][64]; + u32 mi_rows[4]; + u32 mi_cols[64]; + u8 actual_rows; + u8 padding[7]; +}; + +/* + * struct vdec_vp9_slice_reference - vp9 reference frame information + */ +struct vdec_vp9_slice_reference { + u16 frame_width; + u16 frame_height; + u8 bit_depth; + u8 subsampling_x; + u8 subsampling_y; + u8 padding; +}; + +/* + * struct vdec_vp9_slice_frame - vp9 syntax used for decoding + */ +struct vdec_vp9_slice_frame { + struct vdec_vp9_slice_uncompressed_header uh; + struct vdec_vp9_slice_compressed_header ch; + struct vdec_vp9_slice_tiles tiles; + struct vdec_vp9_slice_reference ref[3]; +}; + +/* + * struct vdec_vp9_slice_init_vsi - VSI used to initialize instance + */ +struct vdec_vp9_slice_init_vsi { + unsigned int architecture; + unsigned int reserved; + u64 core_vsi; + /* default frame context's position in MicroP */ + u64 default_frame_ctx; +}; + +/* + * struct vdec_vp9_slice_mem - memory address and size + */ +struct vdec_vp9_slice_mem { + union { + u64 buf; + dma_addr_t dma_addr; + }; + union { + size_t size; + dma_addr_t dma_addr_end; + u64 padding; + }; +}; + +/* + * struct vdec_vp9_slice_bs - input buffer for decoding + */ +struct vdec_vp9_slice_bs { + struct vdec_vp9_slice_mem buf; + struct vdec_vp9_slice_mem frame; +}; + +/* + * struct vdec_vp9_slice_fb - frame buffer for decoding + */ +struct vdec_vp9_slice_fb { + struct vdec_vp9_slice_mem y; + struct vdec_vp9_slice_mem c; +}; + +/* + * struct vdec_vp9_slice_state - decoding state + */ +struct vdec_vp9_slice_state { + int err; + unsigned int full; + unsigned int timeout; + unsigned int perf; + + unsigned int crc[12]; +}; + +/** + * struct vdec_vp9_slice_vsi - exchange decoding information + * between Main CPU and MicroP + * + * @bs: input buffer + * @fb: output buffer + * @ref: 3 reference buffers + * @mv: mv working buffer + * @seg: segmentation working buffer + * @tile: tile buffer + * @prob: prob table buffer, used to set/update prob table + * @counts: counts table buffer, used to update prob table + * @ube: general buffer + * @trans: trans buffer position in general buffer + * @err_map: error buffer + * @row_info: row info buffer + * @frame: decoding syntax + * @state: decoding state + */ +struct vdec_vp9_slice_vsi { + /* used in LAT stage */ + struct vdec_vp9_slice_bs bs; + /* used in Core stage */ + struct vdec_vp9_slice_fb fb; + struct vdec_vp9_slice_fb ref[3]; + + struct vdec_vp9_slice_mem mv[2]; + struct vdec_vp9_slice_mem seg[2]; + struct vdec_vp9_slice_mem tile; + struct vdec_vp9_slice_mem prob; + struct vdec_vp9_slice_mem counts; + + /* LAT stage's output, Core stage's input */ + struct vdec_vp9_slice_mem ube; + struct vdec_vp9_slice_mem trans; + struct vdec_vp9_slice_mem err_map; + struct vdec_vp9_slice_mem row_info; + + /* decoding parameters */ + struct vdec_vp9_slice_frame frame; + + struct vdec_vp9_slice_state state; +}; + +/** + * struct vdec_vp9_slice_pfc - per-frame context that contains a local vsi. + * pass it from lat to core + * + * @vsi: local vsi. copy to/from remote vsi before/after decoding + * @ref_idx: reference buffer index + * @seq: picture sequence + * @state: decoding state + */ +struct vdec_vp9_slice_pfc { + struct vdec_vp9_slice_vsi vsi; + + u64 ref_idx[3]; + + int seq; + + /* LAT/Core CRC */ + struct vdec_vp9_slice_state state[2]; +}; + +/* + * enum vdec_vp9_slice_resolution_level + */ +enum vdec_vp9_slice_resolution_level { + VP9_RES_NONE, + VP9_RES_FHD, + VP9_RES_4K, + VP9_RES_8K, +}; + +/* + * struct vdec_vp9_slice_ref - picture's width & height should kept + * for later decoding as reference picture + */ +struct vdec_vp9_slice_ref { + unsigned int width; + unsigned int height; +}; + +/** + * struct vdec_vp9_slice_instance - represent one vp9 instance + * + * @ctx: pointer to codec's context + * @vpu: VPU instance + * @seq: global picture sequence + * @level: level of current resolution + * @width: width of last picture + * @height: height of last picture + * @frame_type: frame_type of last picture + * @irq: irq to Main CPU or MicroP + * @show_frame: show_frame of last picture + * @dpb: picture information (width/height) for reference + * @mv: mv working buffer + * @seg: segmentation working buffer + * @tile: tile buffer + * @prob: prob table buffer, used to set/update prob table + * @counts: counts table buffer, used to update prob table + * @frame_ctx: 4 frame context according to VP9 Spec + * @frame_ctx_helper: 4 frame context according to newest kernel spec + * @dirty: state of each frame context + * @init_vsi: vsi used for initialized VP9 instance + * @vsi: vsi used for decoding/flush ... + * @core_vsi: vsi used for Core stage + * @counts_map: used map to counts_helper + * @counts_helper: counts table according to newest kernel spec + */ +struct vdec_vp9_slice_instance { + struct mtk_vcodec_ctx *ctx; + struct vdec_vpu_inst vpu; + + int seq; + + enum vdec_vp9_slice_resolution_level level; + + /* for resolution change and get_pic_info */ + unsigned int width; + unsigned int height; + + /* for last_frame_type */ + unsigned int frame_type; + unsigned int irq; + + unsigned int show_frame; + + /* maintain vp9 reference frame state */ + struct vdec_vp9_slice_ref dpb[VB2_MAX_FRAME]; + + /* + * normal working buffers + * mv[0]/seg[0]/tile/prob/counts is used for LAT + * mv[1]/seg[1] is used for CORE + */ + struct mtk_vcodec_mem mv[2]; + struct mtk_vcodec_mem seg[2]; + struct mtk_vcodec_mem tile; + struct mtk_vcodec_mem prob; + struct mtk_vcodec_mem counts; + + /* 4 prob tables */ + struct vdec_vp9_slice_frame_ctx frame_ctx[4]; + /*4 helper tables */ + struct v4l2_vp9_frame_context frame_ctx_helper; + unsigned char dirty[4]; + + /* MicroP vsi */ + union { + struct vdec_vp9_slice_init_vsi *init_vsi; + struct vdec_vp9_slice_vsi *vsi; + }; + struct vdec_vp9_slice_vsi *core_vsi; + + struct vdec_vp9_slice_counts_map counts_map; + struct v4l2_vp9_frame_symbol_counts counts_helper; +}; + +/* + * all VP9 instances could share this default frame context. + */ +static struct vdec_vp9_slice_frame_ctx *vdec_vp9_slice_default_frame_ctx; +static DEFINE_MUTEX(vdec_vp9_slice_frame_ctx_lock); + +static int vdec_vp9_slice_core_decode(struct vdec_lat_buf *lat_buf); + +static int vdec_vp9_slice_init_default_frame_ctx(struct vdec_vp9_slice_ins= tance *instance) +{ + struct vdec_vp9_slice_frame_ctx *remote_frame_ctx; + struct vdec_vp9_slice_frame_ctx *frame_ctx; + struct mtk_vcodec_ctx *ctx; + struct vdec_vp9_slice_init_vsi *vsi; + int ret =3D 0; + + ctx =3D instance->ctx; + vsi =3D instance->vpu.vsi; + if (!ctx || !vsi) + return -EINVAL; + + remote_frame_ctx =3D mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, + (u32)vsi->default_frame_ctx); + if (!remote_frame_ctx) { + mtk_vcodec_err(instance, "failed to map default frame ctx\n"); + return -EINVAL; + } + + mutex_lock(&vdec_vp9_slice_frame_ctx_lock); + if (vdec_vp9_slice_default_frame_ctx) + goto out; + + frame_ctx =3D kmalloc(sizeof(*frame_ctx), GFP_KERNEL); + if (!frame_ctx) { + ret =3D -ENOMEM; + goto out; + } + + memcpy_fromio(frame_ctx, (void __iomem *)remote_frame_ctx, sizeof(*frame_= ctx)); + vdec_vp9_slice_default_frame_ctx =3D frame_ctx; + +out: + mutex_unlock(&vdec_vp9_slice_frame_ctx_lock); + + return ret; +} + +static int vdec_vp9_slice_alloc_working_buffer(struct vdec_vp9_slice_insta= nce *instance, + struct vdec_vp9_slice_vsi *vsi) +{ + struct mtk_vcodec_ctx *ctx =3D instance->ctx; + enum vdec_vp9_slice_resolution_level level; + /* super blocks */ + unsigned int max_sb_w; + unsigned int max_sb_h; + unsigned int max_w; + unsigned int max_h; + unsigned int w; + unsigned int h; + size_t size; + int ret; + int i; + + w =3D vsi->frame.uh.frame_width; + h =3D vsi->frame.uh.frame_height; + + if (w > VCODEC_DEC_4K_CODED_WIDTH || + h > VCODEC_DEC_4K_CODED_HEIGHT) { + return -EINVAL; + } else if (w > MTK_VDEC_MAX_W || h > MTK_VDEC_MAX_H) { + /* 4K */ + level =3D VP9_RES_4K; + max_w =3D VCODEC_DEC_4K_CODED_WIDTH; + max_h =3D VCODEC_DEC_4K_CODED_HEIGHT; + } else { + /* FHD */ + level =3D VP9_RES_FHD; + max_w =3D MTK_VDEC_MAX_W; + max_h =3D MTK_VDEC_MAX_H; + } + + if (level =3D=3D instance->level) + return 0; + + mtk_vcodec_debug(instance, "resolution level changed, from %u to %u, %ux%= u", + instance->level, level, w, h); + + max_sb_w =3D DIV_ROUND_UP(max_w, 64); + max_sb_h =3D DIV_ROUND_UP(max_h, 64); + ret =3D -ENOMEM; + + /* + * Lat-flush must wait core idle, otherwise core will + * use released buffers + */ + + size =3D (max_sb_w * max_sb_h + 2) * 576; + for (i =3D 0; i < 2; i++) { + if (instance->mv[i].va) + mtk_vcodec_mem_free(ctx, &instance->mv[i]); + instance->mv[i].size =3D size; + if (mtk_vcodec_mem_alloc(ctx, &instance->mv[i])) + goto err; + } + + size =3D (max_sb_w * max_sb_h * 32) + 256; + for (i =3D 0; i < 2; i++) { + if (instance->seg[i].va) + mtk_vcodec_mem_free(ctx, &instance->seg[i]); + instance->seg[i].size =3D size; + if (mtk_vcodec_mem_alloc(ctx, &instance->seg[i])) + goto err; + } + + if (!instance->tile.va) { + instance->tile.size =3D VP9_TILE_BUF_SIZE; + if (mtk_vcodec_mem_alloc(ctx, &instance->tile)) + goto err; + } + + if (!instance->prob.va) { + instance->prob.size =3D VP9_PROB_BUF_SIZE; + if (mtk_vcodec_mem_alloc(ctx, &instance->prob)) + goto err; + } + + if (!instance->counts.va) { + instance->counts.size =3D VP9_COUNTS_BUF_SIZE; + if (mtk_vcodec_mem_alloc(ctx, &instance->counts)) + goto err; + } + + instance->level =3D level; + return 0; + +err: + instance->level =3D VP9_RES_NONE; + return ret; +} + +static void vdec_vp9_slice_free_working_buffer(struct vdec_vp9_slice_insta= nce *instance) +{ + struct mtk_vcodec_ctx *ctx =3D instance->ctx; + int i; + + for (i =3D 0; i < ARRAY_SIZE(instance->mv); i++) { + if (instance->mv[i].va) + mtk_vcodec_mem_free(ctx, &instance->mv[i]); + } + for (i =3D 0; i < ARRAY_SIZE(instance->seg); i++) { + if (instance->seg[i].va) + mtk_vcodec_mem_free(ctx, &instance->seg[i]); + } + if (instance->tile.va) + mtk_vcodec_mem_free(ctx, &instance->tile); + if (instance->prob.va) + mtk_vcodec_mem_free(ctx, &instance->prob); + if (instance->counts.va) + mtk_vcodec_mem_free(ctx, &instance->counts); + + instance->level =3D VP9_RES_NONE; +} + +static void vdec_vp9_slice_vsi_from_remote(struct vdec_vp9_slice_vsi *vsi, + struct vdec_vp9_slice_vsi __iomem *remote_vsi, + int skip) +{ + struct vdec_vp9_slice_frame __iomem *rf; + struct vdec_vp9_slice_frame *f; + + /* + * compressed header + * dequant + * buffer position + * decode state + */ + if (!skip) { + rf =3D &remote_vsi->frame; + f =3D &vsi->frame; + memcpy_fromio(&f->ch,(void __iomem *) &rf->ch, sizeof(f->ch)); + memcpy_fromio(&f->uh.dequant, (void __iomem *)&rf->uh.dequant, + sizeof(f->uh.dequant)); + memcpy_fromio(&vsi->trans, (void __iomem *)&remote_vsi->trans, sizeof(vs= i->trans)); + } + + memcpy_fromio(&vsi->state, &remote_vsi->state, sizeof(vsi->state)); +} + +static void vdec_vp9_slice_vsi_to_remote(struct vdec_vp9_slice_vsi *vsi, + struct vdec_vp9_slice_vsi __iomem *remote_vsi) +{ + memcpy_toio(remote_vsi, vsi, sizeof(*vsi)); +} + +static int vdec_vp9_slice_tile_offset(int idx, int mi_num, int tile_log2) +{ + int sbs =3D (mi_num + 7) >> 3; + int offset =3D ((idx * sbs) >> tile_log2) << 3; + + return offset < mi_num ? offset : mi_num; +} + +static int vdec_vp9_slice_setup_lat_from_src_buf(struct vdec_vp9_slice_ins= tance *instance, + struct vdec_lat_buf *lat_buf) +{ + struct vb2_v4l2_buffer *src; + struct vb2_v4l2_buffer *dst; + + src =3D v4l2_m2m_next_src_buf(instance->ctx->m2m_ctx); + if (!src) + return -EINVAL; + + lat_buf->src_buf_req =3D src->vb2_buf.req_obj.req; + + dst =3D &lat_buf->ts_info; + v4l2_m2m_buf_copy_metadata(src, dst, true); + return 0; +} + +static void vdec_vp9_slice_setup_hdr(struct vdec_vp9_slice_instance *insta= nce, + struct vdec_vp9_slice_uncompressed_header *uh, + struct v4l2_ctrl_vp9_frame *hdr) +{ + int i; + + uh->profile =3D hdr->profile; + uh->last_frame_type =3D instance->frame_type; + uh->frame_type =3D !HDR_FLAG(KEY_FRAME); + uh->last_show_frame =3D instance->show_frame; + uh->show_frame =3D HDR_FLAG(SHOW_FRAME); + uh->error_resilient_mode =3D HDR_FLAG(ERROR_RESILIENT); + uh->bit_depth =3D hdr->bit_depth; + uh->last_frame_width =3D instance->width; + uh->last_frame_height =3D instance->height; + uh->frame_width =3D hdr->frame_width_minus_1 + 1; + uh->frame_height =3D hdr->frame_height_minus_1 + 1; + uh->intra_only =3D HDR_FLAG(INTRA_ONLY); + /* map v4l2 enum to values defined in VP9 spec for firmware */ + switch (hdr->reset_frame_context) { + case V4L2_VP9_RESET_FRAME_CTX_NONE: + uh->reset_frame_context =3D VP9_RESET_FRAME_CONTEXT_NONE0; + break; + case V4L2_VP9_RESET_FRAME_CTX_SPEC: + uh->reset_frame_context =3D VP9_RESET_FRAME_CONTEXT_SPEC; + break; + case V4L2_VP9_RESET_FRAME_CTX_ALL: + uh->reset_frame_context =3D VP9_RESET_FRAME_CONTEXT_ALL; + break; + default: + uh->reset_frame_context =3D VP9_RESET_FRAME_CONTEXT_NONE0; + break; + } + /* + * ref_frame_sign_bias specifies the intended direction + * of the motion vector in time for each reference frame. + * - INTRA_FRAME =3D 0, + * - LAST_FRAME =3D 1, + * - GOLDEN_FRAME =3D 2, + * - ALTREF_FRAME =3D 3, + * ref_frame_sign_bias[INTRA_FRAME] is always 0 + * and VDA only passes another 3 directions + */ + uh->ref_frame_sign_bias[0] =3D 0; + for (i =3D 0; i < 3; i++) + uh->ref_frame_sign_bias[i + 1] =3D + !!(hdr->ref_frame_sign_bias & (1 << i)); + uh->allow_high_precision_mv =3D HDR_FLAG(ALLOW_HIGH_PREC_MV); + uh->interpolation_filter =3D hdr->interpolation_filter; + uh->refresh_frame_context =3D HDR_FLAG(REFRESH_FRAME_CTX); + uh->frame_parallel_decoding_mode =3D HDR_FLAG(PARALLEL_DEC_MODE); + uh->frame_context_idx =3D hdr->frame_context_idx; + + /* tile info */ + uh->tile_cols_log2 =3D hdr->tile_cols_log2; + uh->tile_rows_log2 =3D hdr->tile_rows_log2; + + uh->uncompressed_header_size =3D hdr->uncompressed_header_size; + uh->header_size_in_bytes =3D hdr->compressed_header_size; +} + +static void vdec_vp9_slice_setup_frame_ctx(struct vdec_vp9_slice_instance = *instance, + struct vdec_vp9_slice_uncompressed_header *uh, + struct v4l2_ctrl_vp9_frame *hdr) +{ + int error_resilient_mode; + int reset_frame_context; + int key_frame; + int intra_only; + int i; + + key_frame =3D HDR_FLAG(KEY_FRAME); + intra_only =3D HDR_FLAG(INTRA_ONLY); + error_resilient_mode =3D HDR_FLAG(ERROR_RESILIENT); + reset_frame_context =3D uh->reset_frame_context; + + /* + * according to "6.2 Uncompressed header syntax" in + * "VP9 Bitstream & Decoding Process Specification", + * reset @frame_context_idx when (FrameIsIntra || error_resilient_mode) + */ + if (key_frame || intra_only || error_resilient_mode) { + /* + * @reset_frame_context specifies + * whether the frame context should be + * reset to default values: + * 0 or 1 means do not reset any frame context + * 2 resets just the context specified in the frame header + * 3 resets all contexts + */ + if (key_frame || error_resilient_mode || + reset_frame_context =3D=3D 3) { + /* use default table */ + for (i =3D 0; i < 4; i++) + instance->dirty[i] =3D 0; + } else if (reset_frame_context =3D=3D 2) { + instance->dirty[uh->frame_context_idx] =3D 0; + } + uh->frame_context_idx =3D 0; + } +} + +static void vdec_vp9_slice_setup_loop_filter(struct vdec_vp9_slice_uncompr= essed_header *uh, + struct v4l2_vp9_loop_filter *lf) +{ + int i; + + uh->loop_filter_level =3D lf->level; + uh->loop_filter_sharpness =3D lf->sharpness; + uh->loop_filter_delta_enabled =3D LF_FLAG(DELTA_ENABLED); + for (i =3D 0; i < 4; i++) + uh->loop_filter_ref_deltas[i] =3D lf->ref_deltas[i]; + for (i =3D 0; i < 2; i++) + uh->loop_filter_mode_deltas[i] =3D lf->mode_deltas[i]; +} + +static void vdec_vp9_slice_setup_quantization(struct vdec_vp9_slice_uncomp= ressed_header *uh, + struct v4l2_vp9_quantization *quant) +{ + uh->base_q_idx =3D quant->base_q_idx; + uh->delta_q_y_dc =3D quant->delta_q_y_dc; + uh->delta_q_uv_dc =3D quant->delta_q_uv_dc; + uh->delta_q_uv_ac =3D quant->delta_q_uv_ac; +} + +static void vdec_vp9_slice_setup_segmentation(struct vdec_vp9_slice_uncomp= ressed_header *uh, + struct v4l2_vp9_segmentation *seg) +{ + int i; + int j; + + uh->segmentation_enabled =3D SEG_FLAG(ENABLED); + uh->segmentation_update_map =3D SEG_FLAG(UPDATE_MAP); + for (i =3D 0; i < 7; i++) + uh->segmentation_tree_probs[i] =3D seg->tree_probs[i]; + uh->segmentation_temporal_udpate =3D SEG_FLAG(TEMPORAL_UPDATE); + for (i =3D 0; i < 3; i++) + uh->segmentation_pred_prob[i] =3D seg->pred_probs[i]; + uh->segmentation_update_data =3D SEG_FLAG(UPDATE_DATA); + uh->segmentation_abs_or_delta_update =3D SEG_FLAG(ABS_OR_DELTA_UPDATE); + for (i =3D 0; i < 8; i++) { + uh->feature_enabled[i] =3D seg->feature_enabled[i]; + for (j =3D 0; j < 4; j++) + uh->feature_value[i][j] =3D seg->feature_data[i][j]; + } +} + +static int vdec_vp9_slice_setup_tile(struct vdec_vp9_slice_vsi *vsi, + struct v4l2_ctrl_vp9_frame *hdr) +{ + unsigned int rows_log2; + unsigned int cols_log2; + unsigned int rows; + unsigned int cols; + unsigned int mi_rows; + unsigned int mi_cols; + struct vdec_vp9_slice_tiles *tiles; + int offset; + int start; + int end; + int i; + + rows_log2 =3D hdr->tile_rows_log2; + cols_log2 =3D hdr->tile_cols_log2; + rows =3D 1 << rows_log2; + cols =3D 1 << cols_log2; + tiles =3D &vsi->frame.tiles; + tiles->actual_rows =3D 0; + + if (rows > 4 || cols > 64) + return -EINVAL; + + /* setup mi rows/cols information */ + mi_rows =3D (hdr->frame_height_minus_1 + 1 + 7) >> 3; + mi_cols =3D (hdr->frame_width_minus_1 + 1 + 7) >> 3; + + for (i =3D 0; i < rows; i++) { + start =3D vdec_vp9_slice_tile_offset(i, mi_rows, rows_log2); + end =3D vdec_vp9_slice_tile_offset(i + 1, mi_rows, rows_log2); + offset =3D end - start; + tiles->mi_rows[i] =3D (offset + 7) >> 3; + if (tiles->mi_rows[i]) + tiles->actual_rows++; + } + + for (i =3D 0; i < cols; i++) { + start =3D vdec_vp9_slice_tile_offset(i, mi_cols, cols_log2); + end =3D vdec_vp9_slice_tile_offset(i + 1, mi_cols, cols_log2); + offset =3D end - start; + tiles->mi_cols[i] =3D (offset + 7) >> 3; + } + + return 0; +} + +static void vdec_vp9_slice_setup_state(struct vdec_vp9_slice_vsi *vsi) +{ + memset(&vsi->state, 0, sizeof(vsi->state)); +} + +static void vdec_vp9_slice_setup_ref_idx(struct vdec_vp9_slice_pfc *pfc, + struct v4l2_ctrl_vp9_frame *hdr) +{ + pfc->ref_idx[0] =3D hdr->last_frame_ts; + pfc->ref_idx[1] =3D hdr->golden_frame_ts; + pfc->ref_idx[2] =3D hdr->alt_frame_ts; +} + +static int vdec_vp9_slice_setup_pfc(struct vdec_vp9_slice_instance *instan= ce, + struct vdec_vp9_slice_pfc *pfc) +{ + struct v4l2_ctrl_vp9_frame *hdr; + struct vdec_vp9_slice_uncompressed_header *uh; + struct v4l2_ctrl *hdr_ctrl; + struct vdec_vp9_slice_vsi *vsi; + int ret; + + /* frame header */ + hdr_ctrl =3D v4l2_ctrl_find(&instance->ctx->ctrl_hdl, V4L2_CID_STATELESS_= VP9_FRAME); + if (!hdr_ctrl || !hdr_ctrl->p_cur.p) + return -EINVAL; + + hdr =3D hdr_ctrl->p_cur.p; + vsi =3D &pfc->vsi; + uh =3D &vsi->frame.uh; + + /* setup vsi information */ + vdec_vp9_slice_setup_hdr(instance, uh, hdr); + vdec_vp9_slice_setup_frame_ctx(instance, uh, hdr); + vdec_vp9_slice_setup_loop_filter(uh, &hdr->lf); + vdec_vp9_slice_setup_quantization(uh, &hdr->quant); + vdec_vp9_slice_setup_segmentation(uh, &hdr->seg); + ret =3D vdec_vp9_slice_setup_tile(vsi, hdr); + if (ret) + return ret; + vdec_vp9_slice_setup_state(vsi); + + /* core stage needs buffer index to get ref y/c ... */ + vdec_vp9_slice_setup_ref_idx(pfc, hdr); + + pfc->seq =3D instance->seq; + instance->seq++; + + return 0; +} + +static int vdec_vp9_slice_setup_lat_buffer(struct vdec_vp9_slice_instance = *instance, + struct vdec_vp9_slice_vsi *vsi, + struct mtk_vcodec_mem *bs, + struct vdec_lat_buf *lat_buf) +{ + int i; + + vsi->bs.buf.dma_addr =3D bs->dma_addr; + vsi->bs.buf.size =3D bs->size; + vsi->bs.frame.dma_addr =3D bs->dma_addr; + vsi->bs.frame.size =3D bs->size; + + for (i =3D 0; i < 2; i++) { + vsi->mv[i].dma_addr =3D instance->mv[i].dma_addr; + vsi->mv[i].size =3D instance->mv[i].size; + } + for (i =3D 0; i < 2; i++) { + vsi->seg[i].dma_addr =3D instance->seg[i].dma_addr; + vsi->seg[i].size =3D instance->seg[i].size; + } + vsi->tile.dma_addr =3D instance->tile.dma_addr; + vsi->tile.size =3D instance->tile.size; + vsi->prob.dma_addr =3D instance->prob.dma_addr; + vsi->prob.size =3D instance->prob.size; + vsi->counts.dma_addr =3D instance->counts.dma_addr; + vsi->counts.size =3D instance->counts.size; + + vsi->ube.dma_addr =3D lat_buf->ctx->msg_queue.wdma_addr.dma_addr; + vsi->ube.size =3D lat_buf->ctx->msg_queue.wdma_addr.size; + vsi->trans.dma_addr =3D lat_buf->ctx->msg_queue.wdma_wptr_addr; + /* used to store trans end */ + vsi->trans.dma_addr_end =3D lat_buf->ctx->msg_queue.wdma_rptr_addr; + vsi->err_map.dma_addr =3D lat_buf->wdma_err_addr.dma_addr; + vsi->err_map.size =3D lat_buf->wdma_err_addr.size; + + vsi->row_info.buf =3D 0; + vsi->row_info.size =3D 0; + + return 0; +} + +static int vdec_vp9_slice_setup_prob_buffer(struct vdec_vp9_slice_instance= *instance, + struct vdec_vp9_slice_vsi *vsi) +{ + struct vdec_vp9_slice_frame_ctx *frame_ctx; + struct vdec_vp9_slice_uncompressed_header *uh; + + uh =3D &vsi->frame.uh; + + mtk_vcodec_debug(instance, "ctx dirty %u idx %d\n", + instance->dirty[uh->frame_context_idx], + uh->frame_context_idx); + + if (instance->dirty[uh->frame_context_idx]) + frame_ctx =3D &instance->frame_ctx[uh->frame_context_idx]; + else + frame_ctx =3D vdec_vp9_slice_default_frame_ctx; + memcpy(instance->prob.va, frame_ctx, sizeof(*frame_ctx)); + + return 0; +} + +static void vdec_vp9_slice_setup_seg_buffer(struct vdec_vp9_slice_instance= *instance, + struct vdec_vp9_slice_vsi *vsi, + struct mtk_vcodec_mem *buf) +{ + struct vdec_vp9_slice_uncompressed_header *uh; + + /* reset segment buffer */ + uh =3D &vsi->frame.uh; + if (uh->frame_type =3D=3D 0 || + uh->intra_only || + uh->error_resilient_mode || + uh->frame_width !=3D instance->width || + uh->frame_height !=3D instance->height) { + mtk_vcodec_debug(instance, "reset seg\n"); + memset(buf->va, 0, buf->size); + } +} + +/* + * parse tiles according to `6.4 Decode tiles syntax` + * in "vp9-bitstream-specification" + * + * frame contains uncompress header, compressed header and several tiles. + * this function parses tiles' position and size, stores them to tile buff= er + * for decoding. + */ +static int vdec_vp9_slice_setup_tile_buffer(struct vdec_vp9_slice_instance= *instance, + struct vdec_vp9_slice_vsi *vsi, + struct mtk_vcodec_mem *bs) +{ + struct vdec_vp9_slice_uncompressed_header *uh; + unsigned int rows_log2; + unsigned int cols_log2; + unsigned int rows; + unsigned int cols; + unsigned int mi_row; + unsigned int mi_col; + unsigned int offset; + unsigned int pa; + unsigned int size; + struct vdec_vp9_slice_tiles *tiles; + unsigned char *pos; + unsigned char *end; + unsigned char *va; + unsigned int *tb; + int i; + int j; + + uh =3D &vsi->frame.uh; + rows_log2 =3D uh->tile_rows_log2; + cols_log2 =3D uh->tile_cols_log2; + rows =3D 1 << rows_log2; + cols =3D 1 << cols_log2; + + if (rows > 4 || cols > 64) { + mtk_vcodec_err(instance, "tile_rows %u tile_cols %u\n", + rows, cols); + return -EINVAL; + } + + offset =3D uh->uncompressed_header_size + + uh->header_size_in_bytes; + if (bs->size <=3D offset) { + mtk_vcodec_err(instance, "bs size %zu tile offset %u\n", + bs->size, offset); + return -EINVAL; + } + + tiles =3D &vsi->frame.tiles; + /* setup tile buffer */ + + va =3D (unsigned char *)bs->va; + pos =3D va + offset; + end =3D va + bs->size; + /* truncated */ + pa =3D (unsigned int)bs->dma_addr + offset; + tb =3D instance->tile.va; + for (i =3D 0; i < rows; i++) { + for (j =3D 0; j < cols; j++) { + if (i =3D=3D rows - 1 && + j =3D=3D cols - 1) { + size =3D (unsigned int)(end - pos); + } else { + if (end - pos < 4) + return -EINVAL; + + size =3D (pos[0] << 24) | (pos[1] << 16) | + (pos[2] << 8) | pos[3]; + pos +=3D 4; + pa +=3D 4; + offset +=3D 4; + if (end - pos < size) + return -EINVAL; + } + tiles->size[i][j] =3D size; + if (tiles->mi_rows[i]) { + *tb++ =3D (size << 3) + ((offset << 3) & 0x7f); + *tb++ =3D pa & ~0xf; + *tb++ =3D (pa << 3) & 0x7f; + mi_row =3D (tiles->mi_rows[i] - 1) & 0x1ff; + mi_col =3D (tiles->mi_cols[j] - 1) & 0x3f; + *tb++ =3D (mi_row << 6) + mi_col; + } + pos +=3D size; + pa +=3D size; + offset +=3D size; + } + } + + return 0; +} + +static int vdec_vp9_slice_setup_lat(struct vdec_vp9_slice_instance *instan= ce, + struct mtk_vcodec_mem *bs, + struct vdec_lat_buf *lat_buf, + struct vdec_vp9_slice_pfc *pfc) +{ + struct vdec_vp9_slice_vsi *vsi =3D &pfc->vsi; + int ret; + + ret =3D vdec_vp9_slice_setup_lat_from_src_buf(instance, lat_buf); + if (ret) + goto err; + + ret =3D vdec_vp9_slice_setup_pfc(instance, pfc); + if (ret) + goto err; + + ret =3D vdec_vp9_slice_alloc_working_buffer(instance, vsi); + if (ret) + goto err; + + ret =3D vdec_vp9_slice_setup_lat_buffer(instance, vsi, bs, lat_buf); + if (ret) + goto err; + + vdec_vp9_slice_setup_seg_buffer(instance, vsi, &instance->seg[0]); + + /* setup prob/tile buffers for LAT */ + + ret =3D vdec_vp9_slice_setup_prob_buffer(instance, vsi); + if (ret) + goto err; + + ret =3D vdec_vp9_slice_setup_tile_buffer(instance, vsi, bs); + if (ret) + goto err; + + return 0; + +err: + return ret; +} + +static +void vdec_vp9_slice_map_counts_eob_coef(unsigned int i, unsigned int j, un= signed int k, + struct vdec_vp9_slice_frame_counts *counts, + struct v4l2_vp9_frame_symbol_counts *counts_helper) +{ + u32 l =3D 0, m; + + /* + * helper eo -> mtk eo + * helpre e1 -> mtk c3 + * helper c0 -> c0 + * helper c1 -> c1 + * helper c2 -> c2 + */ + for (m =3D 0; m < 3; m++) { + counts_helper->coeff[i][j][k][l][m] =3D + (u32 (*)[3]) & counts->coef_probs[i][j][k].band_0[m]; + counts_helper->eob[i][j][k][l][m][0] =3D + &counts->eob_branch[i][j][k].band_0[m]; + counts_helper->eob[i][j][k][l][m][1] =3D + &counts->coef_probs[i][j][k].band_0[m][3]; + } + + for (l =3D 1; l < 6; l++) { + for (m =3D 0; m < 6; m++) { + counts_helper->coeff[i][j][k][l][m] =3D + (u32 (*)[3]) & counts->coef_probs[i][j][k].band_1_5[l - 1][m]; + counts_helper->eob[i][j][k][l][m][0] =3D + &counts->eob_branch[i][j][k].band_1_5[l - 1][m]; + counts_helper->eob[i][j][k][l][m][1] =3D + &counts->coef_probs[i][j][k].band_1_5[l - 1][m][3]; + } + } +} + +static void vdec_vp9_slice_counts_map_helper(struct vdec_vp9_slice_counts_= map *counts_map, + struct vdec_vp9_slice_frame_counts *counts, + struct v4l2_vp9_frame_symbol_counts *counts_helper) +{ + int i, j, k; + + counts_helper->partition =3D &counts->partition; + counts_helper->intra_inter =3D &counts->intra_inter; + counts_helper->tx32p =3D &counts->tx_p32x32; + counts_helper->tx16p =3D &counts->tx_p16x16; + counts_helper->tx8p =3D &counts->tx_p8x8; + counts_helper->uv_mode =3D &counts->uv_mode; + + counts_helper->comp =3D &counts->comp_inter; + counts_helper->comp_ref =3D &counts->comp_ref; + counts_helper->single_ref =3D &counts->single_ref; + counts_helper->mv_mode =3D &counts->inter_mode; + counts_helper->mv_joint =3D &counts->joint; + + for (i =3D 0; i < ARRAY_SIZE(counts_map->skip); i++) + memcpy(counts_map->skip[i], counts->skip[i], + sizeof(counts_map->skip[0])); + counts_helper->skip =3D &counts_map->skip; + + for (i =3D 0; i < ARRAY_SIZE(counts_map->y_mode); i++) + memcpy(counts_map->y_mode[i], counts->y_mode[i], + sizeof(counts_map->y_mode[0])); + counts_helper->y_mode =3D &counts_map->y_mode; + + for (i =3D 0; i < ARRAY_SIZE(counts_map->filter); i++) + memcpy(counts_map->filter[i], counts->switchable_interp[i], + sizeof(counts_map->filter[0])); + counts_helper->filter =3D &counts_map->filter; + + for (i =3D 0; i < ARRAY_SIZE(counts_map->sign); i++) + memcpy(counts_map->sign[i], counts->mvcomp[i].sign, + sizeof(counts_map->sign[0])); + counts_helper->sign =3D &counts_map->sign; + + for (i =3D 0; i < ARRAY_SIZE(counts_map->classes); i++) + memcpy(counts_map->classes[i], counts->mvcomp[i].classes, + sizeof(counts_map->classes[0])); + counts_helper->classes =3D &counts_map->classes; + + for (i =3D 0; i < ARRAY_SIZE(counts_map->class0); i++) + memcpy(counts_map->class0[i], counts->mvcomp[i].class0, + sizeof(counts_map->class0[0])); + counts_helper->class0 =3D &counts_map->class0; + + for (i =3D 0; i < ARRAY_SIZE(counts_map->bits); i++) + for (j =3D 0; j < ARRAY_SIZE(counts_map->bits[0]); j++) + memcpy(counts_map->bits[i][j], counts->mvcomp[i].bits[j], + sizeof(counts_map->bits[0][0])); + counts_helper->bits =3D &counts_map->bits; + + for (i =3D 0; i < ARRAY_SIZE(counts_map->class0_fp); i++) + for (j =3D 0; j < ARRAY_SIZE(counts_map->class0_fp[0]); j++) + memcpy(counts_map->class0_fp[i][j], counts->mvcomp[i].class0_fp[j], + sizeof(counts_map->class0_fp[0][0])); + counts_helper->class0_fp =3D &counts_map->class0_fp; + + for (i =3D 0; i < ARRAY_SIZE(counts_map->fp); i++) + memcpy(counts_map->fp[i], counts->mvcomp[i].fp, + sizeof(counts_map->fp[0])); + counts_helper->fp =3D &counts_map->fp; + + for (i =3D 0; i < ARRAY_SIZE(counts_map->class0_hp); i++) + memcpy(counts_map->class0_hp[i], counts->mvcomp[i].class0_hp, + sizeof(counts_map->class0_hp[0])); + counts_helper->class0_hp =3D &counts_map->class0_hp; + + for (i =3D 0; i < ARRAY_SIZE(counts_map->hp); i++) + memcpy(counts_map->hp[i], counts->mvcomp[i].hp, sizeof(counts_map->hp[0]= )); + + counts_helper->hp =3D &counts_map->hp; + + for (i =3D 0; i < 4; i++) + for (j =3D 0; j < 2; j++) + for (k =3D 0; k < 2; k++) + vdec_vp9_slice_map_counts_eob_coef(i, j, k, counts, counts_helper); +} + +static void vdec_vp9_slice_map_to_coef(unsigned int i, unsigned int j, uns= igned int k, + struct vdec_vp9_slice_frame_ctx *frame_ctx, + struct v4l2_vp9_frame_context *frame_ctx_helper) +{ + u32 l, m; + + for (l =3D 0; l < ARRAY_SIZE(frame_ctx_helper->coef[0][0][0]); l++) { + for (m =3D 0; m < VP9_BAND_6(l); m++) { + memcpy(frame_ctx_helper->coef[i][j][k][l][m], + frame_ctx->coef_probs[i][j][k][l].probs[m], + sizeof(frame_ctx_helper->coef[i][j][k][l][0])); + } + } +} + +static void vdec_vp9_slice_map_from_coef(unsigned int i, unsigned int j, u= nsigned int k, + struct vdec_vp9_slice_frame_ctx *frame_ctx, + struct v4l2_vp9_frame_context *frame_ctx_helper) +{ + u32 l, m; + + for (l =3D 0; l < ARRAY_SIZE(frame_ctx_helper->coef[0][0][0]); l++) { + for (m =3D 0; m < VP9_BAND_6(l); m++) { + memcpy(frame_ctx->coef_probs[i][j][k][l].probs[m], + frame_ctx_helper->coef[i][j][k][l][m], + sizeof(frame_ctx_helper->coef[i][j][k][l][0])); + } + } +} + +static +void vdec_vp9_slice_framectx_map_helper(bool frame_is_intra, + struct vdec_vp9_slice_frame_ctx *pre_frame_ctx, + struct vdec_vp9_slice_frame_ctx *frame_ctx, + struct v4l2_vp9_frame_context *frame_ctx_helper) +{ + struct v4l2_vp9_frame_mv_context *mv =3D &frame_ctx_helper->mv; + u32 i, j, k; + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->coef); i++) + for (j =3D 0; j < ARRAY_SIZE(frame_ctx_helper->coef[0]); j++) + for (k =3D 0; k < ARRAY_SIZE(frame_ctx_helper->coef[0][0]); k++) + vdec_vp9_slice_map_to_coef(i, j, k, pre_frame_ctx, + frame_ctx_helper); + + /* + * use previous prob when frame is not intra or + * we should use the prob updated by the compressed header parse + */ + if (!frame_is_intra) + frame_ctx =3D pre_frame_ctx; + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->tx8); i++) + memcpy(frame_ctx_helper->tx8[i], frame_ctx->tx_p8x8[i], + sizeof(frame_ctx_helper->tx8[0])); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->tx16); i++) + memcpy(frame_ctx_helper->tx16[i], frame_ctx->tx_p16x16[i], + sizeof(frame_ctx_helper->tx16[0])); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->tx32); i++) + memcpy(frame_ctx_helper->tx32[i], frame_ctx->tx_p32x32[i], + sizeof(frame_ctx_helper->tx32[0])); + + memcpy(frame_ctx_helper->skip, frame_ctx->skip_probs, sizeof(frame_ctx_he= lper->skip)); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->inter_mode); i++) + memcpy(frame_ctx_helper->inter_mode[i], frame_ctx->inter_mode_probs[i], + sizeof(frame_ctx_helper->inter_mode[0])); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->interp_filter); i++) + memcpy(frame_ctx_helper->interp_filter[i], frame_ctx->switch_interp_prob= [i], + sizeof(frame_ctx_helper->interp_filter[0])); + + memcpy(frame_ctx_helper->is_inter, frame_ctx->intra_inter_prob, + sizeof(frame_ctx_helper->is_inter)); + + memcpy(frame_ctx_helper->comp_mode, frame_ctx->comp_inter_prob, + sizeof(frame_ctx_helper->comp_mode)); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->single_ref); i++) + memcpy(frame_ctx_helper->single_ref[i], frame_ctx->single_ref_prob[i], + sizeof(frame_ctx_helper->single_ref[0])); + + memcpy(frame_ctx_helper->comp_ref, frame_ctx->comp_ref_prob, + sizeof(frame_ctx_helper->comp_ref)); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->y_mode); i++) + memcpy(frame_ctx_helper->y_mode[i], frame_ctx->y_mode_prob[i], + sizeof(frame_ctx_helper->y_mode[0])); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->uv_mode); i++) + memcpy(frame_ctx_helper->uv_mode[i], frame_ctx->uv_mode_prob[i], + sizeof(frame_ctx_helper->uv_mode[0])); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->partition); i++) + memcpy(frame_ctx_helper->partition[i], frame_ctx->partition_prob[i], + sizeof(frame_ctx_helper->partition[0])); + + memcpy(mv->joint, frame_ctx->joint, sizeof(mv->joint)); + + for (i =3D 0; i < ARRAY_SIZE(mv->sign); i++) + mv->sign[i] =3D frame_ctx->sign_classes[i].sign; + + for (i =3D 0; i < ARRAY_SIZE(mv->classes); i++) + memcpy(mv->classes[i], frame_ctx->sign_classes[i].classes, + sizeof(mv->classes[i])); + + for (i =3D 0; i < ARRAY_SIZE(mv->class0_bit); i++) + mv->class0_bit[i] =3D frame_ctx->class0_bits[i].class0[0]; + + for (i =3D 0; i < ARRAY_SIZE(mv->bits); i++) + memcpy(mv->bits[i], frame_ctx->class0_bits[i].bits, sizeof(mv->bits[0])); + + for (i =3D 0; i < ARRAY_SIZE(mv->class0_fr); i++) + for (j =3D 0; j < ARRAY_SIZE(mv->class0_fr[0]); j++) + memcpy(mv->class0_fr[i][j], frame_ctx->class0_fp_hp[i].class0_fp[j], + sizeof(mv->class0_fr[0][0])); + + for (i =3D 0; i < ARRAY_SIZE(mv->fr); i++) + memcpy(mv->fr[i], frame_ctx->class0_fp_hp[i].fp, sizeof(mv->fr[0])); + + for (i =3D 0; i < ARRAY_SIZE(mv->class0_hp); i++) + mv->class0_hp[i] =3D frame_ctx->class0_fp_hp[i].class0_hp; + + for (i =3D 0; i < ARRAY_SIZE(mv->hp); i++) + mv->hp[i] =3D frame_ctx->class0_fp_hp[i].hp; +} + +static void vdec_vp9_slice_helper_map_framectx(struct v4l2_vp9_frame_conte= xt *frame_ctx_helper, + struct vdec_vp9_slice_frame_ctx *frame_ctx) +{ + struct v4l2_vp9_frame_mv_context *mv =3D &frame_ctx_helper->mv; + u32 i, j, k; + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->tx8); i++) + memcpy(frame_ctx->tx_p8x8[i], frame_ctx_helper->tx8[i], + sizeof(frame_ctx_helper->tx8[0])); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->tx16); i++) + memcpy(frame_ctx->tx_p16x16[i], frame_ctx_helper->tx16[i], + sizeof(frame_ctx_helper->tx16[0])); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->tx32); i++) + memcpy(frame_ctx->tx_p32x32[i], frame_ctx_helper->tx32[i], + sizeof(frame_ctx_helper->tx32[0])); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->coef); i++) + for (j =3D 0; j < ARRAY_SIZE(frame_ctx_helper->coef[0]); j++) + for (k =3D 0; k < ARRAY_SIZE(frame_ctx_helper->coef[0][0]); k++) + vdec_vp9_slice_map_from_coef(i, j, k, frame_ctx, + frame_ctx_helper); + + memcpy(frame_ctx->skip_probs, frame_ctx_helper->skip, sizeof(frame_ctx_he= lper->skip)); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->inter_mode); i++) + memcpy(frame_ctx->inter_mode_probs[i], frame_ctx_helper->inter_mode[i], + sizeof(frame_ctx_helper->inter_mode[0])); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->interp_filter); i++) + memcpy(frame_ctx->switch_interp_prob[i], frame_ctx_helper->interp_filter= [i], + sizeof(frame_ctx_helper->interp_filter[0])); + + memcpy(frame_ctx->intra_inter_prob, frame_ctx_helper->is_inter, + sizeof(frame_ctx_helper->is_inter)); + + memcpy(frame_ctx->comp_inter_prob, frame_ctx_helper->comp_mode, + sizeof(frame_ctx_helper->comp_mode)); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->single_ref); i++) + memcpy(frame_ctx->single_ref_prob[i], frame_ctx_helper->single_ref[i], + sizeof(frame_ctx_helper->single_ref[0])); + + memcpy(frame_ctx->comp_ref_prob, frame_ctx_helper->comp_ref, + sizeof(frame_ctx_helper->comp_ref)); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->y_mode); i++) + memcpy(frame_ctx->y_mode_prob[i], frame_ctx_helper->y_mode[i], + sizeof(frame_ctx_helper->y_mode[0])); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->uv_mode); i++) + memcpy(frame_ctx->uv_mode_prob[i], frame_ctx_helper->uv_mode[i], + sizeof(frame_ctx_helper->uv_mode[0])); + + for (i =3D 0; i < ARRAY_SIZE(frame_ctx_helper->partition); i++) + memcpy(frame_ctx->partition_prob[i], frame_ctx_helper->partition[i], + sizeof(frame_ctx_helper->partition[0])); + + memcpy(frame_ctx->joint, mv->joint, sizeof(mv->joint)); + + for (i =3D 0; i < ARRAY_SIZE(mv->sign); i++) + frame_ctx->sign_classes[i].sign =3D mv->sign[i]; + + for (i =3D 0; i < ARRAY_SIZE(mv->classes); i++) + memcpy(frame_ctx->sign_classes[i].classes, mv->classes[i], + sizeof(mv->classes[i])); + + for (i =3D 0; i < ARRAY_SIZE(mv->class0_bit); i++) + frame_ctx->class0_bits[i].class0[0] =3D mv->class0_bit[i]; + + for (i =3D 0; i < ARRAY_SIZE(mv->bits); i++) + memcpy(frame_ctx->class0_bits[i].bits, mv->bits[i], sizeof(mv->bits[0])); + + for (i =3D 0; i < ARRAY_SIZE(mv->class0_fr); i++) + for (j =3D 0; j < ARRAY_SIZE(mv->class0_fr[0]); j++) + memcpy(frame_ctx->class0_fp_hp[i].class0_fp[j], mv->class0_fr[i][j], + sizeof(mv->class0_fr[0][0])); + + for (i =3D 0; i < ARRAY_SIZE(mv->fr); i++) + memcpy(frame_ctx->class0_fp_hp[i].fp, mv->fr[i], sizeof(mv->fr[0])); + + for (i =3D 0; i < ARRAY_SIZE(mv->class0_hp); i++) + frame_ctx->class0_fp_hp[i].class0_hp =3D mv->class0_hp[i]; + + for (i =3D 0; i < ARRAY_SIZE(mv->hp); i++) + frame_ctx->class0_fp_hp[i].hp =3D mv->hp[i]; +} + +static int vdec_vp9_slice_update_prob(struct vdec_vp9_slice_instance *inst= ance, + struct vdec_vp9_slice_vsi *vsi) +{ + struct vdec_vp9_slice_frame_ctx *pre_frame_ctx; + struct v4l2_vp9_frame_context *pre_frame_ctx_helper; + struct vdec_vp9_slice_frame_ctx *frame_ctx; + struct vdec_vp9_slice_frame_counts *counts; + struct v4l2_vp9_frame_symbol_counts *counts_helper; + struct vdec_vp9_slice_uncompressed_header *uh; + bool frame_is_intra; + bool use_128; + + uh =3D &vsi->frame.uh; + pre_frame_ctx =3D &instance->frame_ctx[uh->frame_context_idx]; + pre_frame_ctx_helper =3D &instance->frame_ctx_helper; + frame_ctx =3D (struct vdec_vp9_slice_frame_ctx *)instance->prob.va; + counts =3D (struct vdec_vp9_slice_frame_counts *)instance->counts.va; + counts_helper =3D &instance->counts_helper; + + if (!uh->refresh_frame_context) + return 0; + + if (!uh->frame_parallel_decoding_mode) { + vdec_vp9_slice_counts_map_helper(&instance->counts_map, counts, counts_h= elper); + + frame_is_intra =3D !vsi->frame.uh.frame_type || vsi->frame.uh.intra_only; + /* check default prob */ + if (!instance->dirty[uh->frame_context_idx]) + vdec_vp9_slice_framectx_map_helper(frame_is_intra, + vdec_vp9_slice_default_frame_ctx, + frame_ctx, + pre_frame_ctx_helper); + else + vdec_vp9_slice_framectx_map_helper(frame_is_intra, + pre_frame_ctx, + frame_ctx, + pre_frame_ctx_helper); + + use_128 =3D !frame_is_intra && !vsi->frame.uh.last_frame_type; + v4l2_vp9_adapt_coef_probs(pre_frame_ctx_helper, + counts_helper, + use_128, + frame_is_intra); + if (!frame_is_intra) + v4l2_vp9_adapt_noncoef_probs(pre_frame_ctx_helper, + counts_helper, + V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE, + vsi->frame.uh.interpolation_filter, + vsi->frame.ch.tx_mode, + vsi->frame.uh.allow_high_precision_mv ? + V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV : 0); + vdec_vp9_slice_helper_map_framectx(pre_frame_ctx_helper, pre_frame_ctx); + } else { + memcpy(pre_frame_ctx, frame_ctx, sizeof(*frame_ctx)); + } + + instance->dirty[uh->frame_context_idx] =3D 1; + + return 0; +} + +static int vdec_vp9_slice_update_lat(struct vdec_vp9_slice_instance *insta= nce, + struct vdec_lat_buf *lat_buf, + struct vdec_vp9_slice_pfc *pfc) +{ + struct vdec_vp9_slice_vsi *vsi; + + vsi =3D &pfc->vsi; + memcpy(&pfc->state[0], &vsi->state, sizeof(vsi->state)); + + mtk_vcodec_debug(instance, "Frame %u LAT CRC 0x%08x %lx %lx\n", + pfc->seq, vsi->state.crc[0], + (unsigned long)vsi->trans.dma_addr, + (unsigned long)vsi->trans.dma_addr_end); + + /* buffer full, need to re-decode */ + if (vsi->state.full) { + /* buffer not enough */ + if (vsi->trans.dma_addr_end - vsi->trans.dma_addr =3D=3D + vsi->ube.size) + return -ENOMEM; + return -EAGAIN; + } + + vdec_vp9_slice_update_prob(instance, vsi); + + instance->width =3D vsi->frame.uh.frame_width; + instance->height =3D vsi->frame.uh.frame_height; + instance->frame_type =3D vsi->frame.uh.frame_type; + instance->show_frame =3D vsi->frame.uh.show_frame; + + return 0; +} + +static int vdec_vp9_slice_setup_core_to_dst_buf(struct vdec_vp9_slice_inst= ance *instance, + struct vdec_lat_buf *lat_buf) +{ + struct vb2_v4l2_buffer *dst; + + dst =3D v4l2_m2m_next_dst_buf(instance->ctx->m2m_ctx); + if (!dst) + return -EINVAL; + + v4l2_m2m_buf_copy_metadata(&lat_buf->ts_info, dst, true); + return 0; +} + +static int vdec_vp9_slice_setup_core_buffer(struct vdec_vp9_slice_instance= *instance, + struct vdec_vp9_slice_pfc *pfc, + struct vdec_vp9_slice_vsi *vsi, + struct vdec_fb *fb, + struct vdec_lat_buf *lat_buf) +{ + struct vb2_buffer *vb; + struct vb2_queue *vq; + struct vdec_vp9_slice_reference *ref; + int plane; + int size; + int idx; + int w; + int h; + int i; + + plane =3D instance->ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes; + w =3D vsi->frame.uh.frame_width; + h =3D vsi->frame.uh.frame_height; + size =3D ALIGN(w, 64) * ALIGN(h, 64); + + /* frame buffer */ + vsi->fb.y.dma_addr =3D fb->base_y.dma_addr; + if (plane =3D=3D 1) + vsi->fb.c.dma_addr =3D fb->base_y.dma_addr + size; + else + vsi->fb.c.dma_addr =3D fb->base_c.dma_addr; + + /* reference buffers */ + vq =3D v4l2_m2m_get_vq(instance->ctx->m2m_ctx, + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + if (!vq) + return -EINVAL; + + /* get current output buffer */ + vb =3D &v4l2_m2m_next_dst_buf(instance->ctx->m2m_ctx)->vb2_buf; + if (!vb) + return -EINVAL; + + /* update internal buffer's width/height */ + for (i =3D 0; i < vq->num_buffers; i++) { + if (vb =3D=3D vq->bufs[i]) { + instance->dpb[i].width =3D w; + instance->dpb[i].height =3D h; + break; + } + } + + /* + * get buffer's width/height from instance + * get buffer address from vb2buf + */ + for (i =3D 0; i < 3; i++) { + ref =3D &vsi->frame.ref[i]; + idx =3D vb2_find_timestamp(vq, pfc->ref_idx[i], 0); + if (idx < 0) { + ref->frame_width =3D w; + ref->frame_height =3D h; + memset(&vsi->ref[i], 0, sizeof(vsi->ref[i])); + } else { + ref->frame_width =3D instance->dpb[idx].width; + ref->frame_height =3D instance->dpb[idx].height; + vb =3D vq->bufs[idx]; + vsi->ref[i].y.dma_addr =3D + vb2_dma_contig_plane_dma_addr(vb, 0); + if (plane =3D=3D 1) + vsi->ref[i].c.dma_addr =3D + vsi->ref[i].y.dma_addr + size; + else + vsi->ref[i].c.dma_addr =3D + vb2_dma_contig_plane_dma_addr(vb, 1); + } + } + + return 0; +} + +static int vdec_vp9_slice_setup_core(struct vdec_vp9_slice_instance *insta= nce, + struct vdec_fb *fb, + struct vdec_lat_buf *lat_buf, + struct vdec_vp9_slice_pfc *pfc) +{ + struct vdec_vp9_slice_vsi *vsi =3D &pfc->vsi; + int ret; + + vdec_vp9_slice_setup_state(vsi); + + ret =3D vdec_vp9_slice_setup_core_to_dst_buf(instance, lat_buf); + if (ret) + goto err; + + ret =3D vdec_vp9_slice_setup_core_buffer(instance, pfc, vsi, fb, lat_buf); + if (ret) + goto err; + + vdec_vp9_slice_setup_seg_buffer(instance, vsi, &instance->seg[1]); + + return 0; + +err: + return ret; +} + +static int vdec_vp9_slice_update_core(struct vdec_vp9_slice_instance *inst= ance, + struct vdec_lat_buf *lat_buf, + struct vdec_vp9_slice_pfc *pfc) +{ + struct vdec_vp9_slice_vsi *vsi; + + vsi =3D &pfc->vsi; + memcpy(&pfc->state[1], &vsi->state, sizeof(vsi->state)); + + mtk_vcodec_debug(instance, "Frame %u Y_CRC %08x %08x %08x %08x\n", + pfc->seq, + vsi->state.crc[0], vsi->state.crc[1], + vsi->state.crc[2], vsi->state.crc[3]); + mtk_vcodec_debug(instance, "Frame %u C_CRC %08x %08x %08x %08x\n", + pfc->seq, + vsi->state.crc[4], vsi->state.crc[5], + vsi->state.crc[6], vsi->state.crc[7]); + + return 0; +} + +static int vdec_vp9_slice_init(struct mtk_vcodec_ctx *ctx) +{ + struct vdec_vp9_slice_instance *instance; + struct vdec_vp9_slice_init_vsi *vsi; + int ret; + + instance =3D kzalloc(sizeof(*instance), GFP_KERNEL); + if (!instance) + return -ENOMEM; + + instance->ctx =3D ctx; + instance->vpu.id =3D SCP_IPI_VDEC_LAT; + instance->vpu.core_id =3D SCP_IPI_VDEC_CORE; + instance->vpu.ctx =3D ctx; + instance->vpu.codec_type =3D ctx->current_codec; + + ret =3D vpu_dec_init(&instance->vpu); + if (ret) { + mtk_vcodec_err(instance, "failed to init vpu dec, ret %d\n", ret); + goto error_vpu_init; + } + + /* init vsi and global flags */ + + vsi =3D instance->vpu.vsi; + if (!vsi) { + mtk_vcodec_err(instance, "failed to get VP9 vsi\n"); + ret =3D -EINVAL; + goto error_vsi; + } + instance->init_vsi =3D vsi; + instance->core_vsi =3D mtk_vcodec_fw_map_dm_addr(ctx->dev->fw_handler, + (u32)vsi->core_vsi); + if (!instance->core_vsi) { + mtk_vcodec_err(instance, "failed to get VP9 core vsi\n"); + ret =3D -EINVAL; + goto error_vsi; + } + + instance->irq =3D 1; + + ret =3D vdec_vp9_slice_init_default_frame_ctx(instance); + if (ret) + goto error_default_frame_ctx; + + ctx->drv_handle =3D instance; + + return 0; + +error_default_frame_ctx: +error_vsi: + vpu_dec_deinit(&instance->vpu); +error_vpu_init: + kfree(instance); + return ret; +} + +static void vdec_vp9_slice_deinit(void *h_vdec) +{ + struct vdec_vp9_slice_instance *instance =3D h_vdec; + + if (!instance) + return; + + vpu_dec_deinit(&instance->vpu); + vdec_vp9_slice_free_working_buffer(instance); + vdec_msg_queue_deinit(&instance->ctx->msg_queue, instance->ctx); + kfree(instance); +} + +static int vdec_vp9_slice_flush(void *h_vdec, struct mtk_vcodec_mem *bs, + struct vdec_fb *fb, bool *res_chg) +{ + struct vdec_vp9_slice_instance *instance =3D h_vdec; + + mtk_vcodec_debug(instance, "flush ...\n"); + + vdec_msg_queue_wait_lat_buf_full(&instance->ctx->msg_queue); + return vpu_dec_reset(&instance->vpu); +} + +static void vdec_vp9_slice_get_pic_info(struct vdec_vp9_slice_instance *in= stance) +{ + struct mtk_vcodec_ctx *ctx =3D instance->ctx; + unsigned int data[3]; + + mtk_vcodec_debug(instance, "w %u h %u\n", + ctx->picinfo.pic_w, ctx->picinfo.pic_h); + + data[0] =3D ctx->picinfo.pic_w; + data[1] =3D ctx->picinfo.pic_h; + data[2] =3D ctx->capture_fourcc; + vpu_dec_get_param(&instance->vpu, data, 3, GET_PARAM_PIC_INFO); + + ctx->picinfo.buf_w =3D ALIGN(ctx->picinfo.pic_w, 64); + ctx->picinfo.buf_h =3D ALIGN(ctx->picinfo.pic_h, 64); + ctx->picinfo.fb_sz[0] =3D instance->vpu.fb_sz[0]; + ctx->picinfo.fb_sz[1] =3D instance->vpu.fb_sz[1]; +} + +static void vdec_vp9_slice_get_dpb_size(struct vdec_vp9_slice_instance *in= stance, + unsigned int *dpb_sz) +{ + /* refer VP9 specification */ + *dpb_sz =3D 9; +} + +static int vdec_vp9_slice_get_param(void *h_vdec, enum vdec_get_param_type= type, void *out) +{ + struct vdec_vp9_slice_instance *instance =3D h_vdec; + + switch (type) { + case GET_PARAM_PIC_INFO: + vdec_vp9_slice_get_pic_info(instance); + break; + case GET_PARAM_DPB_SIZE: + vdec_vp9_slice_get_dpb_size(instance, out); + break; + case GET_PARAM_CROP_INFO: + mtk_vcodec_debug(instance, "No need to get vp9 crop information."); + break; + default: + mtk_vcodec_err(instance, "invalid get parameter type=3D%d\n", + type); + return -EINVAL; + } + + return 0; +} + +static int vdec_vp9_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *= bs, + struct vdec_fb *fb, bool *res_chg) +{ + struct vdec_vp9_slice_instance *instance =3D h_vdec; + struct vdec_lat_buf *lat_buf; + struct vdec_vp9_slice_pfc *pfc; + struct vdec_vp9_slice_vsi *vsi; + struct mtk_vcodec_ctx *ctx; + int ret; + + if (!instance || !instance->ctx) + return -EINVAL; + ctx =3D instance->ctx; + + /* init msgQ for the first time */ + if (vdec_msg_queue_init(&ctx->msg_queue, ctx, + vdec_vp9_slice_core_decode, + sizeof(*pfc))) + return -ENOMEM; + + /* bs NULL means flush decoder */ + if (!bs) + return vdec_vp9_slice_flush(h_vdec, bs, fb, res_chg); + + lat_buf =3D vdec_msg_queue_dqbuf(&instance->ctx->msg_queue.lat_ctx); + if (!lat_buf) { + mtk_vcodec_err(instance, "Failed to get VP9 lat buf\n"); + return -EBUSY; + } + pfc =3D (struct vdec_vp9_slice_pfc *)lat_buf->private_data; + if (!pfc) + return -EINVAL; + vsi =3D &pfc->vsi; + + ret =3D vdec_vp9_slice_setup_lat(instance, bs, lat_buf, pfc); + if (ret) { + mtk_vcodec_err(instance, "Failed to setup VP9 lat ret %d\n", ret); + return ret; + } + vdec_vp9_slice_vsi_to_remote(vsi, (void __iomem *)instance->vsi); + + ret =3D vpu_dec_start(&instance->vpu, NULL, 0); + if (ret) { + mtk_vcodec_err(instance, "Failed to dec VP9 ret %d\n", ret); + return ret; + } + + if (instance->irq) { + ret =3D mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0); + /* update remote vsi if decode timeout */ + if (ret) { + mtk_vcodec_err(instance, "VP9 decode timeout %d pic %d\n", ret, pfc->se= q); + writel(1, (void __iomem *)&instance->vsi->state.timeout); + } + vpu_dec_end(&instance->vpu); + } + + vdec_vp9_slice_vsi_from_remote(vsi, (void __iomem *)instance->vsi, 0); + ret =3D vdec_vp9_slice_update_lat(instance, lat_buf, pfc); + + /* LAT trans full, no more UBE or decode timeout */ + if (ret) { + mtk_vcodec_err(instance, "VP9 decode error: %d\n", ret); + return ret; + } + + mtk_vcodec_debug(instance, "lat dma addr: 0x%lx 0x%lx\n", + (unsigned long)pfc->vsi.trans.dma_addr, + (unsigned long)pfc->vsi.trans.dma_addr_end); + + vdec_msg_queue_update_ube_wptr(&ctx->msg_queue, + vsi->trans.dma_addr_end + + ctx->msg_queue.wdma_addr.dma_addr); + vdec_msg_queue_qbuf(&ctx->dev->msg_queue_core_ctx, lat_buf); + + return 0; +} + +static int vdec_vp9_slice_core_decode(struct vdec_lat_buf *lat_buf) +{ + struct vdec_vp9_slice_instance *instance; + struct vdec_vp9_slice_pfc *pfc; + struct mtk_vcodec_ctx *ctx =3D NULL; + struct vdec_fb *fb =3D NULL; + int ret =3D -EINVAL; + + if (!lat_buf) + goto err; + + pfc =3D lat_buf->private_data; + ctx =3D lat_buf->ctx; + if (!pfc || !ctx) + goto err; + + instance =3D ctx->drv_handle; + if (!instance) + goto err; + + fb =3D ctx->dev->vdec_pdata->get_cap_buffer(ctx); + if (!fb) { + ret =3D -EBUSY; + goto err; + } + + ret =3D vdec_vp9_slice_setup_core(instance, fb, lat_buf, pfc); + if (ret) { + mtk_vcodec_err(instance, "vdec_vp9_slice_setup_core\n"); + goto err; + } + vdec_vp9_slice_vsi_to_remote(&pfc->vsi, (void __iomem *)instance->core_vs= i); + + ret =3D vpu_dec_core(&instance->vpu); + if (ret) { + mtk_vcodec_err(instance, "vpu_dec_core\n"); + goto err; + } + + if (instance->irq) { + ret =3D mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED, + WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE); + /* update remote vsi if decode timeout */ + if (ret) { + mtk_vcodec_err(instance, "VP9 core timeout pic %d\n", pfc->seq); + writel(1, (void __iomem *)&instance->core_vsi->state.timeout); + } + vpu_dec_core_end(&instance->vpu); + } + + vdec_vp9_slice_vsi_from_remote(&pfc->vsi, (void __iomem *)instance->core_= vsi, 1); + ret =3D vdec_vp9_slice_update_core(instance, lat_buf, pfc); + if (ret) { + mtk_vcodec_err(instance, "vdec_vp9_slice_update_core\n"); + goto err; + } + + pfc->vsi.trans.dma_addr_end +=3D ctx->msg_queue.wdma_addr.dma_addr; + mtk_vcodec_debug(instance, "core dma_addr_end 0x%lx\n", + (unsigned long)pfc->vsi.trans.dma_addr_end); + vdec_msg_queue_update_ube_rptr(&ctx->msg_queue, pfc->vsi.trans.dma_addr_e= nd); + ctx->dev->vdec_pdata->cap_to_disp(ctx, 0, lat_buf->src_buf_req); + + return 0; + +err: + if (ctx && pfc) { + /* always update read pointer */ + vdec_msg_queue_update_ube_rptr(&ctx->msg_queue, pfc->vsi.trans.dma_addr_= end); + + if (fb) + ctx->dev->vdec_pdata->cap_to_disp(ctx, 1, lat_buf->src_buf_req); + } + return ret; +} + +const struct vdec_common_if vdec_vp9_slice_lat_if =3D { + .init =3D vdec_vp9_slice_init, + .decode =3D vdec_vp9_slice_lat_decode, + .get_param =3D vdec_vp9_slice_get_param, + .deinit =3D vdec_vp9_slice_deinit, +}; diff --git a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c b/drivers= /media/platform/mediatek/vcodec/vdec_drv_if.c index b709c7bae197..27b4b35039cf 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec_drv_if.c @@ -45,6 +45,10 @@ int vdec_if_init(struct mtk_vcodec_ctx *ctx, unsigned in= t fourcc) ctx->dec_if =3D &vdec_vp9_if; ctx->hw_id =3D MTK_VDEC_CORE; break; + case V4L2_PIX_FMT_VP9_FRAME: + ctx->dec_if =3D &vdec_vp9_slice_lat_if; + ctx->hw_id =3D MTK_VDEC_LAT0; + break; default: return -EINVAL; } diff --git a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h b/drivers= /media/platform/mediatek/vcodec/vdec_drv_if.h index 97f6e324e623..076306ff2dd4 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h +++ b/drivers/media/platform/mediatek/vcodec/vdec_drv_if.h @@ -60,6 +60,7 @@ extern const struct vdec_common_if vdec_h264_slice_multi_= if; extern const struct vdec_common_if vdec_vp8_if; extern const struct vdec_common_if vdec_vp8_slice_if; extern const struct vdec_common_if vdec_vp9_if; +extern const struct vdec_common_if vdec_vp9_slice_lat_if; =20 /** * vdec_if_init() - initialize decode driver --=20 2.18.0 From nobody Thu Nov 14 10:08:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F947C433EF for ; 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Fri, 06 May 2022 17:29:34 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 6 May 2022 17:29:32 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 6 May 2022 17:29:30 +0800 From: Yunfei Dong To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v11, 17/17] media: mediatek: vcodec: prevent kernel crash when rmmod mtk-vcodec-dec.ko Date: Fri, 6 May 2022 17:28:55 +0800 Message-ID: <20220506092855.22940-18-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506092855.22940-1-yunfei.dong@mediatek.com> References: <20220506092855.22940-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If the driver support subdev mode, the parameter "dev->pm.dev" will be NULL in mtk_vcodec_dec_remove. Kernel will crash when try to rmmod mtk-vcodec-dec.ko. [ 4380.702726] pc : do_raw_spin_trylock+0x4/0x80 [ 4380.707075] lr : _raw_spin_lock_irq+0x90/0x14c [ 4380.711509] sp : ffff80000819bc10 [ 4380.714811] x29: ffff80000819bc10 x28: ffff3600c03e4000 x27: 00000000000= 00000 [ 4380.721934] x26: 0000000000000000 x25: 0000000000000000 x24: 00000000000= 00000 [ 4380.729057] x23: ffff3600c0f34930 x22: ffffd5e923549000 x21: 00000000000= 00220 [ 4380.736179] x20: 0000000000000208 x19: ffffd5e9213e8ebc x18: 00000000000= 00020 [ 4380.743298] x17: 0000002000000000 x16: ffffd5e9213e8e90 x15: 696c346f656= 46976 [ 4380.750420] x14: 0000000000000000 x13: 0000000000000001 x12: 00000000000= 00040 [ 4380.757542] x11: 0000000000000000 x10: 0000000000000000 x9 : 00000000000= 00000 [ 4380.764664] x8 : 0000000000000000 x7 : ffff3600c7273ae8 x6 : ffffd5e9213= e8ebc [ 4380.771786] x5 : 0000000000000000 x4 : 0000000000000001 x3 : 00000000000= 00000 [ 4380.778908] x2 : 0000000000000000 x1 : ffff3600c03e4000 x0 : 00000000000= 00208 [ 4380.786031] Call trace: [ 4380.788465] do_raw_spin_trylock+0x4/0x80 [ 4380.792462] __pm_runtime_disable+0x2c/0x1b0 [ 4380.796723] mtk_vcodec_dec_remove+0x5c/0xa0 [mtk_vcodec_dec] [ 4380.802466] platform_remove+0x2c/0x60 [ 4380.806204] __device_release_driver+0x194/0x250 [ 4380.810810] driver_detach+0xc8/0x15c [ 4380.814462] bus_remove_driver+0x5c/0xb0 [ 4380.818375] driver_unregister+0x34/0x64 [ 4380.822288] platform_driver_unregister+0x18/0x24 [ 4380.826979] mtk_vcodec_dec_driver_exit+0x1c/0x888 [mtk_vcodec_dec] [ 4380.833240] __arm64_sys_delete_module+0x190/0x224 [ 4380.838020] invoke_syscall+0x48/0x114 [ 4380.841760] el0_svc_common.constprop.0+0x60/0x11c [ 4380.846540] do_el0_svc+0x28/0x90 [ 4380.849844] el0_svc+0x4c/0x100 [ 4380.852975] el0t_64_sync_handler+0xec/0xf0 [ 4380.857148] el0t_64_sync+0x190/0x194 [ 4380.860801] Code: 94431515 17ffffca d503201f d503245f (b9400004) Signed-off-by: Yunfei Dong --- drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c b/= drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c index a84df6596aaa..5da4572c5b14 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c @@ -482,7 +482,8 @@ static int mtk_vcodec_dec_remove(struct platform_device= *pdev) video_unregister_device(dev->vfd_dec); =20 v4l2_device_unregister(&dev->v4l2_dev); - pm_runtime_disable(dev->pm.dev); + if (!dev->vdec_pdata->is_subdev_supported) + pm_runtime_disable(dev->pm.dev); mtk_vcodec_fw_release(dev->fw_handler); return 0; } --=20 2.18.0