From nobody Sun May 10 10:32:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E052FC4332F for ; Thu, 5 May 2022 13:43:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379919AbiEENrH (ORCPT ); Thu, 5 May 2022 09:47:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379889AbiEENrE (ORCPT ); Thu, 5 May 2022 09:47:04 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD87457981; Thu, 5 May 2022 06:43:16 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 245Dh7Ka039902; Thu, 5 May 2022 08:43:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1651758188; bh=dwDqfTZcpar8twstwU6LFYm3Ok1etJ+eeBYha6p9PDI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mtdibd95XMmviVydRH85Yc7rRHWpYYoi3nIXqgbN2vdjXCOuBG/j2TG9f3rrXakut BW53JTiuQykX1RIkBoB8hABOGEDZygRM6Pf1BkEiEn1kvKd4qyw3vbkqPius2Nqblu qdPchkdehcd8guD3K3U+MeHac5AFOz7Ip0BoUaG0= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 245Dh7bB053435 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 May 2022 08:43:07 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 5 May 2022 08:43:07 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 5 May 2022 08:43:06 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 245Dh6mQ077914; Thu, 5 May 2022 08:43:06 -0500 From: Aradhya Bhatia To: Vignesh Raghavendra CC: Nishanth Menon , Rob Herring , Linux ARM Kernel List , Devicetree List , Linux Kernel List , Aradhya Bhatia , Rahul T R Subject: [PATCH v2 1/4] arm64: dts: ti: k3-am62-main: Add node for Display SubSystem Date: Thu, 5 May 2022 19:13:00 +0530 Message-ID: <20220505134303.23208-2-a-bhatia1@ti.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505134303.23208-1-a-bhatia1@ti.com> References: <20220505134303.23208-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add DT node for the Display SubSystem on the am62x soc in cbass_main. The DSS IP on this soc is compatible with the one on the am65x soc. The DSS supports one each of video pipeline (vid) and video-lite pipeline (vidl1). It outputs OLDI signals on one video port (vp1) and DPI signals on another (vp2). The video ports are connected to the pipelines via 2 identical overlay managers (ovr1 and ovr2). Signed-off-by: Aradhya Bhatia Reviewed-by: Rahul T R --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index eec8dae65e7c..ff21efa4ffad 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -515,6 +515,36 @@ cpts@3d000 { }; }; =20 + dss: dss@30200000 { + compatible =3D "ti,am65x-dss"; + + reg =3D <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + + reg-names =3D "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + + power-domains =3D <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + + clocks =3D <&k3_clks 186 4>, + <&k3_clks 186 0>, + <&k3_clks 186 2>; + + clock-names =3D "fck", "vp1", "vp2"; + + interrupts =3D ; + + dss_ports: ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + hwspinlock: spinlock@2a000000 { compatible =3D "ti,am64-hwspinlock"; reg =3D <0x00 0x2a000000 0x00 0x1000>; --=20 2.36.0 From nobody Sun May 10 10:32:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2E97C433F5 for ; Thu, 5 May 2022 13:43:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379933AbiEENrS (ORCPT ); Thu, 5 May 2022 09:47:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379893AbiEENrF (ORCPT ); Thu, 5 May 2022 09:47:05 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA048579AF; Thu, 5 May 2022 06:43:24 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 245Dh970030871; Thu, 5 May 2022 08:43:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1651758189; bh=c7sai7TRJE+eZjumyOih54NfthenOjddx5v2Xq2F4EM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PT2jcBYPu0A3WnPnQjfKHrkJXak0If18MgUR+tFbNokutXn97fSUss712SrrXzqnN 7FQwyS7gz2m2WU6hD1fqDtcTHCDiig65PMulxTWY9kPo2eLdofaPdaLzpaijmjHeIG 6wq1YbTVMoNhbp4YwQ16yB94TrGUt/IwrIX6gxww= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 245Dh9k4007546 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 May 2022 08:43:09 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 5 May 2022 08:43:08 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 5 May 2022 08:43:08 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 245Dh7Kg077922; Thu, 5 May 2022 08:43:08 -0500 From: Aradhya Bhatia To: Vignesh Raghavendra CC: Nishanth Menon , Rob Herring , Linux ARM Kernel List , Devicetree List , Linux Kernel List , Aradhya Bhatia , Rahul T R Subject: [PATCH v2 2/4] arm64: dts: ti: k3-am625-sk: Add DSS pinmux info Date: Thu, 5 May 2022 19:13:01 +0530 Message-ID: <20220505134303.23208-3-a-bhatia1@ti.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505134303.23208-1-a-bhatia1@ti.com> References: <20220505134303.23208-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add pinmux info for video output signals from DSS. The DSS outputs dpi signals through its second video port (vp2). This output is of 24 bits (RGB888) and is forwarded to an HDMI transmitter chip on the board. Signed-off-by: Aradhya Bhatia Reviewed-by: Rahul T R --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 38 ++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/t= i/k3-am625-sk.dts index 5c38ee5ff9b2..ab3d90d358ee 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -255,6 +255,39 @@ AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ >; }; =20 + main_dss0_pins_default: main-dss0-pins-default { + pinctrl-single,pins =3D < + AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ + AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ + AM62X_IOPAD(0x0064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ + AM62X_IOPAD(0x0068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ + AM62X_IOPAD(0x006c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62X_IOPAD(0x0070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ + AM62X_IOPAD(0x0074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ + AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { pinctrl-single,pins =3D < AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ @@ -412,6 +445,11 @@ cpsw3g_phy1: ethernet-phy@1 { }; }; =20 +&dss { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_dss0_pins_default>; +}; + &mailbox0_cluster0 { mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; --=20 2.36.0 From nobody Sun May 10 10:32:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7402AC43219 for ; Thu, 5 May 2022 13:43:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238690AbiEENrN (ORCPT ); Thu, 5 May 2022 09:47:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379855AbiEENrF (ORCPT ); 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Thu, 5 May 2022 08:43:10 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 5 May 2022 08:43:09 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 245Dh939104707; Thu, 5 May 2022 08:43:09 -0500 From: Aradhya Bhatia To: Vignesh Raghavendra CC: Nishanth Menon , Rob Herring , Linux ARM Kernel List , Devicetree List , Linux Kernel List , Aradhya Bhatia , Rahul T R Subject: [PATCH v2 3/4] arm64: dts: ti: k3-am625-sk: Update main-i2c1 frequency Date: Thu, 5 May 2022 19:13:02 +0530 Message-ID: <20220505134303.23208-4-a-bhatia1@ti.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505134303.23208-1-a-bhatia1@ti.com> References: <20220505134303.23208-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Update the main-i2c1 frequency from 400KHz to 100KHz. There are 2 devices on the i2c-1 bus. An IO-Expander and an HDMI TX. Both of these are capable of servicing i2c upto a max frequency of 400KHz. However, below warning log shows up while running any userspace application that uses the HDMI display when the main-i2c1 frequency is set at 400KHz. [ 985.773431] omap_i2c 20010000.i2c: controller timed out With some further tests using 2 frequencies, 100 KHz and 400KHz across different HDMI cable & monitor setups, it was observed that, - i2c frequency of 400KHz works fine with standard good quality HDMI cables with branded displays. It will show the controller timeout warnings only when a sub-standard / generic HDMI cable is being used. - Using 100KHz for i2c frequency, stops the warning from showing up for the generic HDMI cables as well. Since, the IO-Expander is the only other component on that i2c bus and we are not performing any intensive operations on it, it would be safe to set the i2c frequency at 100KHz in order to support a broader variety of HDMI cables. Signed-off-by: Aradhya Bhatia Reviewed-by: Rahul T R --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/t= i/k3-am625-sk.dts index ab3d90d358ee..96414c5dacf7 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -357,7 +357,7 @@ &main_i2c0 { &main_i2c1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c1_pins_default>; - clock-frequency =3D <400000>; + clock-frequency =3D <100000>; =20 exp1: gpio@22 { compatible =3D "ti,tca6424"; --=20 2.36.0 From nobody Sun May 10 10:32:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 377D5C433F5 for ; Thu, 5 May 2022 13:43:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235829AbiEENrY (ORCPT ); Thu, 5 May 2022 09:47:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379894AbiEENrE (ORCPT ); Thu, 5 May 2022 09:47:04 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EBF657988; Thu, 5 May 2022 06:43:18 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 245DhDuQ122533; Thu, 5 May 2022 08:43:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1651758193; bh=pQy8r4nSyp4/lSSZsHHCYvHBoz+cDyLXwl/nngd8tIo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Nm6Puk+1tY3VUjLZhgbK5X8k3qfhoR401QjFt6CnyxC9Mtv0+SpLr+NATsCgsaF9D +bV2u+kLXjqcyc9m7oOITtdNwKTEba47AySgkfzlYqzePqbCvm0BL976RtYhCnNa4p Z7mPV5tixy4qA2DI+GqGx1R4SXhF8nvyj76taswY= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 245DhDAm062630 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 May 2022 08:43:13 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Thu, 5 May 2022 08:43:11 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Thu, 5 May 2022 08:43:11 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 245DhAS7104725; Thu, 5 May 2022 08:43:11 -0500 From: Aradhya Bhatia To: Vignesh Raghavendra CC: Nishanth Menon , Rob Herring , Linux ARM Kernel List , Devicetree List , Linux Kernel List , Aradhya Bhatia , Rahul T R Subject: [PATCH v2 4/4] arm64: dts: ti: k3-am625-sk: Add DSS ports, HDMI tx & peripherals Date: Thu, 5 May 2022 19:13:03 +0530 Message-ID: <20220505134303.23208-5-a-bhatia1@ti.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505134303.23208-1-a-bhatia1@ti.com> References: <20220505134303.23208-1-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add DT nodes for sil9022 HDMI transmitter (tx), HDMI connector and the HDMI fixed master clock on the am625-sk board. Additionally, add and connect output port for DSS (vp2), input and output ports for the sil9022 HDMI tx and the input port for the HDMI connector. The sil9022 HDMI tx is connected on the i2c1 bus. The HDMI connector on the board is of type "a". The clock frequency of the master clock that supports the HDMI tx is 12.288 MHz. The dpi output signals from the vp2 of DSS are fed into the sil9022 HDMI transmitter. These signals are converted into HDMI signals which are further passed on to the HDMI connector on the board, on which display can be connected via appropriate HDMI cables. Signed-off-by: Aradhya Bhatia Reviewed-by: Rahul T R --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 60 ++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/t= i/k3-am625-sk.dts index 96414c5dacf7..e5b05223e9a1 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -134,6 +134,23 @@ led-0 { default-state =3D "off"; }; }; + + hdmi_mstrclk: hdmi-mstrclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <12288000>; + }; + + hdmi: connector { + compatible =3D "hdmi-connector"; + label =3D "hdmi"; + type =3D "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint =3D <&sii9022_out>; + }; + }; + }; }; =20 &main_pmx0 { @@ -385,6 +402,38 @@ exp1: gpio@22 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_gpio1_ioexp_intr_pins_default>; }; + + sii9022: sii9022@3b { + compatible =3D "sil,sii9022"; + reg =3D <0x3b>; + + clocks =3D <&hdmi_mstrclk>; + clock-names =3D "mclk"; + + interrupt-parent =3D <&exp1>; + interrupts =3D <16 IRQ_TYPE_EDGE_FALLING>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + sii9022_in: endpoint { + remote-endpoint =3D <&dpi1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + sii9022_out: endpoint { + remote-endpoint =3D <&hdmi_connector_in>; + }; + }; + }; + }; }; =20 &main_i2c2 { @@ -450,6 +499,17 @@ &dss { pinctrl-0 =3D <&main_dss0_pins_default>; }; =20 +&dss_ports { + /* VP2: DPI Output */ + port@1 { + reg =3D <1>; + + dpi1_out: endpoint { + remote-endpoint =3D <&sii9022_in>; + }; + }; +}; + &mailbox0_cluster0 { mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; --=20 2.36.0