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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id l20-20020adfc794000000b0020c5253d8dfsm13330101wrg.43.2022.05.04.13.35.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 13:35:12 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v4 1/8] riscv: dts: microchip: remove icicle memory clocks Date: Wed, 4 May 2022 21:30:45 +0100 Message-Id: <20220504203051.1210355-2-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504203051.1210355-1-mail@conchuod.ie> References: <20220504203051.1210355-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The clock properties in the icicle kit's memory entries cause dtbs_check errors: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: /: memory@8000= 0000: 'clocks' does not match any of the regexes: 'pinctrl-[0-9]+' Get rid of the clocks to avoid the errors. Reported-by: Palmer Dabbelt Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Fixes: 5b28df37d311 ("riscv: dts: microchip: update peripherals in icicle k= it device tree") Reviewed-by: Heiko Stuebner Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/= arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index 3392153dd0f1..c71d6aa6137a 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -32,14 +32,12 @@ cpus { ddrc_cache_lo: memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0x0 0x2e000000>; - clocks =3D <&clkcfg CLK_DDRC>; status =3D "okay"; }; =20 ddrc_cache_hi: memory@1000000000 { device_type =3D "memory"; reg =3D <0x10 0x0 0x0 0x40000000>; - clocks =3D <&clkcfg CLK_DDRC>; status =3D "okay"; }; }; --=20 2.36.0 From nobody Fri May 8 10:48:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B15FC433F5 for ; Wed, 4 May 2022 20:35:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234143AbiEDUjO (ORCPT ); Wed, 4 May 2022 16:39:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378200AbiEDUiy (ORCPT ); Wed, 4 May 2022 16:38:54 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F0991092 for ; Wed, 4 May 2022 13:35:15 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id c11so3513337wrn.8 for ; Wed, 04 May 2022 13:35:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u32JFIRC//emCZL/Ld3yABcbdL+d3UQ5fDlVHIQccNo=; b=EqFAmxuYJmI2kg2xatXiw/7b//+XA/+XzJzcDLMsLcAOX1ovCEd1KFfehGAAlyE/4f xiEsAoP4ivzt5ag/BNffjzP+vfNzGXwAIK22vNZQHW+NcP7O09lV3mpCC7Y6loIiONrA TTsShcURvOoV0uUpDVoGQAxc1Bl2gAypo/gfEHlcSVj5tO79VuX+dc+7lB+A2Y42au5l H7WUi6m66kT551TvD/5W6zFWyscv1V1s17bypijpwcglt/NXM9J0zI3zkSpgFPF+rZVs ZbH1OXkxjFCSbAD6w2PvEQE0c1NTq4S6bPHM+Pn78i4aywVaF3Meg/7ZOF1rAk3WinHd YsQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u32JFIRC//emCZL/Ld3yABcbdL+d3UQ5fDlVHIQccNo=; b=qpeePhYev92yhCPSkdV3GiA9ujMC/vxzo2qjoVg91WUIDvQbqCOjm1IYx7PRU7wFOU obV/tOodzsQwjcx1iuKorzIMVkuVc+QsMbWTnnh4lVrUUxClmnSRo8m+tV544wy01ULB JayMdL8pcxrD0itEeotzXLWbG0NdUbw47qz3Vudxv0unsr7eytWxDvIdbcr8Z1eSkJdi wT/AcnqPpx8gM5OAo8ZBi31jgQsO06Ngu2mVgQ6QE2CmFGYn1zY7yPIgcf/QXn/i3kIw EyuYuNSFBpnyD+Mln3HoXInUT8KB05k9KauKC2gHBNTbaeqqk1wBed6jJyIZaREIBMYZ dvTA== X-Gm-Message-State: AOAM531uXkfrIUGT4cOGAEytCJqrAilEfc6R0RSnwZ/kSxCVzUoaMZWS PekHmkVAHmmutzNx2fQ7s/hMfQ== X-Google-Smtp-Source: ABdhPJzdiW4qElFhKIrkosBG7ULnYOtaYvUC52RzTtbzq9l2iyrkPzwTsFVvo1mh5bSHLcpQlZiRLA== X-Received: by 2002:adf:f6c1:0:b0:20a:c408:4aeb with SMTP id y1-20020adff6c1000000b0020ac4084aebmr17411494wrp.74.1651696514483; Wed, 04 May 2022 13:35:14 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id l20-20020adfc794000000b0020c5253d8dfsm13330101wrg.43.2022.05.04.13.35.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 13:35:13 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Rob Herring Subject: [PATCH v4 2/8] riscv: dts: microchip: move sysctrlr out of soc bus Date: Wed, 4 May 2022 21:30:46 +0100 Message-Id: <20220504203051.1210355-3-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504203051.1210355-1-mail@conchuod.ie> References: <20220504203051.1210355-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley The MPFS system controller has no registers of its own, so move it out of the soc node to avoid dtbs_check warnings: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: soc: syscontro= ller: {'compatible': ['microchip,mpfs-sys-controller'], 'mboxes': [[15, 0]]= , 'status': ['okay']} should not be valid under {'type': 'object'} Reported-by: Palmer Dabbelt Suggested-by: Rob Herring Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle = kit device tree") Signed-off-by: Conor Dooley Reviewed-by: Heiko Stuebner --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv= /boot/dts/microchip/microchip-mpfs.dtsi index 746c4d4e7686..bf21a2edd180 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -146,6 +146,11 @@ refclk: mssrefclk { #clock-cells =3D <0>; }; =20 + syscontroller: syscontroller { + compatible =3D "microchip,mpfs-sys-controller"; + mboxes =3D <&mbox 0>; + }; + soc { #address-cells =3D <2>; #size-cells =3D <2>; @@ -446,10 +451,5 @@ mbox: mailbox@37020000 { #mbox-cells =3D <1>; status =3D "disabled"; }; - - syscontroller: syscontroller { - compatible =3D "microchip,mpfs-sys-controller"; - mboxes =3D <&mbox 0>; - }; }; }; --=20 2.36.0 From nobody Fri May 8 10:48:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57A79C433F5 for ; Wed, 4 May 2022 20:35:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378160AbiEDUjH (ORCPT ); Wed, 4 May 2022 16:39:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378211AbiEDUiz (ORCPT ); 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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id l20-20020adfc794000000b0020c5253d8dfsm13330101wrg.43.2022.05.04.13.35.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 13:35:15 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v4 3/8] riscv: dts: microchip: remove soc vendor from filenames Date: Wed, 4 May 2022 21:30:47 +0100 Message-Id: <20220504203051.1210355-4-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504203051.1210355-1-mail@conchuod.ie> References: <20220504203051.1210355-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Having the SoC vendor both as the directory and in the filename adds little. Remove microchip from the filenames so that the files will resemble the other directories in riscv (and arm64). The new names follow a soc-board.dts & soc{,-fabric}.dtsi pattern. Reviewed-by: Heiko Stuebner Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 2 +- .../microchip/{microchip-mpfs-fabric.dtsi =3D> mpfs-fabric.dtsi} | 0 .../{microchip-mpfs-icicle-kit.dts =3D> mpfs-icicle-kit.dts} | 2 +- .../riscv/boot/dts/microchip/{microchip-mpfs.dtsi =3D> mpfs.dtsi} | 2 +- 4 files changed, 3 insertions(+), 3 deletions(-) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi =3D> mpfs= -fabric.dtsi} (100%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts =3D> m= pfs-icicle-kit.dts} (98%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi =3D> mpfs.dtsi} = (99%) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index 855c1502d912..af3a5059b350 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D microchip-mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arc= h/riscv/boot/dts/microchip/mpfs-fabric.dtsi similarity index 100% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi rename to arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/= arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts similarity index 98% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index c71d6aa6137a..84b0015dfd47 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -3,7 +3,7 @@ =20 /dts-v1/; =20 -#include "microchip-mpfs.dtsi" +#include "mpfs.dtsi" =20 /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv= /boot/dts/microchip/mpfs.dtsi similarity index 99% rename from arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi rename to arch/riscv/boot/dts/microchip/mpfs.dtsi index bf21a2edd180..cc3386068c2d 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -3,7 +3,7 @@ =20 /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" -#include "microchip-mpfs-fabric.dtsi" +#include "mpfs-fabric.dtsi" =20 / { #address-cells =3D <2>; --=20 2.36.0 From nobody Fri May 8 10:48:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 889C2C433EF for ; Wed, 4 May 2022 20:35:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378248AbiEDUjV (ORCPT ); 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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id l20-20020adfc794000000b0020c5253d8dfsm13330101wrg.43.2022.05.04.13.35.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 13:35:16 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Krzysztof Kozlowski Subject: [PATCH v4 4/8] dt-bindings: riscv: microchip: document icicle reference design Date: Wed, 4 May 2022 21:30:48 +0100 Message-Id: <20220504203051.1210355-5-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504203051.1210355-1-mail@conchuod.ie> References: <20220504203051.1210355-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add a compatible for the icicle kit's reference design. This represents the FPGA fabric's contents & is versioned to denote which release of the reference design it applies to. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 3f981e897126..822a711df9e9 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -20,6 +20,7 @@ properties: items: - enum: - microchip,mpfs-icicle-kit + - microchip,mpfs-icicle-reference-rtlv2203 - const: microchip,mpfs =20 additionalProperties: true --=20 2.36.0 From nobody Fri May 8 10:48:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04D35C433F5 for ; Wed, 4 May 2022 20:35:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378228AbiEDUj3 (ORCPT ); Wed, 4 May 2022 16:39:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378197AbiEDUi6 (ORCPT ); Wed, 4 May 2022 16:38:58 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6142B263E for ; Wed, 4 May 2022 13:35:20 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id d5so3511043wrb.6 for ; Wed, 04 May 2022 13:35:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RprtUxA8LLqon8+v6D8C02QlLfkROjmGkz+QRU7rBDI=; b=aDLMYf06Nnx6e/HeHuwHBam2WaPjC9EAVu1x5UdXLNi9+1AQ1ryhQgRhiMsk6xEwhj Q5VvcUsbCQNBgFc/hLKCKjiuy2wSPw2+teFGRZgielDG1jF4sb20dFDeXmj/9KTur4zn 1rdc7SuZyzTadFWSgIVlUtg9cfJwihJEgkBdpATxIETghw2304yVE5O8g7wry3E0PicG eNHmqdQeXu4EVh9I3qkC6FquyINd6WEs5Qsn6FCxjggGSHxo/X4TjQ+q/guHnN26gEkU ATI68RDc9b5+DEJFVvhLhXV3XU63jtndtN+uTXlrLrB6yZOSvvY0vCemtmyEu/ujuyT3 Fwyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RprtUxA8LLqon8+v6D8C02QlLfkROjmGkz+QRU7rBDI=; b=sc29Kx0vFWTo0opGzb3xyV3MGNBbHZK0tx2I8AceICkM28kkI9PHAnpxZMKgrjbSd8 h/vQ3vt3DoCFLS6gfOLVVMwLQKvH0MhMjXhkxeCQmJOkeu6qxQJug6nkE17f5lpRtJXE Ic4ofHLuPQq1xcAa9O8a+hvtXkk/Wu43JJbTRGAGWtjuJ0C1B5q0oYiHyLCjWwQcAmNp rWtHPUFfnQgszuHBxL4BeBeDiLKI21DUbuMhYWU0Ym+fpR2gDwm8fo3/3nxZwcnnzoFB nDqzKJkI93Oy8Nkk4OI8jaZYEYf9TQZ8EUjivphYi1h7WFjvC9VEriEysb3Z0dye+sje Y1Uw== X-Gm-Message-State: AOAM531KXlyzae7iQWoHXGh5gEw37FB6TuWwhfHx/OaOuNQCssvMwmhL apKOdNBn5mPsQrwu+QisDNtyDA== X-Google-Smtp-Source: ABdhPJxteJVJs+X9m1ttN+KqKFgEscJRioMfV5WffwO+tTjBvwM5rUsFtEO24U/iKXSoIxw0gw+YLA== X-Received: by 2002:a05:6000:1d8b:b0:20c:54e6:1659 with SMTP id bk11-20020a0560001d8b00b0020c54e61659mr16780999wrb.169.1651696518687; Wed, 04 May 2022 13:35:18 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id l20-20020adfc794000000b0020c5253d8dfsm13330101wrg.43.2022.05.04.13.35.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 13:35:18 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v4 5/8] riscv: dts: microchip: make the fabric dtsi board specific Date: Wed, 4 May 2022 21:30:49 +0100 Message-Id: <20220504203051.1210355-6-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504203051.1210355-1-mail@conchuod.ie> References: <20220504203051.1210355-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Currently mpfs-fabric.dtsi is included by mpfs.dtsi - which is fine currently since there is only one board with this SoC upstream. However if another board was added, it would include the fabric contents of the Icicle Kit's reference design. To avoid this, rename mpfs-fabric.dtsi to mpfs-icicle-kit-fabric.dtsi & include it in the dts rather than mpfs.dtsi. mpfs-icicle-kit-fabric.dtsi specifically matches the 22.03 reference design for the icicle kit's FPGA fabric & an older version of the design may not have the i2c or pwm devices - so add the compatible string to document this. Reviewed-by: Heiko Stuebner Signed-off-by: Conor Dooley --- .../microchip/{mpfs-fabric.dtsi =3D> mpfs-icicle-kit-fabric.dtsi} | 2 ++ arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 1 + arch/riscv/boot/dts/microchip/mpfs.dtsi | 1 - 3 files changed, 3 insertions(+), 1 deletion(-) rename arch/riscv/boot/dts/microchip/{mpfs-fabric.dtsi =3D> mpfs-icicle-ki= t-fabric.dtsi} (91%) diff --git a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi b/arch/riscv/bo= ot/dts/microchip/mpfs-icicle-kit-fabric.dtsi similarity index 91% rename from arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index ccaac3371cf9..0d28858b83f2 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,6 +2,8 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ =20 / { + compatible =3D "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpf= s"; + core_pwm0: pwm@41000000 { compatible =3D "microchip,corepwm-rtl-v4"; reg =3D <0x0 0x41000000 0x0 0xF0>; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv= /boot/dts/microchip/mpfs-icicle-kit.dts index 84b0015dfd47..739dfa52bed1 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -4,6 +4,7 @@ /dts-v1/; =20 #include "mpfs.dtsi" +#include "mpfs-icicle-kit-fabric.dtsi" =20 /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/= microchip/mpfs.dtsi index cc3386068c2d..695c4e2807f5 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -3,7 +3,6 @@ =20 /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" -#include "mpfs-fabric.dtsi" =20 / { #address-cells =3D <2>; --=20 2.36.0 From nobody Fri May 8 10:48:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02109C433EF for ; Wed, 4 May 2022 20:35:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344986AbiEDUje (ORCPT ); Wed, 4 May 2022 16:39:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238079AbiEDUi6 (ORCPT ); Wed, 4 May 2022 16:38:58 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53FB6109D for ; Wed, 4 May 2022 13:35:21 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id 1-20020a05600c248100b00393fbf11a05so3904445wms.3 for ; Wed, 04 May 2022 13:35:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/kez/qpsFQ+IZamV7zrV7LTtRW1TdlvsPTX0KFg6YaM=; b=OzZyx1llwNQhvtNr3EhzufY2pfeGAnTQZ8980mXd99emptugndbzow05J7OXa8m8Xu nqP+vnqzlOc8kFKMq/iHrWMedvjQ0wRUG+S6H4wF7jl0Za89CZBcRF4J5wksf86kGhMj KrIvfuB1e62wN7PxM6tUfql2MvRjusCaH8FUy4WoNLxv1xPZsxlUOaOjz0eN4iMqdeeg mkaG14zpKOLYsIheTbsOJqXU3Kj4mOfQNxRjiFvz9zmvBAKMTPGk8x/owLYrzK1Y9nts 1Ts50BdFx8cFdgu/qKUZoQVP75gO+N4ac/cN7jK+IUdqCbCasA2zIH60wWTZoHtf6qwh 2H6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/kez/qpsFQ+IZamV7zrV7LTtRW1TdlvsPTX0KFg6YaM=; b=5L7WOxHWadXzJJ3ogiIYfFO1HWB0oGF3ldAfHfup3M46rL6RANPBmi7HCnsCEPmG3B EXa5LhaPdK8ZS4j+7vW9mf1MQBeRzBrDQu48gICpmpRYi6e+mEYx0T54as9wB4vkM84l XRUK5M5TuHe/KlyY3sEJ19m9AEV2ESlWuySftBmysAOY5yY9cON6jBgM1S1YHYbouoV+ 5dkbOGjoxpVRMEyHpd3zm+Ohu1MJEM0pzMaw5ChGk0R8nrkoSncm5m7lHbzQVBQizbHB 8JmMuQNE4BgrTRtU0ZloftnNdYcAv/9RmxQTZetmrRWZLFRr9Y7g/oB1wIR8cH0vhXFh OMdg== X-Gm-Message-State: AOAM530zvgN4oJIVedlnhVUALqNAtfCnB1d2iA0a7VN2c8NJ68TAsPHv 5dmzLk2txYQvlwe9RZiCQ2MB2JnFRXKbHWFfucU= X-Google-Smtp-Source: ABdhPJwTP+LGkjMrAS/D90kMOMXTYP/hJZZwmXwXPYgDQ3kVDjSRRrJF5JOfWaxcbNwZKXmG/pVgEQ== X-Received: by 2002:a1c:5459:0:b0:394:1191:a1ff with SMTP id p25-20020a1c5459000000b003941191a1ffmr1086431wmi.96.1651696519959; Wed, 04 May 2022 13:35:19 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id l20-20020adfc794000000b0020c5253d8dfsm13330101wrg.43.2022.05.04.13.35.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 13:35:19 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Krzysztof Kozlowski Subject: [PATCH v4 6/8] dt-bindings: vendor-prefixes: add Sundance DSP Date: Wed, 4 May 2022 21:30:50 +0100 Message-Id: <20220504203051.1210355-7-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504203051.1210355-1-mail@conchuod.ie> References: <20220504203051.1210355-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Sundance DSP Inc. (https://www.sundancedsp.com/) is a supplier of high-performance DSP and FPGA processor boards and I/O modules. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 01430973ecec..1d47a38c2a2e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1197,6 +1197,8 @@ patternProperties: description: Summit microelectronics "^sunchip,.*": description: Shenzhen Sunchip Technology Co., Ltd + "^sundance,.*": + description: Sundance DSP Inc. "^sunplus,.*": description: Sunplus Technology Co., Ltd. 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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id l20-20020adfc794000000b0020c5253d8dfsm13330101wrg.43.2022.05.04.13.35.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 13:35:20 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Krzysztof Kozlowski Subject: [PATCH v4 7/8] dt-bindings: riscv: microchip: add polarberry compatible string Date: Wed, 4 May 2022 21:30:51 +0100 Message-Id: <20220504203051.1210355-8-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504203051.1210355-1-mail@conchuod.ie> References: <20220504203051.1210355-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add a binding for the Sundance Polarberry board. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Docum= entation/devicetree/bindings/riscv/microchip.yaml index 822a711df9e9..1aa7336a9672 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -21,6 +21,7 @@ properties: - enum: - microchip,mpfs-icicle-kit - microchip,mpfs-icicle-reference-rtlv2203 + - sundance,polarberry - const: microchip,mpfs =20 additionalProperties: true --=20 2.36.0 From nobody Fri May 8 10:48:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66F55C433EF for ; Wed, 4 May 2022 20:36:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378288AbiEDUjo (ORCPT ); Wed, 4 May 2022 16:39:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378159AbiEDUjC (ORCPT ); Wed, 4 May 2022 16:39:02 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3AAEB7F0 for ; Wed, 4 May 2022 13:35:23 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id a14-20020a7bc1ce000000b00393fb52a386so3929108wmj.1 for ; Wed, 04 May 2022 13:35:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod.ie; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fsh4pbs3Reo8M+2WhELoDR9Jgw5waXtKp+zOH5sp9UY=; b=BVwVA9Mihadsw+0aZxp3gkgbyCJ+Dg52FAHNdNppEqfjL91z9zMOjvJwUsz7TtzE9o bLajepeEas5+xQlj67PBRX07sXnY5tkzCXadRDHg+LO7lXwkI3kSJt1qTUfbKNZx9ZqD EjDUg3YXP3yq5wG/qpj4wrbVtoeF/0P/PLIlq3t1kEuEgwYglnpwSKgKeUYxgPOaHKMy wVzLEHX3D7ADUTMrsXbrhFdz1MvvG03zKypEg4SEq5b+2MJNwmOCQuOG8PT53ykhjSTt PzC74e7eqwqrWqNJEAofERfKaHOU5YhAco7aY9P5j7G64a6sDZXZxE5j+3K/DE7rbLsQ dz3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fsh4pbs3Reo8M+2WhELoDR9Jgw5waXtKp+zOH5sp9UY=; b=74Qt4oK64tmHpB9qI5fyJQtN/4m9xurTRTBit2MaLImo764hR4WX0zBOdvqUMGLyQ0 1UY1pn6ao3kLWSiNdNIFNdwXZ0E+nReCyN0FDl9LcAjXu8z6HFewJ7KGcXNuOHb22s10 YlE3r+q9TYMx0p8jgaFoxbDkyGGGbjN7sUzRodjaH5bCNr3Es/08exfIC9TTStX480+T q1aO+JhF56qEIK7w+cC48ervUbL026nL1ECbXZeAPqRValApwxDtrf2Cz577AvDwNfv2 /l1uwlgvnxuDFJGfQtk5xq9jWKOZ185efGzwkI18AukuGW9/AND7cG+WsjPSOcFm6Vb9 UApA== X-Gm-Message-State: AOAM531bTwYIxoGGR285lx+UJ32POaiHWyUOv/pte/Cu/xuOMmEOCkwp ELeHrdQxrAwN5O0SNinEv9RjiQ== X-Google-Smtp-Source: ABdhPJzBd2X1g1vv5U4f2un+q/En59yasOly1MTqtmipkBqEI+cZhShIPdGKAXebzJkRSYAqxPMV1g== X-Received: by 2002:a05:600c:9:b0:393:ea67:1c68 with SMTP id g9-20020a05600c000900b00393ea671c68mr1127451wmc.92.1651696522583; Wed, 04 May 2022 13:35:22 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id l20-20020adfc794000000b0020c5253d8dfsm13330101wrg.43.2022.05.04.13.35.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 13:35:22 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, heiko@sntech.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v4 8/8] riscv: dts: microchip: add the sundance polarberry Date: Wed, 4 May 2022 21:30:52 +0100 Message-Id: <20220504203051.1210355-9-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504203051.1210355-1-mail@conchuod.ie> References: <20220504203051.1210355-1-mail@conchuod.ie> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Conor Dooley Add a minimal device tree for the PolarFire SoC based Sundance PolarBerry. Signed-off-by: Conor Dooley Reviewed-by: Heiko Stuebner --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 +++ .../boot/dts/microchip/mpfs-polarberry.dts | 97 +++++++++++++++++++ 3 files changed, 114 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dt= si create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/m= icrochip/Makefile index af3a5059b350..39aae7b04f1c 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) +=3D mpfs-polarberry.dtb obj-$(CONFIG_BUILTIN_DTB) +=3D $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/ar= ch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi new file mode 100644 index 000000000000..49380c428ec9 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv= /boot/dts/microchip/mpfs-polarberry.dts new file mode 100644 index 000000000000..1cad5b0d42e1 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-polarberry-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model =3D "Sundance PolarBerry"; + compatible =3D "sundance,polarberry", "microchip,mpfs"; + + aliases { + ethernet0 =3D &mac1; + serial0 =3D &mmuart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + cpus { + timebase-frequency =3D ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x2e000000>; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type =3D "memory"; + reg =3D <0x10 0x00000000 0x0 0xC0000000>; + }; +}; + +/* + * phy0 is connected to mac0, but the port itself is on the (optional) car= rier + * board. + */ +&mac0 { + status =3D "disabled"; + phy-mode =3D "sgmii"; + phy-handle =3D <&phy0>; +}; + +&mac1 { + status =3D "okay"; + phy-mode =3D "sgmii"; + phy-handle =3D <&phy1>; + phy1: ethernet-phy@5 { + reg =3D <5>; + ti,fifo-depth =3D <0x01>; + }; + phy0: ethernet-phy@4 { + reg =3D <4>; + ti,fifo-depth =3D <0x01>; + }; +}; + +&mbox { + status =3D "okay"; +}; + +&mmc { + bus-width =3D <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + card-detect-delay =3D <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status =3D "okay"; +}; + +&mmuart0 { + status =3D "okay"; +}; + +&refclk { + clock-frequency =3D <125000000>; +}; + +&rtc { + status =3D "okay"; +}; + +&syscontroller { + status =3D "okay"; +}; --=20 2.36.0