From nobody Sun Sep 22 04:51:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 179F1C43217 for ; Wed, 4 May 2022 13:06:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350260AbiEDNJx (ORCPT ); Wed, 4 May 2022 09:09:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350151AbiEDNJa (ORCPT ); Wed, 4 May 2022 09:09:30 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A31992D1FE; Wed, 4 May 2022 06:05:48 -0700 (PDT) X-UUID: 16a14344a37d49ca862e2d36314b2450-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:73ae4dd8-54ab-42eb-965e-dbcd88de9e64,OB:10,L OB:20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,A CTION:release,TS:95 X-CID-INFO: VERSION:1.1.4,REQID:73ae4dd8-54ab-42eb-965e-dbcd88de9e64,OB:10,LOB :20,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,A CTION:quarantine,TS:95 X-CID-META: VersionHash:faefae9,CLOUDID:1fb32c16-2e53-443e-b81a-655c13977218,C OID:a8c8ccef9126,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,File:nil ,QS:0,BEC:nil X-UUID: 16a14344a37d49ca862e2d36314b2450-20220504 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 959914227; Wed, 04 May 2022 21:05:42 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 4 May 2022 21:05:41 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 21:05:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 21:05:41 +0800 From: Rex-BC Chen To: , , , , CC: , , , , , , , , , , , Rex-BC Chen Subject: [PATCH v5 3/9] cpufreq: mediatek: Move voltage limits to platform data Date: Wed, 4 May 2022 21:05:34 +0800 Message-ID: <20220504130540.5902-4-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220504130540.5902-1-rex-bc.chen@mediatek.com> References: <20220504130540.5902-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jia-Wei Chang Voltages and shifts are defined as macros originally. There are different requirements of these values for each MediaTek SoCs. Therefore, we add the platform data and move these values into it. Signed-off-by: Jia-Wei Chang Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/cpufreq/mediatek-cpufreq.c | 90 ++++++++++++++++++++---------- 1 file changed, 61 insertions(+), 29 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-= cpufreq.c index 363ebecb2c80..80a3d4cd49ed 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -10,15 +10,21 @@ #include #include #include +#include #include #include #include =20 -#define MIN_VOLT_SHIFT (100000) -#define MAX_VOLT_SHIFT (200000) -#define MAX_VOLT_LIMIT (1150000) #define VOLT_TOL (10000) =20 +struct mtk_cpufreq_platform_data { + int min_volt_shift; + int max_volt_shift; + int proc_max_volt; + int sram_min_volt; + int sram_max_volt; +}; + /* * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU = DVFS * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in @@ -46,8 +52,11 @@ struct mtk_cpu_dvfs_info { struct notifier_block opp_nb; unsigned int opp_cpu; unsigned long opp_freq; + const struct mtk_cpufreq_platform_data *soc_data; }; =20 +static struct platform_device *cpufreq_pdev; + static LIST_HEAD(dvfs_info_list); =20 static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu) @@ -65,6 +74,7 @@ static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup= (int cpu) static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, int new_vproc) { + const struct mtk_cpufreq_platform_data *soc_data =3D info->soc_data; struct regulator *proc_reg =3D info->proc_reg; struct regulator *sram_reg =3D info->sram_reg; int pre_vproc, pre_vsram, new_vsram, vsram, vproc, ret; @@ -76,7 +86,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dv= fs_info *info, return pre_vproc; } /* Vsram should not exceed the maximum allowed voltage of SoC. */ - new_vsram =3D min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); + new_vsram =3D min(new_vproc + soc_data->min_volt_shift, + soc_data->sram_max_volt); =20 if (pre_vproc < new_vproc) { /* @@ -99,10 +110,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu= _dvfs_info *info, return pre_vproc; } =20 - vsram =3D min(new_vsram, pre_vproc + MAX_VOLT_SHIFT); + vsram =3D min(new_vsram, + pre_vproc + soc_data->min_volt_shift); =20 - if (vsram + VOLT_TOL >=3D MAX_VOLT_LIMIT) { - vsram =3D MAX_VOLT_LIMIT; + if (vsram + VOLT_TOL >=3D soc_data->sram_max_volt) { + vsram =3D soc_data->sram_max_volt; =20 /* * If the target Vsram hits the maximum voltage, @@ -120,7 +132,7 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_= dvfs_info *info, ret =3D regulator_set_voltage(sram_reg, vsram, vsram + VOLT_TOL); =20 - vproc =3D vsram - MIN_VOLT_SHIFT; + vproc =3D vsram - soc_data->min_volt_shift; } if (ret) return ret; @@ -154,7 +166,8 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_= dvfs_info *info, return pre_vsram; } =20 - vproc =3D max(new_vproc, pre_vsram - MAX_VOLT_SHIFT); + vproc =3D max(new_vproc, + pre_vsram - soc_data->max_volt_shift); ret =3D regulator_set_voltage(proc_reg, vproc, vproc + VOLT_TOL); if (ret) @@ -163,10 +176,11 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cp= u_dvfs_info *info, if (vproc =3D=3D new_vproc) vsram =3D new_vsram; else - vsram =3D max(new_vsram, vproc + MIN_VOLT_SHIFT); + vsram =3D max(new_vsram, + vproc + soc_data->min_volt_shift); =20 - if (vsram + VOLT_TOL >=3D MAX_VOLT_LIMIT) { - vsram =3D MAX_VOLT_LIMIT; + if (vsram + VOLT_TOL >=3D soc_data->sram_max_volt) { + vsram =3D soc_data->sram_max_volt; =20 /* * If the target Vsram hits the maximum voltage, @@ -197,13 +211,14 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cp= u_dvfs_info *info, =20 static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vpr= oc) { + const struct mtk_cpufreq_platform_data *soc_data =3D info->soc_data; int ret; =20 if (info->need_voltage_tracking) ret =3D mtk_cpufreq_voltage_tracking(info, vproc); else ret =3D regulator_set_voltage(info->proc_reg, vproc, - MAX_VOLT_LIMIT); + soc_data->proc_max_volt); if (!ret) info->pre_vproc =3D vproc; =20 @@ -583,9 +598,17 @@ static struct cpufreq_driver mtk_cpufreq_driver =3D { =20 static int mtk_cpufreq_probe(struct platform_device *pdev) { + const struct of_device_id *match; struct mtk_cpu_dvfs_info *info, *tmp; int cpu, ret; =20 + match =3D dev_get_platdata(&pdev->dev); + if (!match || !match->data) { + dev_err(&pdev->dev, + "failed to get mtk cpufreq platform data\n"); + return -ENODEV; + } + for_each_possible_cpu(cpu) { info =3D mtk_cpu_dvfs_info_lookup(cpu); if (info) @@ -597,6 +620,7 @@ static int mtk_cpufreq_probe(struct platform_device *pd= ev) goto release_dvfs_info_list; } =20 + info->soc_data =3D match->data; ret =3D mtk_cpu_dvfs_info_init(info, cpu); if (ret) { dev_err(&pdev->dev, @@ -632,20 +656,27 @@ static struct platform_driver mtk_cpufreq_platdrv =3D= { .probe =3D mtk_cpufreq_probe, }; =20 +static const struct mtk_cpufreq_platform_data mt2701_platform_data =3D { + .min_volt_shift =3D 100000, + .max_volt_shift =3D 200000, + .proc_max_volt =3D 1150000, + .sram_min_volt =3D 0, + .sram_max_volt =3D 1150000, +}; + /* List of machines supported by this driver */ static const struct of_device_id mtk_cpufreq_machines[] __initconst =3D { - { .compatible =3D "mediatek,mt2701", }, - { .compatible =3D "mediatek,mt2712", }, - { .compatible =3D "mediatek,mt7622", }, - { .compatible =3D "mediatek,mt7623", }, - { .compatible =3D "mediatek,mt8167", }, - { .compatible =3D "mediatek,mt817x", }, - { .compatible =3D "mediatek,mt8173", }, - { .compatible =3D "mediatek,mt8176", }, - { .compatible =3D "mediatek,mt8183", }, - { .compatible =3D "mediatek,mt8365", }, - { .compatible =3D "mediatek,mt8516", }, - + { .compatible =3D "mediatek,mt2701", .data =3D &mt2701_platform_data }, + { .compatible =3D "mediatek,mt2712", .data =3D &mt2701_platform_data }, + { .compatible =3D "mediatek,mt7622", .data =3D &mt2701_platform_data }, + { .compatible =3D "mediatek,mt7623", .data =3D &mt2701_platform_data }, + { .compatible =3D "mediatek,mt8167", .data =3D &mt2701_platform_data }, + { .compatible =3D "mediatek,mt817x", .data =3D &mt2701_platform_data }, + { .compatible =3D "mediatek,mt8173", .data =3D &mt2701_platform_data }, + { .compatible =3D "mediatek,mt8176", .data =3D &mt2701_platform_data }, + { .compatible =3D "mediatek,mt8183", .data =3D &mt2701_platform_data }, + { .compatible =3D "mediatek,mt8365", .data =3D &mt2701_platform_data }, + { .compatible =3D "mediatek,mt8516", .data =3D &mt2701_platform_data }, { } }; MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines); @@ -654,7 +685,6 @@ static int __init mtk_cpufreq_driver_init(void) { struct device_node *np; const struct of_device_id *match; - struct platform_device *pdev; int err; =20 np =3D of_find_node_by_path("/"); @@ -678,11 +708,12 @@ static int __init mtk_cpufreq_driver_init(void) * and the device registration codes are put here to handle defer * probing. */ - pdev =3D platform_device_register_simple("mtk-cpufreq", -1, NULL, 0); - if (IS_ERR(pdev)) { + cpufreq_pdev =3D platform_device_register_data(NULL, "mtk-cpufreq", -1, + match, sizeof(*match)); + if (IS_ERR(cpufreq_pdev)) { pr_err("failed to register mtk-cpufreq platform device\n"); platform_driver_unregister(&mtk_cpufreq_platdrv); - return PTR_ERR(pdev); + return PTR_ERR(cpufreq_pdev); } =20 return 0; @@ -691,6 +722,7 @@ module_init(mtk_cpufreq_driver_init) =20 static void __exit mtk_cpufreq_driver_exit(void) { + platform_device_unregister(cpufreq_pdev); platform_driver_unregister(&mtk_cpufreq_platdrv); } module_exit(mtk_cpufreq_driver_exit) --=20 2.18.0