From nobody Fri May 8 11:30:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA17CC433FE for ; Wed, 4 May 2022 13:03:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350154AbiEDNGw (ORCPT ); Wed, 4 May 2022 09:06:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232905AbiEDNGq (ORCPT ); Wed, 4 May 2022 09:06:46 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84028366AE; Wed, 4 May 2022 06:03:09 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 244ALwRe018222; Wed, 4 May 2022 15:02:41 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=xzVNZjTzmtBSIdVv6DBe++9eoUDnPj2RYYfZVOlqvaM=; b=samI+CtMvgD52A39gBqPpHXB+YG/3V36i7MpWEKQIKJaGJZooqnayV7FMkCE0zBVttQh OhQToxKdr7bvp2ZT5bgf6vgRueFifaxTTdAd434H4NjD40nPLdDGKqq2F/kFr4X5eSow wFQ7jqF6Sw/cSgsP8rTRKxijqDuiRQVXircx8anMfwkQLDyxULRNmVhwj7BDt+pRSj1d 5yPet6ZLC/WttKulqMbba2ZLGWOJP8iNlSQKMNT+pX3pdG0QDDcN+EVsenFw8I8xnF1S lHe0qDsp2z2MWRkt/22pZGI+LVuaYQweBf2sBEX+UlNdVCXDlmxmzuObprK7Ui89mcjF +A== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3frthjvemr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 May 2022 15:02:41 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 12435100034; Wed, 4 May 2022 15:02:41 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0A43121FE9E; Wed, 4 May 2022 15:02:41 +0200 (CEST) Received: from localhost (10.75.127.46) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 4 May 2022 15:02:40 +0200 From: Valentin Caron To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Alexandre Torgue CC: Gabriel Fernandez , Amelie Delaunay , Valentin Caron , , , , , Subject: [PATCH 1/6] dt-bindings: rtc: stm32: add st,lsco optional property to select output Date: Wed, 4 May 2022 15:02:28 +0200 Message-ID: <20220504130233.330983-2-valentin.caron@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220504130233.330983-1-valentin.caron@foss.st.com> References: <20220504130233.330983-1-valentin.caron@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-04_04,2022-05-04_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Amelie Delaunay STM32 RTC has three output pins: RTC_OUT1, RTC_OUT2 or RTC_OUT2_RMP. RTC Low-Speed Clock Output (LSCO) can be output on RTC_OUT1 or RTC_OUT2_RMP. This patch adds constants for RTC output bindings and adds st,lsco optional property for stm32 rtc driver, to select and enable LSCO. A pinctrl state is also optional to reserve pin for RTC output. Signed-off-by: Amelie Delaunay Signed-off-by: Valentin Caron --- .../devicetree/bindings/rtc/st,stm32-rtc.yaml | 20 +++++++++++++++++++ include/dt-bindings/rtc/rtc-stm32.h | 14 +++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 include/dt-bindings/rtc/rtc-stm32.h diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml b/Docu= mentation/devicetree/bindings/rtc/st,stm32-rtc.yaml index 764717ce1873..56d46ea35c5d 100644 --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml @@ -52,6 +52,13 @@ properties: override default rtc_ck parent clock phandle of the new parent clock= of rtc_ck maxItems: 1 =20 + st,lsco: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: | + To select and enable RTC Low Speed Clock Output. + Refer to for the supported val= ues. + Pinctrl state named "default" may be defined to reserve pin for RTC = output. + allOf: - if: properties: @@ -65,6 +72,9 @@ allOf: minItems: 1 maxItems: 1 =20 + st,lsco: + maxItems: 0 + clock-names: false =20 required: @@ -82,6 +92,9 @@ allOf: minItems: 2 maxItems: 2 =20 + st,lsco: + maxItems: 0 + required: - clock-names - st,syscfg @@ -101,6 +114,9 @@ allOf: assigned-clocks: false assigned-clock-parents: false =20 + st,lsco: + maxItems: 1 + required: - clock-names =20 @@ -130,12 +146,16 @@ examples: - | #include #include + #include rtc@5c004000 { compatible =3D "st,stm32mp1-rtc"; reg =3D <0x5c004000 0x400>; clocks =3D <&rcc RTCAPB>, <&rcc RTC>; clock-names =3D "pclk", "rtc_ck"; interrupts =3D ; + st,lsco =3D ; + pinctrl-0 =3D <&rtc_out2_rmp_pins_a>; + pinctrl-names =3D "default"; }; =20 ... diff --git a/include/dt-bindings/rtc/rtc-stm32.h b/include/dt-bindings/rtc/= rtc-stm32.h new file mode 100644 index 000000000000..2fd78c2e62d4 --- /dev/null +++ b/include/dt-bindings/rtc/rtc-stm32.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for STM32_RTC bindings. + */ + +#ifndef _DT_BINDINGS_RTC_RTC_STM32_H +#define _DT_BINDINGS_RTC_RTC_STM32_H + +#define RTC_NO_OUT 0 +#define RTC_OUT1 1 +#define RTC_OUT2 2 +#define RTC_OUT2_RMP 3 + +#endif --=20 2.25.1 From nobody Fri May 8 11:30:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DABC8C433EF for ; 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Wed, 4 May 2022 15:06:36 +0200 From: Valentin Caron To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Alexandre Torgue CC: Gabriel Fernandez , Amelie Delaunay , Valentin Caron , , , , , Subject: [PATCH 2/6] dt-bindings: rtc: stm32: add alarm A out property to select output Date: Wed, 4 May 2022 15:06:13 +0200 Message-ID: <20220504130617.331290-1-valentin.caron@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220504130233.330983-1-valentin.caron@foss.st.com> References: <20220504130233.330983-1-valentin.caron@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-04_04,2022-05-04_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" STM32 RTC can pulse some SOC pins when an alarm of RTC expires. This patch adds property to activate alarm A output. The pulse can output on three pins RTC_OUT1, RTC_OUT2, RTC_OUT2_RMP (PC13, PB2, PI8 on stm32mp15) (PC13, PB2, PI1 on stm32mp13). Signed-off-by: Valentin Caron --- .../devicetree/bindings/rtc/st,stm32-rtc.yaml | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml b/Docu= mentation/devicetree/bindings/rtc/st,stm32-rtc.yaml index 56d46ea35c5d..71e02604e8de 100644 --- a/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/st,stm32-rtc.yaml @@ -59,6 +59,13 @@ properties: Refer to for the supported val= ues. Pinctrl state named "default" may be defined to reserve pin for RTC = output. =20 + st,alarm: + $ref: "/schemas/types.yaml#/definitions/uint32" + description: | + To select and enable RTC Alarm A output. + Refer to for the supported val= ues. + Pinctrl state named "default" may be defined to reserve pin for RTC = output. + allOf: - if: properties: @@ -75,6 +82,9 @@ allOf: st,lsco: maxItems: 0 =20 + st,alarm: + maxItems: 0 + clock-names: false =20 required: @@ -95,6 +105,9 @@ allOf: st,lsco: maxItems: 0 =20 + st,alarm: + maxItems: 0 + required: - clock-names - st,syscfg @@ -117,6 +130,9 @@ allOf: st,lsco: maxItems: 1 =20 + st,alarm: + maxItems: 1 + required: - clock-names =20 @@ -153,8 +169,9 @@ examples: clocks =3D <&rcc RTCAPB>, <&rcc RTC>; clock-names =3D "pclk", "rtc_ck"; interrupts =3D ; + st,alarm =3D ; st,lsco =3D ; - pinctrl-0 =3D <&rtc_out2_rmp_pins_a>; + pinctrl-0 =3D <&rtc_out1_pins_a &rtc_out2_rmp_pins_a>; pinctrl-names =3D "default"; }; =20 --=20 2.25.1 From nobody Fri May 8 11:30:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFD8EC433EF for ; Wed, 4 May 2022 13:07:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350326AbiEDNLa (ORCPT ); Wed, 4 May 2022 09:11:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350390AbiEDNKr (ORCPT ); Wed, 4 May 2022 09:10:47 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4AE2403DA; Wed, 4 May 2022 06:06:53 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 244ALwSj018222; Wed, 4 May 2022 15:06:38 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=xlADDDAYf7bLutWTVCq2qRcVqVGLfJSifwbAguzb0gc=; b=HmCIJQCrZDeDppLqlB5AYEhWMgfGoOmSt7ACGIv+gmuJCipK4Ac8ozCcT9SovDNRRENh 92UEDE/8m+0Thd6/S5+j0kMDadtE5cUq+GzD04QPYHEZy20U/8eibHFMKP8dSqyxnI29 MS505Tmn1LyaBw/hYloTU4xOBj0F0LB8gtymgogYfWutfaZNL2j4nuZDfpEdIMXU7fDq uv9mnJp1ssWdZ6+Z3NzCSCfcxuqCxZ1qiei93Ci3tFK3BmqU909NXIVqyLaFW1GHu3bc gfEmbQCEL+ul7OOWLKVEQfPqiKXbb4UD9cgxOpZHCZldoO2jAOonW4rI3M/3kLfRYNAv oQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3frthjvfg3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 May 2022 15:06:38 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0C7DC100034; Wed, 4 May 2022 15:06:38 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 026C321FEAA; Wed, 4 May 2022 15:06:38 +0200 (CEST) Received: from localhost (10.75.127.44) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 4 May 2022 15:06:37 +0200 From: Valentin Caron To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Alexandre Torgue CC: Gabriel Fernandez , Amelie Delaunay , Valentin Caron , , , , , Subject: [PATCH 3/6] rtc: stm32: add Low Speed Clock Output (LSCO) support Date: Wed, 4 May 2022 15:06:14 +0200 Message-ID: <20220504130617.331290-2-valentin.caron@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220504130233.330983-1-valentin.caron@foss.st.com> References: <20220504130233.330983-1-valentin.caron@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.44] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-04_04,2022-05-04_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Amelie Delaunay STM32 RTC is now registered as a clock provider. It provides rtc_lsco clock, that means RTC_LSCO is output on either RTC_OUT1 or RTC_OUT2_RMP, depending on st,lsco DT property (PC13 or PI8 on stm32mp15), (PC13 or PI1 on stm32mp13). Signed-off-by: Amelie Delaunay Signed-off-by: Valentin Caron --- drivers/rtc/Kconfig | 1 + drivers/rtc/rtc-stm32.c | 133 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 134 insertions(+) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 41c65b4d2baf..2e8021d7c98a 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1888,6 +1888,7 @@ config RTC_DRV_R7301 config RTC_DRV_STM32 tristate "STM32 RTC" select REGMAP_MMIO + depends on COMMON_CLK depends on ARCH_STM32 || COMPILE_TEST help If you say yes here you get support for the STM32 On-Chip diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c index ac9e228b56d0..ace041eb44b8 100644 --- a/drivers/rtc/rtc-stm32.c +++ b/drivers/rtc/rtc-stm32.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include #include #include @@ -15,6 +16,8 @@ #include #include =20 +#include + #define DRIVER_NAME "stm32_rtc" =20 /* STM32_RTC_TR bit fields */ @@ -39,6 +42,11 @@ #define STM32_RTC_CR_FMT BIT(6) #define STM32_RTC_CR_ALRAE BIT(8) #define STM32_RTC_CR_ALRAIE BIT(12) +#define STM32_RTC_CR_COSEL BIT(19) +#define STM32_RTC_CR_OSEL GENMASK(22, 21) +#define STM32_RTC_CR_COE BIT(23) +#define STM32_RTC_CR_TAMPOE BIT(26) +#define STM32_RTC_CR_OUT2EN BIT(31) =20 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */ #define STM32_RTC_ISR_ALRAWF BIT(0) @@ -75,6 +83,12 @@ /* STM32_RTC_SR/_SCR bit fields */ #define STM32_RTC_SR_ALRA BIT(0) =20 +/* STM32_RTC_CFGR bit fields */ +#define STM32_RTC_CFGR_OUT2_RMP BIT(0) +#define STM32_RTC_CFGR_LSCOEN GENMASK(2, 1) +#define STM32_RTC_CFGR_LSCOEN_OUT1 1 +#define STM32_RTC_CFGR_LSCOEN_OUT2_RMP 2 + /* STM32_RTC_VERR bit fields */ #define STM32_RTC_VERR_MINREV_SHIFT 0 #define STM32_RTC_VERR_MINREV GENMASK(3, 0) @@ -89,6 +103,9 @@ /* Max STM32 RTC register offset is 0x3FC */ #define UNDEF_REG 0xFFFF =20 +/* Frequency of HSE clock (Hz) */ +#define STM32_RTC_HSE_FREQ 32768 + struct stm32_rtc; =20 struct stm32_rtc_registers { @@ -101,6 +118,7 @@ struct stm32_rtc_registers { u16 wpr; u16 sr; u16 scr; + u16 cfgr; u16 verr; }; =20 @@ -115,6 +133,7 @@ struct stm32_rtc_data { bool has_pclk; bool need_dbp; bool has_wakeirq; + bool has_lsco; }; =20 struct stm32_rtc { @@ -128,8 +147,88 @@ struct stm32_rtc { const struct stm32_rtc_data *data; int irq_alarm; int wakeirq_alarm; + int lsco; + struct clk *clk_lsco; }; =20 +/* + * ----------------------------------------------------------------------= --- + * | TAMPOE | OSEL[1:0] | COE | OUT2EN | RTC_OUT1 | RTC_OUT2 = | + * | | | | | | or RTC_OUT2_RMP | + * |----------------------------------------------------------------------= ---| + * | 0 | 00 | 0 | 0 or 1 | - | - = | + * |--------|-----------|-----|--------|------------------|---------------= ---| + * | 0 | 00 | 1 | 0 | CALIB | - = | + * |--------|-----------|-----|--------|------------------|---------------= ---| + * | 0 or 1 | !=3D00 | 0 | 0 | TAMPALRM | - = | + * |--------|-----------|-----|--------|------------------|---------------= ---| + * | 0 | 00 | 1 | 1 | - | CALIB = | + * |--------|-----------|-----|--------|------------------|---------------= ---| + * | 0 or 1 | !=3D00 | 0 | 1 | - | TAMPALRM= | + * |--------|-----------|-----|--------|------------------|---------------= ---| + * | 0 or 1 | !=3D00 | 1 | 1 | TAMPALRM | CALIB = | + * ----------------------------------------------------------------------= --- + */ +static int stm32_rtc_clk_lsco_check_availability(struct stm32_rtc *rtc) +{ + struct stm32_rtc_registers regs =3D rtc->data->regs; + unsigned int cr =3D readl_relaxed(rtc->base + regs.cr); + unsigned int cfgr =3D readl_relaxed(rtc->base + regs.cfgr); + unsigned int calib =3D STM32_RTC_CR_COE; + unsigned int tampalrm =3D STM32_RTC_CR_TAMPOE | STM32_RTC_CR_OSEL; + + switch (rtc->lsco) { + case RTC_OUT1: + if ((!(cr & STM32_RTC_CR_OUT2EN) && + ((cr & calib) || cr & tampalrm)) || + ((cr & calib) && (cr & tampalrm))) + return -EBUSY; + break; + case RTC_OUT2_RMP: + if ((cr & STM32_RTC_CR_OUT2EN) && + (cfgr & STM32_RTC_CFGR_OUT2_RMP) && + ((cr & calib) || (cr & tampalrm))) + return -EBUSY; + break; + default: + return -EINVAL; + } + + /* LSCO can only work if RTC clock source is HSE */ + if (clk_get_rate(rtc->rtc_ck) !=3D STM32_RTC_HSE_FREQ) + return -ERANGE; + + return 0; +} + +static int stm32_rtc_clk_lsco_register(struct platform_device *pdev) +{ + struct stm32_rtc *rtc =3D platform_get_drvdata(pdev); + struct stm32_rtc_registers regs =3D rtc->data->regs; + u8 lscoen; + int ret; + + ret =3D stm32_rtc_clk_lsco_check_availability(rtc); + if (ret) + return ret; + + lscoen =3D (rtc->lsco =3D=3D RTC_OUT1) ? STM32_RTC_CFGR_LSCOEN_OUT1 : + STM32_RTC_CFGR_LSCOEN_OUT2_RMP; + + rtc->clk_lsco =3D clk_register_gate(&pdev->dev, "rtc_lsco", + __clk_get_name(rtc->rtc_ck), + CLK_IS_CRITICAL, + rtc->base + regs.cfgr, lscoen, + 0, NULL); + if (IS_ERR(rtc->clk_lsco)) + return PTR_ERR(rtc->clk_lsco); + + of_clk_add_provider(pdev->dev.of_node, + of_clk_src_simple_get, rtc->clk_lsco); + + return 0; +} + static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc) { const struct stm32_rtc_registers *regs =3D &rtc->data->regs; @@ -145,6 +244,15 @@ static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc) writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr); } =20 +static void stm32_rtc_clk_lsco_disable(struct platform_device *pdev) +{ + struct stm32_rtc *rtc =3D platform_get_drvdata(pdev); + struct stm32_rtc_registers regs =3D rtc->data->regs; + unsigned int cfgr =3D readl_relaxed(rtc->base + regs.cfgr); + + writel_relaxed(cfgr &=3D ~STM32_RTC_CFGR_LSCOEN, rtc->base + regs.cfgr); +} + static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc) { const struct stm32_rtc_registers *regs =3D &rtc->data->regs; @@ -548,6 +656,7 @@ static const struct stm32_rtc_data stm32_rtc_data =3D { .has_pclk =3D false, .need_dbp =3D true, .has_wakeirq =3D false, + .has_lsco =3D false, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -558,6 +667,7 @@ static const struct stm32_rtc_data stm32_rtc_data =3D { .wpr =3D 0x24, .sr =3D 0x0C, /* set to ISR offset to ease alarm management */ .scr =3D UNDEF_REG, + .cfgr =3D UNDEF_REG, .verr =3D UNDEF_REG, }, .events =3D { @@ -570,6 +680,7 @@ static const struct stm32_rtc_data stm32h7_rtc_data =3D= { .has_pclk =3D true, .need_dbp =3D true, .has_wakeirq =3D false, + .has_lsco =3D false, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -580,6 +691,7 @@ static const struct stm32_rtc_data stm32h7_rtc_data =3D= { .wpr =3D 0x24, .sr =3D 0x0C, /* set to ISR offset to ease alarm management */ .scr =3D UNDEF_REG, + .cfgr =3D UNDEF_REG, .verr =3D UNDEF_REG, }, .events =3D { @@ -601,6 +713,7 @@ static const struct stm32_rtc_data stm32mp1_data =3D { .has_pclk =3D true, .need_dbp =3D false, .has_wakeirq =3D true, + .has_lsco =3D true, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -611,6 +724,7 @@ static const struct stm32_rtc_data stm32mp1_data =3D { .wpr =3D 0x24, .sr =3D 0x50, .scr =3D 0x5C, + .cfgr =3D 0x60, .verr =3D 0x3F4, }, .events =3D { @@ -814,6 +928,22 @@ static int stm32_rtc_probe(struct platform_device *pde= v) goto err; } =20 + if (rtc->data->has_lsco) { + ret =3D of_property_read_s32(pdev->dev.of_node, + "st,lsco", &rtc->lsco); + if (!ret) { + ret =3D stm32_rtc_clk_lsco_register(pdev); + if (ret) + dev_warn(&pdev->dev, + "LSCO clock registration failed: %d\n", + ret); + } else { + stm32_rtc_clk_lsco_disable(pdev); + rtc->lsco =3D ret; + dev_dbg(&pdev->dev, "No LSCO clock: %d\n", ret); + } + } + /* * If INITS flag is reset (calendar year field set to 0x00), calendar * must be initialized @@ -852,6 +982,9 @@ static int stm32_rtc_remove(struct platform_device *pde= v) const struct stm32_rtc_registers *regs =3D &rtc->data->regs; unsigned int cr; =20 + if (!IS_ERR_OR_NULL(rtc->clk_lsco)) + clk_unregister_gate(rtc->clk_lsco); + /* Disable interrupts */ stm32_rtc_wpr_unlock(rtc); cr =3D readl_relaxed(rtc->base + regs->cr); --=20 2.25.1 From nobody Fri May 8 11:30:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC795C433F5 for ; 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Wed, 4 May 2022 15:06:37 +0200 From: Valentin Caron To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Alexandre Torgue CC: Gabriel Fernandez , Amelie Delaunay , Valentin Caron , , , , , Subject: [PATCH 4/6] rtc: stm32: add alarm A out feature Date: Wed, 4 May 2022 15:06:15 +0200 Message-ID: <20220504130617.331290-3-valentin.caron@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220504130233.330983-1-valentin.caron@foss.st.com> References: <20220504130233.330983-1-valentin.caron@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-04_04,2022-05-04_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" STM32 RTC can pulse some SOC pins when an RTC alarm expires. This patch adds this functionality for alarm A. The pulse can out on three pins RTC_OUT1, RTC_OUT2, RTC_OUT2_RMP (PC13, PB2, PI8 on stm32mp15) (PC13, PB2, PI1 on stm32mp13). This patch only adds the functionality for devices which are using st,stm32mp1-rtc compatible. Signed-off-by: Valentin Caron --- drivers/rtc/rtc-stm32.c | 77 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/rtc/rtc-stm32.c b/drivers/rtc/rtc-stm32.c index ace041eb44b8..f27927be20b2 100644 --- a/drivers/rtc/rtc-stm32.c +++ b/drivers/rtc/rtc-stm32.c @@ -5,6 +5,7 @@ */ =20 #include +#include #include #include #include @@ -44,8 +45,10 @@ #define STM32_RTC_CR_ALRAIE BIT(12) #define STM32_RTC_CR_COSEL BIT(19) #define STM32_RTC_CR_OSEL GENMASK(22, 21) +#define STM32_RTC_CR_OSEL_ALARM_A FIELD_PREP(STM32_RTC_CR_OSEL, 0x01) #define STM32_RTC_CR_COE BIT(23) #define STM32_RTC_CR_TAMPOE BIT(26) +#define STM32_RTC_CR_TAMPALRM_TYPE BIT(30) #define STM32_RTC_CR_OUT2EN BIT(31) =20 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */ @@ -134,6 +137,7 @@ struct stm32_rtc_data { bool need_dbp; bool has_wakeirq; bool has_lsco; + bool has_alarm_out; }; =20 struct stm32_rtc { @@ -149,6 +153,7 @@ struct stm32_rtc { int wakeirq_alarm; int lsco; struct clk *clk_lsco; + int out_alarm; }; =20 /* @@ -253,6 +258,64 @@ static void stm32_rtc_clk_lsco_disable(struct platform= _device *pdev) writel_relaxed(cfgr &=3D ~STM32_RTC_CFGR_LSCOEN, rtc->base + regs.cfgr); } =20 +static int stm32_rtc_out_alarm_config(struct platform_device *pdev) +{ + struct stm32_rtc *rtc =3D platform_get_drvdata(pdev); + struct stm32_rtc_registers regs =3D rtc->data->regs; + unsigned int cr =3D readl_relaxed(rtc->base + regs.cr); + unsigned int cfgr =3D readl_relaxed(rtc->base + regs.cfgr); + + cr &=3D ~STM32_RTC_CR_OSEL; + cr |=3D STM32_RTC_CR_OSEL_ALARM_A; + cr &=3D ~STM32_RTC_CR_TAMPOE; + cr &=3D ~STM32_RTC_CR_COE; + cr &=3D ~STM32_RTC_CR_TAMPALRM_TYPE; + + switch (rtc->out_alarm) { + case RTC_OUT1: + cr &=3D ~STM32_RTC_CR_OUT2EN; + cfgr &=3D ~STM32_RTC_CFGR_OUT2_RMP; + break; + case RTC_OUT2: + cr |=3D STM32_RTC_CR_OUT2EN; + cfgr &=3D ~STM32_RTC_CFGR_OUT2_RMP; + break; + case RTC_OUT2_RMP: + cr |=3D STM32_RTC_CR_OUT2EN; + cfgr |=3D STM32_RTC_CFGR_OUT2_RMP; + break; + default: + return -EINVAL; + } + + stm32_rtc_wpr_unlock(rtc); + writel_relaxed(cr, rtc->base + regs.cr); + writel_relaxed(cfgr, rtc->base + regs.cfgr); + stm32_rtc_wpr_lock(rtc); + + return 0; +} + +static void stm32_rtc_out_alarm_disable(struct platform_device *pdev) +{ + struct stm32_rtc *rtc =3D platform_get_drvdata(pdev); + struct stm32_rtc_registers regs =3D rtc->data->regs; + unsigned int cr =3D readl_relaxed(rtc->base + regs.cr); + unsigned int cfgr =3D readl_relaxed(rtc->base + regs.cfgr); + + cr &=3D ~STM32_RTC_CR_OSEL; + cr &=3D ~STM32_RTC_CR_TAMPOE; + cr &=3D ~STM32_RTC_CR_COE; + cr &=3D ~STM32_RTC_CR_TAMPALRM_TYPE; + cr &=3D ~STM32_RTC_CR_OUT2EN; + cfgr &=3D ~STM32_RTC_CFGR_OUT2_RMP; + + stm32_rtc_wpr_unlock(rtc); + writel_relaxed(cr, rtc->base + regs.cr); + writel_relaxed(cfgr, rtc->base + regs.cfgr); + stm32_rtc_wpr_lock(rtc); +} + static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc) { const struct stm32_rtc_registers *regs =3D &rtc->data->regs; @@ -657,6 +720,7 @@ static const struct stm32_rtc_data stm32_rtc_data =3D { .need_dbp =3D true, .has_wakeirq =3D false, .has_lsco =3D false, + .has_alarm_out =3D false, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -681,6 +745,7 @@ static const struct stm32_rtc_data stm32h7_rtc_data =3D= { .need_dbp =3D true, .has_wakeirq =3D false, .has_lsco =3D false, + .has_alarm_out =3D false, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -714,6 +779,7 @@ static const struct stm32_rtc_data stm32mp1_data =3D { .need_dbp =3D false, .has_wakeirq =3D true, .has_lsco =3D true, + .has_alarm_out =3D true, .regs =3D { .tr =3D 0x00, .dr =3D 0x04, @@ -928,6 +994,17 @@ static int stm32_rtc_probe(struct platform_device *pde= v) goto err; } =20 + if (rtc->data->has_alarm_out) { + ret =3D of_property_read_s32(pdev->dev.of_node, "st,alarm", &rtc->out_al= arm); + if (!ret) { + ret =3D stm32_rtc_out_alarm_config(pdev); + } else { + stm32_rtc_out_alarm_disable(pdev); + rtc->out_alarm =3D ret; + dev_dbg(&pdev->dev, "No alarm out: %d\n", ret); + } + } + if (rtc->data->has_lsco) { ret =3D of_property_read_s32(pdev->dev.of_node, "st,lsco", &rtc->lsco); --=20 2.25.1 From nobody Fri May 8 11:30:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32E72C4332F for ; Wed, 4 May 2022 13:07:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236791AbiEDNLR (ORCPT ); Wed, 4 May 2022 09:11:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350381AbiEDNKq (ORCPT ); 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charset="utf-8" From: Gabriel Fernandez Add LSCO support on stm32mp157c-dk2 board. LSCO output is mapped on RTC_OUT2_RMP (PI8), directly routed on LPO_IN pin of Wifi/Bluetooth module. Signed-off-by: Gabriel Fernandez Signed-off-by: Valentin Caron --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 6 ++++++ arch/arm/boot/dts/stm32mp157c-dk2.dts | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/s= tm32mp15-pinctrl.dtsi index 6052243ad81c..c65d1ea8b614 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1244,6 +1244,12 @@ pins { }; }; =20 + rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 { + pins { + pinmux =3D ; /* RTC_OUT2_RMP */ + }; + }; + sai2a_pins_a: sai2a-0 { pins { pinmux =3D , /* SAI2_SCK_A */ diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts b/arch/arm/boot/dts/stm3= 2mp157c-dk2.dts index 2bc92ef3aeb9..a1eda91bc2e3 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts @@ -11,6 +11,7 @@ #include "stm32mp15-pinctrl.dtsi" #include "stm32mp15xxac-pinctrl.dtsi" #include "stm32mp15xx-dkx.dtsi" +#include =20 / { model =3D "STMicroelectronics STM32MP157C-DK2 Discovery Board"; @@ -92,6 +93,12 @@ ltdc_ep1_out: endpoint@1 { }; }; =20 +&rtc { + st,lsco =3D ; + pinctrl-0 =3D <&rtc_out2_rmp_pins_a>; + pinctrl-names =3D "default"; +}; + &usart2 { pinctrl-names =3D "default", "sleep", "idle"; pinctrl-0 =3D <&usart2_pins_c>; --=20 2.25.1 From nobody Fri May 8 11:30:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C308FC433EF for ; Wed, 4 May 2022 13:07:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350186AbiEDNLU (ORCPT ); Wed, 4 May 2022 09:11:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350391AbiEDNKr (ORCPT ); Wed, 4 May 2022 09:10:47 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A10940E63; Wed, 4 May 2022 06:06:54 -0700 (PDT) Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 244AF0hI016186; Wed, 4 May 2022 15:06:40 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=ebGEldA3FSxzjKP+0IoEsgqVdV2j6ezCK0sWg/HoQHE=; b=zJyiiAF94Zf8uKa13IiCR5sv9lvl9c2skYQ+DuNSw2ClfzCkR9pptSzSJwCJP/ljmOnF 1xefXURZaa4NReuCEF4lzx95XlK6PL1A/bovCLXTTBQeQhyJ/030MOnPVvW2CPojlpwo Qi+O8m5Il95Bv1giY0D7JxJmiKnH/25/jwu9GfHuR0uun6JVdxape9PPeP8i03TuqsVZ XU44lt5bNhZ6lNa47axe4rQbA57/4itbUoyaGApMJrFQj2CZ3xcx6YDNDefyIltnPflR Ye2Xjx1rBShrXqhLhvLoMXe4NN8nfLhfqk39zI3zumHZS8LCAs+s1fbeDOVp29ik/xWu kA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3frvf0m5a5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 May 2022 15:06:40 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C5A8810002A; Wed, 4 May 2022 15:06:39 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id BEEE121FEAA; Wed, 4 May 2022 15:06:39 +0200 (CEST) Received: from localhost (10.75.127.45) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Wed, 4 May 2022 15:06:39 +0200 From: Valentin Caron To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Alexandre Torgue CC: Gabriel Fernandez , Amelie Delaunay , Valentin Caron , , , , , Subject: [PATCH 6/6] ARM: dts: stm32: add RTC LSCO support on stm32mp135f-dk Date: Wed, 4 May 2022 15:06:17 +0200 Message-ID: <20220504130617.331290-5-valentin.caron@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220504130233.330983-1-valentin.caron@foss.st.com> References: <20220504130233.330983-1-valentin.caron@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.45] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-04_04,2022-05-04_01,2022-02-23_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Gabriel Fernandez Add LSCO support on stm32mp135f-dk board. LSCO output is mapped on RTC_OUT2_RMP (PI1), directly routed on LPO_IN pin of Wifi/Bluetooth module. Signed-off-by: Gabriel Fernandez Signed-off-by: Valentin Caron --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 6 ++++++ arch/arm/boot/dts/stm32mp135f-dk.dts | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/s= tm32mp13-pinctrl.dtsi index d2472cd8f1d0..0aaafd529404 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -6,6 +6,12 @@ #include =20 &pinctrl { + rtc_out2_rmp_pins_a: rtc-out2-rmp-pins-0 { + pins { + pinmux =3D ; /* RTC_OUT2_RMP */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux =3D , /* SDMMC1_D0 */ diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32= mp135f-dk.dts index 09d6226d598f..de9fd89fce5c 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -12,6 +12,7 @@ #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" #include "stm32mp13-pinctrl.dtsi" +#include =20 / { model =3D "STMicroelectronics STM32MP135F-DK Discovery Board"; @@ -63,6 +64,9 @@ &iwdg2 { }; =20 &rtc { + st,lsco =3D ; + pinctrl-0 =3D <&rtc_out2_rmp_pins_a>; + pinctrl-names =3D "default"; status =3D "okay"; }; =20 --=20 2.25.1