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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:33:23 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 13/13] clk: mediatek: Add driver for MT6735 pericfg Date: Wed, 4 May 2022 16:26:02 +0400 Message-Id: <20220504122601.335495-14-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add a driver for MT6735 pericfg clock gates and resets. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 1 + drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-pericfg.c | 360 ++++++++++++++++++++++ 4 files changed, 369 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c diff --git a/MAINTAINERS b/MAINTAINERS index 8662f12f34a2..5d90c2f2a587 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12444,6 +12444,7 @@ L: linux-mediatek@lists.infradead.org (moderated fo= r non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixed.c F: drivers/clk/mediatek/clk-mt6735-infracfg.c +F: drivers/clk/mediatek/clk-mt6735-pericfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 62195e5d90a0..698ff2995460 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -131,6 +131,13 @@ config COMMON_CLK_MT6735_INFRACFG help This driver supports MediaTek MT6735 infracfg clocks and resets. =20 +config COMMON_CLK_MT6735_PERICFG + tristate "Clock driver for MediaTek MT6735 pericfg" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This driver supports MediaTek MT6735 pericfg clocks and resets. + config COMMON_CLK_MT6735_TOPCKGEN tristate "Clock driver for MediaTek MT6735 topckgen" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e5c1da6e2711..b1a4d18e382d 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mtk.o clk-pll.o = clk-gate.o clk-apmixed. =20 obj-$(CONFIG_COMMON_CLK_MT6735_APMIXED) +=3D clk-mt6735-apmixed.o obj-$(CONFIG_COMMON_CLK_MT6735_INFRACFG) +=3D clk-mt6735-infracfg.o +obj-$(CONFIG_COMMON_CLK_MT6735_PERICFG) +=3D clk-mt6735-pericfg.o obj-$(CONFIG_COMMON_CLK_MT6735_TOPCKGEN) +=3D clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6765) +=3D clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) +=3D clk-mt6765-audio.o diff --git a/drivers/clk/mediatek/clk-mt6735-pericfg.c b/drivers/clk/mediat= ek/clk-mt6735-pericfg.c new file mode 100644 index 000000000000..8a01aa63a81e --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-pericfg.c @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define PERI_GLOBALCON_RST0 0x00 +#define PERI_GLOBALCON_PDN0_SET 0x08 +#define PERI_GLOBALCON_PDN0_CLR 0x10 +#define PERI_GLOBALCON_PDN0_STA 0x18 + +struct mt6735_pericfg { + struct clk_onecell_data *clk_data; + struct mtk_reset *reset_data; +}; + +static struct mtk_gate_regs peri_cg_regs =3D { + .set_ofs =3D PERI_GLOBALCON_PDN0_SET, + .clr_ofs =3D PERI_GLOBALCON_PDN0_CLR, + .sta_ofs =3D PERI_GLOBALCON_PDN0_STA, +}; + +static const struct mtk_gate pericfg_gates[] =3D { + { + .id =3D DISP_PWM, + .name =3D "disp_pwm", + .parent_name =3D "disppwm_sel", + .regs =3D &peri_cg_regs, + .shift =3D 0, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D THERM, + .name =3D "therm", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 1, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM1, + .name =3D "pwm1", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 2, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM2, + .name =3D "pwm2", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 3, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM3, + .name =3D "pwm3", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 4, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM4, + .name =3D "pwm4", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 5, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM5, + .name =3D "pwm5", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 6, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM6, + .name =3D "pwm6", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 7, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM7, + .name =3D "pwm7", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 8, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM, + .name =3D "pwm", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 9, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D USB0, + .name =3D "usb0", + .parent_name =3D "usb20_sel", + .regs =3D &peri_cg_regs, + .shift =3D 10, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D IRDA, + .name =3D "irda", + .parent_name =3D "irda_sel", + .regs =3D &peri_cg_regs, + .shift =3D 11, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D APDMA, + .name =3D "apdma", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 12, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_0, + .name =3D "msdc30_0", + .parent_name =3D "msdc30_0_sel", + .regs =3D &peri_cg_regs, + .shift =3D 13, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_1, + .name =3D "msdc30_1", + .parent_name =3D "msdc30_1_sel", + .regs =3D &peri_cg_regs, + .shift =3D 14, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_2, + .name =3D "msdc30_2", + .parent_name =3D "msdc30_2_sel", + .regs =3D &peri_cg_regs, + .shift =3D 15, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_3, + .name =3D "msdc30_3", + .parent_name =3D "msdc30_3_sel", + .regs =3D &peri_cg_regs, + .shift =3D 16, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART0, + .name =3D "uart0", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 17, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART1, + .name =3D "uart1", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 18, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART2, + .name =3D "uart2", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 19, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART3, + .name =3D "uart3", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 20, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART4, + .name =3D "uart4", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 21, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D BTIF, + .name =3D "btif", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 22, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C0, + .name =3D "i2c0", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 23, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C1, + .name =3D "i2c1", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 24, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C2, + .name =3D "i2c2", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 25, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C3, + .name =3D "i2c3", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 26, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D AUXADC, + .name =3D "auxadc", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 27, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D SPI0, + .name =3D "spi0", + .parent_name =3D "spi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 28, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D IRTX, + .name =3D "IRTX", + .parent_name =3D "irtx_sel", + .regs =3D &peri_cg_regs, + .shift =3D 29, + .ops =3D &mtk_clk_gate_ops_setclr + }, +}; + +int clk_mt6735_pericfg_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct resource *res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct mt6735_pericfg *pericfg; + int ret; + + base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pericfg =3D devm_kmalloc(&pdev->dev, sizeof(struct mt6735_pericfg), + GFP_KERNEL); + if (!pericfg) + return -ENOMEM; + + pericfg->clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(pericfg_gates)); + if (!pericfg->clk_data) + return -ENOMEM; + platform_set_drvdata(pdev, pericfg); + + ret =3D mtk_clk_register_gates_with_dev(pdev->dev.of_node, pericfg_gates, + ARRAY_SIZE(pericfg_gates), + pericfg->clk_data, &pdev->dev); + if (ret) { + dev_err(&pdev->dev, "Failed to register gates: %pe\n", + ERR_PTR(ret)); + goto free_clk_data; + } + + ret =3D of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + pericfg->clk_data); + if (ret) { + dev_err(&pdev->dev, + "Failed to register clock provider: %pe\n", + ERR_PTR(ret)); + goto unregister_gates; + } + + pericfg->reset_data =3D mtk_register_reset_controller(pdev->dev.of_node, = 2, + PERI_GLOBALCON_RST0); + if (IS_ERR(pericfg->reset_data)) { + dev_err(&pdev->dev, "Failed to register reset controller: %pe\n", + pericfg->reset_data); + return PTR_ERR(pericfg->reset_data); + } + + return 0; +unregister_gates: + mtk_clk_unregister_gates(pericfg_gates, ARRAY_SIZE(pericfg_gates), + pericfg->clk_data); +free_clk_data: + mtk_free_clk_data(pericfg->clk_data); + + return ret; +} + +int clk_mt6735_pericfg_remove(struct platform_device *pdev) +{ + struct mt6735_pericfg *pericfg =3D platform_get_drvdata(pdev); + + mtk_unregister_reset_controller(pericfg->reset_data); + of_clk_del_provider(pdev->dev.of_node); + mtk_clk_unregister_gates(pericfg_gates, ARRAY_SIZE(pericfg_gates), + pericfg->clk_data); + mtk_free_clk_data(pericfg->clk_data); + + return 0; +} + +static const struct of_device_id of_match_mt6735_pericfg[] =3D { + { .compatible =3D "mediatek,mt6735-pericfg" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_pericfg =3D { + .probe =3D clk_mt6735_pericfg_probe, + .remove =3D clk_mt6735_pericfg_remove, + .driver =3D { + .name =3D "clk-mt6735-pericfg", + .of_match_table =3D of_match_mt6735_pericfg, + }, +}; +module_platform_driver(clk_mt6735_pericfg); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 pericfg clock driver"); +MODULE_LICENSE("GPL"); --=20 2.36.0