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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:33:15 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/13] clk: mediatek: Add driver for MT6735 infracfg Date: Wed, 4 May 2022 16:26:01 +0400 Message-Id: <20220504122601.335495-13-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add a driver for MT6735 infracfg clock gates and resets. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 1 + drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-infracfg.c | 265 +++++++++++++++++++++ 4 files changed, 274 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c diff --git a/MAINTAINERS b/MAINTAINERS index d9d6449f910e..8662f12f34a2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12443,6 +12443,7 @@ L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixed.c +F: drivers/clk/mediatek/clk-mt6735-infracfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 7c19e2d7bb02..62195e5d90a0 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -124,6 +124,13 @@ config COMMON_CLK_MT6735_APMIXED help This driver supports MediaTek MT6735 apmixedsys clocks. =20 +config COMMON_CLK_MT6735_INFRACFG + tristate "Clock driver for MediaTek MT6735 infracfg" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This driver supports MediaTek MT6735 infracfg clocks and resets. + config COMMON_CLK_MT6735_TOPCKGEN tristate "Clock driver for MediaTek MT6735 topckgen" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e8e892c4145f..e5c1da6e2711 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mtk.o clk-pll.o clk-gate.o clk-= apmixed.o clk-cpumux.o reset.o clk-mux.o =20 obj-$(CONFIG_COMMON_CLK_MT6735_APMIXED) +=3D clk-mt6735-apmixed.o +obj-$(CONFIG_COMMON_CLK_MT6735_INFRACFG) +=3D clk-mt6735-infracfg.o obj-$(CONFIG_COMMON_CLK_MT6735_TOPCKGEN) +=3D clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6765) +=3D clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) +=3D clk-mt6765-audio.o diff --git a/drivers/clk/mediatek/clk-mt6735-infracfg.c b/drivers/clk/media= tek/clk-mt6735-infracfg.c new file mode 100644 index 000000000000..ce1a5739b3b2 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-infracfg.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define INFRA_RST0 0x30 +#define INFRA_GLOBALCON_PDN0 0x40 +#define INFRA_PDN1 0x44 +#define INFRA_PDN_STA 0x48 + +struct mt6735_infracfg { + struct clk_onecell_data *clk_data; + struct mtk_reset *reset_data; +}; + +static struct mtk_gate_regs infra_cg_regs =3D { + .set_ofs =3D INFRA_GLOBALCON_PDN0, + .clr_ofs =3D INFRA_PDN1, + .sta_ofs =3D INFRA_PDN_STA, +}; + +static const struct mtk_gate infracfg_gates[] =3D { + { + .id =3D DBGCLK, + .name =3D "dbgclk", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 0, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D GCE, + .name =3D "gce", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 1, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D TRBG, + .name =3D "trbg", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 2, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CPUM, + .name =3D "cpum", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 3, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D DEVAPC, + .name =3D "devapc", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 4, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D AUDIO, + .name =3D "audio", + .parent_name =3D "aud_intbus_sel", + .regs =3D &infra_cg_regs, + .shift =3D 5, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D GCPU, + .name =3D "gcpu", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 6, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D L2C_SRAM, + .name =3D "l2csram", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 7, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D M4U, + .name =3D "m4u", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 8, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CLDMA, + .name =3D "cldma", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 12, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CONNMCU_BUS, + .name =3D "connmcu_bus", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 15, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D KP, + .name =3D "kp", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 16, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D APXGPT, + .name =3D "apxgpt", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 18, + .ops =3D &mtk_clk_gate_ops_setclr, + .flags =3D CLK_IS_CRITICAL + }, + { + .id =3D SEJ, + .name =3D "sej", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 19, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CCIF0_AP, + .name =3D "ccif0ap", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 20, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CCIF1_AP, + .name =3D "ccif1ap", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 21, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PMIC_SPI, + .name =3D "pmicspi", + .parent_name =3D "pmicspi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 22, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PMIC_WRAP, + .name =3D "pmicwrap", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 23, + .ops =3D &mtk_clk_gate_ops_setclr + }, +}; + +int clk_mt6735_infracfg_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct resource *res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct mt6735_infracfg *infracfg; + int ret; + + base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + infracfg =3D devm_kmalloc(&pdev->dev, sizeof(struct mt6735_infracfg), + GFP_KERNEL); + if (!infracfg) + return -ENOMEM; + + infracfg->clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(infracfg_gates)); + if (!infracfg->clk_data) + return -ENOMEM; + platform_set_drvdata(pdev, infracfg); + + ret =3D mtk_clk_register_gates_with_dev(pdev->dev.of_node, infracfg_gates, + ARRAY_SIZE(infracfg_gates), + infracfg->clk_data, &pdev->dev); + if (ret) { + dev_err(&pdev->dev, "Failed to register gates: %pe\n", + ERR_PTR(ret)); + goto free_clk_data; + } + + ret =3D of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + infracfg->clk_data); + if (ret) { + dev_err(&pdev->dev, "Failed to register clock provider: %pe\n", + ERR_PTR(ret)); + goto unregister_gates; + } + + infracfg->reset_data =3D mtk_register_reset_controller(pdev->dev.of_node, + 1, INFRA_RST0); + if (IS_ERR(infracfg->reset_data)) { + dev_err(&pdev->dev, "Failed to register reset controller: %pe\n", + infracfg->reset_data); + return PTR_ERR(infracfg->reset_data); + } + + return 0; + +unregister_gates: + mtk_clk_unregister_gates(infracfg_gates, ARRAY_SIZE(infracfg_gates), + infracfg->clk_data); +free_clk_data: + mtk_free_clk_data(infracfg->clk_data); + + return ret; +} + +int clk_mt6735_infracfg_remove(struct platform_device *pdev) +{ + struct mt6735_infracfg *infracfg =3D platform_get_drvdata(pdev); + + mtk_unregister_reset_controller(infracfg->reset_data); + of_clk_del_provider(pdev->dev.of_node); + mtk_clk_unregister_gates(infracfg_gates, ARRAY_SIZE(infracfg_gates), + infracfg->clk_data); + mtk_free_clk_data(infracfg->clk_data); + + return 0; +} + +static const struct of_device_id of_match_mt6735_infracfg[] =3D { + { .compatible =3D "mediatek,mt6735-infracfg" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_infracfg =3D { + .probe =3D clk_mt6735_infracfg_probe, + .remove =3D clk_mt6735_infracfg_remove, + .driver =3D { + .name =3D "clk-mt6735-infracfg", + .of_match_table =3D of_match_mt6735_infracfg, + }, +}; +module_platform_driver(clk_mt6735_infracfg); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 infracfg clock and reset driver"); +MODULE_LICENSE("GPL"); --=20 2.36.0