From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 292C6C433FE for ; Wed, 4 May 2022 12:30:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349538AbiEDMeU (ORCPT ); Wed, 4 May 2022 08:34:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240502AbiEDMeS (ORCPT ); Wed, 4 May 2022 08:34:18 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C58C414099; Wed, 4 May 2022 05:30:41 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id gh6so2627798ejb.0; Wed, 04 May 2022 05:30:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ysH00HyaDWMX3g6z4wMVizpKRp8qVpyqeMYEzT6C4WY=; b=UmOQeFRlgk1stR2NmLpQW+SDcyKo7NYlY5RN8eB9sAoG+7DFYiW5P69CUQ14Qswzee 8uadORkcp8BMGnvvz59WqMr+rlTLKLDiCY6QTIrQh6HCWFhw4JTJVnUw1zrmoGSZ+JJw TG4g2tKBxg9j+aUx81OAbAxxyanm/A/VIPcqjFiO43okoqNbsqziHTHKp8M4/yWIE5ID hWZ0+2ZKMkfDpa8F+CVv8oisIF1QuowYHmTAFIKw41+0G3YctIj03YPxOYPitcUqP29g d6fivTck2GEhetzgC44rVRxV1i5iYNECGt80oOs1s0clzm2IvDE4qspPT5pxq27vcTJ+ CA7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ysH00HyaDWMX3g6z4wMVizpKRp8qVpyqeMYEzT6C4WY=; b=sWIB4c5Ej3PJPYNpaKIaFSP7fd7zNIS7d/zT2e2LmMoUyrGZZGIVWWOjeJefMVcDQU 03JPxABrF9Jx12E4Jblc090WhelrpjJVUvhXgafLo06Gg+2h5w3rC5RIK9SUtqoZ9GV4 OByIgnHO17GEQG8iRUMGE/UX7dqNoIUVO4hyHUWsqPbxTnsPIhGPQfQsGiwyJqLdSi8p oar/CRC2ZTAYUC0+yPbGnhcwo6oFxUY7EPtXrAIC9hrCgo/D0cSqigoq+n/5Y9fsD0ta atrQO5ERf8+/rC7S4f/NMTnGun/0HLxXFn9zh8H1sEsYWZratiJ5bAMsJKTWNw1DEWX4 xzrw== X-Gm-Message-State: AOAM533ZXhSirDkp4QQN1dL5mwkhZZcuMngonEwh0Gkl/w4wDvIObb0t +0MWx/Ej1SRJ74V9HR2mNKE= X-Google-Smtp-Source: ABdhPJzqrcu+vGdjVz8arDFDG21wP7cRG4mf/U2UT7S5YNTI5mlnaRQ/efBX7UUbFJ6GRQov/bRnlA== X-Received: by 2002:a17:907:3f16:b0:6f4:c54:2700 with SMTP id hq22-20020a1709073f1600b006f40c542700mr20290260ejc.615.1651667440245; Wed, 04 May 2022 05:30:40 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.30.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:30:39 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 01/13] dt-bindings: clock: Add Mediatek MT6735 clock bindings Date: Wed, 4 May 2022 16:25:50 +0400 Message-Id: <20220504122601.335495-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add clock definitions for Mediatek MT6735 clocks provided by apmixedsys, topckgen, infracfg and pericfg. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring --- MAINTAINERS | 10 +++ .../clock/mediatek,mt6735-apmixedsys.h | 16 ++++ .../clock/mediatek,mt6735-infracfg.h | 25 ++++++ .../clock/mediatek,mt6735-pericfg.h | 37 +++++++++ .../clock/mediatek,mt6735-topckgen.h | 79 +++++++++++++++++++ 5 files changed, 167 insertions(+) create mode 100644 include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-pericfg.h create mode 100644 include/dt-bindings/clock/mediatek,mt6735-topckgen.h diff --git a/MAINTAINERS b/MAINTAINERS index 2869a958f5e4..e917039b9d8c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12437,6 +12437,16 @@ S: Maintained F: Documentation/devicetree/bindings/mmc/mtk-sd.yaml F: drivers/mmc/host/mtk-sd.c =20 +MEDIATEK MT6735 CLOCK DRIVERS +M: Yassine Oudjana +L: linux-clk@vger.kernel.org +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h +F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h +F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h +F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h + MEDIATEK MT76 WIRELESS LAN DRIVER M: Felix Fietkau M: Lorenzo Bianconi diff --git a/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h b/inclu= de/dt-bindings/clock/mediatek,mt6735-apmixedsys.h new file mode 100644 index 000000000000..3dda719fd5d5 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H +#define _DT_BINDINGS_CLK_MT6735_APMIXEDSYS_H + +#define ARMPLL 0 +#define MAINPLL 1 +#define UNIVPLL 2 +#define MMPLL 3 +#define MSDCPLL 4 +#define VENCPLL 5 +#define TVDPLL 6 +#define APLL1 7 +#define APLL2 8 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-infracfg.h b/include= /dt-bindings/clock/mediatek,mt6735-infracfg.h new file mode 100644 index 000000000000..979a174ff8b6 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-infracfg.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H +#define _DT_BINDINGS_CLK_MT6735_INFRACFG_H + +#define DBGCLK 0 +#define GCE 1 +#define TRBG 2 +#define CPUM 3 +#define DEVAPC 4 +#define AUDIO 5 +#define GCPU 6 +#define L2C_SRAM 7 +#define M4U 8 +#define CLDMA 9 +#define CONNMCU_BUS 10 +#define KP 11 +#define APXGPT 12 +#define SEJ 13 +#define CCIF0_AP 14 +#define CCIF1_AP 15 +#define PMIC_SPI 16 +#define PMIC_WRAP 17 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-pericfg.h b/include/= dt-bindings/clock/mediatek,mt6735-pericfg.h new file mode 100644 index 000000000000..16f3c6a9a772 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-pericfg.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_PERICFG_H +#define _DT_BINDINGS_CLK_MT6735_PERICFG_H + +#define DISP_PWM 0 +#define THERM 1 +#define PWM1 2 +#define PWM2 3 +#define PWM3 4 +#define PWM4 5 +#define PWM5 6 +#define PWM6 7 +#define PWM7 8 +#define PWM 9 +#define USB0 10 +#define IRDA 11 +#define APDMA 12 +#define MSDC30_0 13 +#define MSDC30_1 14 +#define MSDC30_2 15 +#define MSDC30_3 16 +#define UART0 17 +#define UART1 18 +#define UART2 19 +#define UART3 20 +#define UART4 21 +#define BTIF 22 +#define I2C0 23 +#define I2C1 24 +#define I2C2 25 +#define I2C3 26 +#define AUXADC 27 +#define SPI0 28 +#define IRTX 29 + +#endif diff --git a/include/dt-bindings/clock/mediatek,mt6735-topckgen.h b/include= /dt-bindings/clock/mediatek,mt6735-topckgen.h new file mode 100644 index 000000000000..a771910a4b8a --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt6735-topckgen.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H +#define _DT_BINDINGS_CLK_MT6735_TOPCKGEN_H + +#define AD_SYS_26M_CK 0 +#define CLKPH_MCK_O 1 +#define DMPLL 2 +#define DPI_CK 3 +#define WHPLL_AUDIO_CK 4 + +#define SYSPLL_D2 5 +#define SYSPLL_D3 6 +#define SYSPLL_D5 7 +#define SYSPLL1_D2 8 +#define SYSPLL1_D4 9 +#define SYSPLL1_D8 10 +#define SYSPLL1_D16 11 +#define SYSPLL2_D2 12 +#define SYSPLL2_D4 13 +#define SYSPLL3_D2 14 +#define SYSPLL3_D4 15 +#define SYSPLL4_D2 16 +#define SYSPLL4_D4 17 +#define UNIVPLL_D2 18 +#define UNIVPLL_D3 19 +#define UNIVPLL_D5 20 +#define UNIVPLL_D26 21 +#define UNIVPLL1_D2 22 +#define UNIVPLL1_D4 23 +#define UNIVPLL1_D8 24 +#define UNIVPLL2_D2 25 +#define UNIVPLL2_D4 26 +#define UNIVPLL2_D8 27 +#define UNIVPLL3_D2 28 +#define UNIVPLL3_D4 29 +#define MSDCPLL_D2 30 +#define MSDCPLL_D4 31 +#define MSDCPLL_D8 32 +#define MSDCPLL_D16 33 +#define VENCPLL_D3 34 +#define TVDPLL_D2 35 +#define TVDPLL_D4 36 +#define DMPLL_D2 37 +#define DMPLL_D4 38 +#define DMPLL_D8 39 +#define AD_SYS_26M_D2 40 + +#define AXI_SEL 41 +#define MEM_SEL 42 +#define DDRPHY_SEL 43 +#define MM_SEL 44 +#define PWM_SEL 45 +#define VDEC_SEL 46 +#define MFG_SEL 47 +#define CAMTG_SEL 48 +#define UART_SEL 49 +#define SPI_SEL 50 +#define USB20_SEL 51 +#define MSDC50_0_SEL 52 +#define MSDC30_0_SEL 53 +#define MSDC30_1_SEL 54 +#define MSDC30_2_SEL 55 +#define MSDC30_3_SEL 56 +#define AUDIO_SEL 57 +#define AUDINTBUS_SEL 58 +#define PMICSPI_SEL 59 +#define SCP_SEL 60 +#define ATB_SEL 61 +#define DPI0_SEL 62 +#define SCAM_SEL 63 +#define MFG13M_SEL 64 +#define AUD1_SEL 65 +#define AUD2_SEL 66 +#define IRDA_SEL 67 +#define IRTX_SEL 68 +#define DISPPWM_SEL 69 + +#endif --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:16 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 02/13] dt-bindings: reset: Add MT6735 reset bindings Date: Wed, 4 May 2022 16:25:51 +0400 Message-Id: <20220504122601.335495-3-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add reset definitions for Mediatek MT6735 resets provided by infracfg and pericfg. Signed-off-by: Yassine Oudjana Acked-by: Rob Herring --- MAINTAINERS | 2 ++ .../reset/mediatek,mt6735-infracfg.h | 31 +++++++++++++++++++ .../reset/mediatek,mt6735-pericfg.h | 31 +++++++++++++++++++ 3 files changed, 64 insertions(+) create mode 100644 include/dt-bindings/reset/mediatek,mt6735-infracfg.h create mode 100644 include/dt-bindings/reset/mediatek,mt6735-pericfg.h diff --git a/MAINTAINERS b/MAINTAINERS index e917039b9d8c..de15c3d50d2d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12446,6 +12446,8 @@ F: include/dt-bindings/clock/mediatek,mt6735-apmixe= dsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h F: include/dt-bindings/clock/mediatek,mt6735-topckgen.h +F: include/dt-bindings/reset/mediatek,mt6735-infracfg.h +F: include/dt-bindings/reset/mediatek,mt6735-pericfg.h =20 MEDIATEK MT76 WIRELESS LAN DRIVER M: Felix Fietkau diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include= /dt-bindings/reset/mediatek,mt6735-infracfg.h new file mode 100644 index 000000000000..86448f946568 --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RST_MT6735_INFRACFG_H +#define _DT_BINDINGS_RST_MT6735_INFRACFG_H + +#define EMI_REG_RST 0 +#define DRAMC0_AO_RST 1 +#define AP_CIRQ_EINT_RST 3 +#define APXGPT_RST 4 +#define SCPSYS_RST 5 +#define KP_RST 6 +#define PMIC_WRAP_RST 7 +#define CLDMA_AO_TOP_RST 8 +#define EMI_RST 16 +#define CCIF_RST 17 +#define DRAMC0_RST 18 +#define EMI_AO_REG_RST 19 +#define CCIF_AO_RST 20 +#define TRNG_RST 21 +#define SYS_CIRQ_RST 22 +#define GCE_RST 23 +#define MM_IOMMU_RST 24 +#define CCIF1_RST 25 +#define CLDMA_TOP_PD_RST 26 +#define CBIP_P2P_MFG 27 +#define CBIP_P2P_APMIXED 28 +#define CBIP_P2P_CKSYS 29 +#define CBIP_P2P_MIPI 30 +#define CBIP_P2P_DDRPHY 31 + +#endif diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/= dt-bindings/reset/mediatek,mt6735-pericfg.h new file mode 100644 index 000000000000..6cdfaa7ddadf --- /dev/null +++ b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_RST_MT6735_PERICFG_H +#define _DT_BINDINGS_RST_MT6735_PERICFG_H + +#define UART0_SW_RST 0 +#define UART1_SW_RST 1 +#define UART2_SW_RST 2 +#define UART3_SW_RST 3 +#define UART4_SW_RST 4 +#define BTIF_SW_RST 6 +#define DISP_PWM_SW_RST 7 +#define PWM_SW_RST 8 +#define AUXADC_SW_RST 10 +#define DMA_SW_RST 11 +#define IRDA_SW_RST 12 +#define IRTX_SW_RST 13 +#define THERM_SW_RST 16 +#define MSDC2_SW_RST 17 +#define MSDC3_SW_RST 17 +#define MSDC0_SW_RST 19 +#define MSDC1_SW_RST 20 +#define I2C0_SW_RST 22 +#define I2C1_SW_RST 23 +#define I2C2_SW_RST 24 +#define I2C3_SW_RST 25 +#define USB_SW_RST 28 + +#define SPI0_SW_RST 33 + +#endif --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04983C433EF for ; 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:22 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 03/13] dt-bindings: arm: mediatek: Add MT6735 clock controller compatibles Date: Wed, 4 May 2022 16:25:52 +0400 Message-Id: <20220504122601.335495-4-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add compatible strings for MT6735 apmixedsys, topckgen, infracfg and pericfg. Signed-off-by: Yassine Oudjana Reviewed-by: Rob Herring --- .../bindings/arm/mediatek/mediatek,infracfg.yaml | 8 +++++--- .../bindings/arm/mediatek/mediatek,pericfg.yaml | 1 + .../devicetree/bindings/clock/mediatek,apmixedsys.yaml | 4 +++- .../devicetree/bindings/clock/mediatek,topckgen.yaml | 4 +++- 4 files changed, 12 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infrac= fg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.= yaml index 8681b785ed6d..aa1bb13e0d67 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml @@ -11,9 +11,10 @@ maintainers: =20 description: The Mediatek infracfg controller provides various clocks and reset outpu= ts - to the system. The clock values can be found in , - and reset values in and - . + to the system. The clock values can be found in + and , and reset values in + , and + . =20 properties: compatible: @@ -22,6 +23,7 @@ properties: - enum: - mediatek,mt2701-infracfg - mediatek,mt2712-infracfg + - mediatek,mt6735-infracfg - mediatek,mt6765-infracfg - mediatek,mt6779-infracfg_ao - mediatek,mt6797-infracfg diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericf= g.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.ya= ml index 611f666f359d..94e5e003e60e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml @@ -20,6 +20,7 @@ properties: - enum: - mediatek,mt2701-pericfg - mediatek,mt2712-pericfg + - mediatek,mt6735-pericfg - mediatek,mt6765-pericfg - mediatek,mt7622-pericfg - mediatek,mt7629-pericfg diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.ya= ml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml index 770546195fb5..3a186621e7a9 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml @@ -12,7 +12,8 @@ maintainers: =20 description: The Mediatek apmixedsys controller provides PLLs to the system. - The clock values can be found in . + The clock values can be found in + and . =20 properties: compatible: @@ -32,6 +33,7 @@ properties: - enum: - mediatek,mt2701-apmixedsys - mediatek,mt2712-apmixedsys + - mediatek,mt6735-apmixedsys - mediatek,mt6765-apmixedsys - mediatek,mt6779-apmixedsys - mediatek,mt7629-apmixedsys diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml= b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml index 5b8b37a2e594..920bf0828d58 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml @@ -12,7 +12,8 @@ maintainers: =20 description: The Mediatek topckgen controller provides various clocks to the system. - The clock values can be found in . + The clock values can be found in and + . =20 properties: compatible: @@ -31,6 +32,7 @@ properties: - enum: - mediatek,mt2701-topckgen - mediatek,mt2712-topckgen + - mediatek,mt6735-topckgen - mediatek,mt6765-topckgen - mediatek,mt6779-topckgen - mediatek,mt7629-topckgen --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD3BCC433EF for ; Wed, 4 May 2022 12:32:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240187AbiEDMgS (ORCPT ); Wed, 4 May 2022 08:36:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349601AbiEDMgG (ORCPT ); Wed, 4 May 2022 08:36:06 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0A703057C; Wed, 4 May 2022 05:32:30 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id g23so1502743edy.13; Wed, 04 May 2022 05:32:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UYV9WwfLVrhrjjukDe9qosCTrZP5yItzO2ZQyMR1lZc=; b=clzbEqsXQv/9j5beNysVRxnHh7EbfdL42WEK+sogVY160hfxT5oK2+IR1IBBklte5t ljb7kUC16gyqCia6Y1DO9VfnKQsmElv94rsEBhm5/71Ump62UeGSLcIRqAhZNNoIcDrj /d2+1GCvvxljr4i4IwSxzd+zN7RmCWZwPgTid2EQU7r4zlXhXfOVzt4oK/5ZrDB6/15V LI78hx3bZppBPCqu/mae/VXn0rWFnZwnac5Mc3eTK4HJ1KKYp/ut3KogNLUhyHK16mSc WsdMo1j0Ep4IrzcvMfA7hofu9ZE4xpIeqaz9iFbXt7Vh+BMyk8g4n2fje+1RsfQgxg4e OPYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UYV9WwfLVrhrjjukDe9qosCTrZP5yItzO2ZQyMR1lZc=; b=VjJHnK9K6MSeJLwkcAbSikmBNYlqjGDW1gaiBKpsL75aViuOk2DoBeDBLMSBnvoY+b idVM16OS4t68cSvd0W+6opJG8NlAvs/gqbcYse6W40QXjW2Wc8Y7TUvZE6bPR7Yck44t 8BzIG4patHR/H+QklqnUemaks7k/OZPMOD33SNa1Bslg03yRbHLGutwRqWk8cbl0VKkZ ZYgci+AmpAR1T6KRlJXF34JIXEr68THNZqFLadBb6pywT1Uwwzqo4qcmkNI0Pu4Ni4no HySdSkX5puqEmOlUuZKDRO/fYEaDk1NOiTlHrOFazgzbXJqcx32Jid22hipnJH9d9lNZ qF7Q== X-Gm-Message-State: AOAM530sFDJravAd/+64Kxk1UupO73Y+3Sa9AfZD2IhAen5UOcA+hZRk RrbpDp/F+8FlkWtNH5HfUhU= X-Google-Smtp-Source: ABdhPJz9W/mMV44IrVK/27fYXrCOAHDuuLtFYy0c/F+TRA1NVYOwalt2veeTybfEqPXiQUKHfnL3eg== X-Received: by 2002:a05:6402:d05:b0:425:b7ab:776e with SMTP id eb5-20020a0564020d0500b00425b7ab776emr23169472edb.142.1651667549307; Wed, 04 May 2022 05:32:29 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:28 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 04/13] clk: composite: Export clk_unregister_composite Date: Wed, 4 May 2022 16:25:53 +0400 Message-Id: <20220504122601.335495-5-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana This is required to build the Mediatek clock core as a module. Doing so currently fails: ERROR: modpost: "clk_unregister_composite" [drivers/clk/mediatek/clk-mtk.ko= ] undefined! Fixes: cb50864f6cee ("clk: mediatek: Implement mtk_clk_unregister_composite= s() API") Signed-off-by: Yassine Oudjana --- drivers/clk/clk-composite.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index b9c5f904f535..0935a54c9d81 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -425,6 +425,7 @@ void clk_unregister_composite(struct clk *clk) clk_unregister(clk); kfree(composite); } +EXPORT_SYMBOL_GPL(clk_unregister_composite); =20 void clk_hw_unregister_composite(struct clk_hw *hw) { --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 826FFC4332F for ; Wed, 4 May 2022 12:32:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349635AbiEDMgW (ORCPT ); Wed, 4 May 2022 08:36:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349586AbiEDMgQ (ORCPT ); Wed, 4 May 2022 08:36:16 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D42030F65; Wed, 4 May 2022 05:32:36 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id l18so2582713ejc.7; Wed, 04 May 2022 05:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CNKzAxju2H5F78AxmBtE86NJhowOrzcymru33IBzxRo=; b=fhgI+VpoueobRqvh9tlA+tLmknI0/GBMBlZVChuFNtle9pQIpmqvLOhKfM6Dmjr1xw R3/4j2ipVTMcLVfcdiFVhPLlaPqRNY5t3H+rxBSFArOYE5xwpZxH3Jq/6mwZQVR5g5nH DS3m+OPLGiWRLFkR1OgFSMe8XxRKuEH9W86Sit7CTWaS36IS1BcjrV89ZJ+WtFIIoN5V SMHkwP1Nl0jDUWaKx2biMH+3mBhtuY+mAxeY2i82RlP9W3AZmkdHxsVek7a/DNULJQMK QeOxtBznr+PojfyE1rhzKOyrX/n2xr6Tt/U/VTGSbiKJy7ewUjeVFX4fuW8b/wFLsQHw dYPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CNKzAxju2H5F78AxmBtE86NJhowOrzcymru33IBzxRo=; b=LHQOpehIJ1Hurb3xWnwrkhyESwzosbRzkTY2X9AZpjU9RiMuI8MJM649fzjVC23Zqs 5Om1LfB8Yf/K0dI04D1jC0hHOzM9qkQ1kE0LT1/KtTQrdYwGq+NLx0H2VqUSNL1vjnZ9 UbjZR63M3XTERR46GyTXE7eOiE5cxtgxIpp8wtvidWaCxnuIegJdpZSsugZEjKTII0fF zNPuue4qwFwO9XgFudF2NkGm9nwAqp0FfNBbe2Vs14zbpYu2JoAzMNRoWbEYkbrxra2u FU04v3EWXydS2AxsTGKKQHoZQfBWRpI1bRoS8Ab6bX0CMNalT5tRy8E38mc/1bKOrLGW jzbQ== X-Gm-Message-State: AOAM532A3BWJX6qhQCDyK0VekUf6BCH0M76JPTNcUsfebjkGluSU1M8r lR7hxpvrLYdLdsaQMj+/lVs= X-Google-Smtp-Source: ABdhPJz1LfNQyXPrgPpEVU72LKcwzEzy3aEBePRzfJCjCXhN8ogrNFGeDXHVMFOxKgDBPTqeQGtifQ== X-Received: by 2002:a17:907:980d:b0:6d6:f910:513a with SMTP id ji13-20020a170907980d00b006d6f910513amr18770753ejc.643.1651667555088; Wed, 04 May 2022 05:32:35 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:34 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 05/13] clk: mediatek: Export mtk_free_clk_data Date: Wed, 4 May 2022 16:25:54 +0400 Message-Id: <20220504122601.335495-6-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Export mtk_free_clk_data to allow using it in clock drivers built as modules. Signed-off-by: Yassine Oudjana --- drivers/clk/mediatek/clk-mtk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index b4063261cf56..0746b0f5beda 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -52,6 +52,7 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_data) kfree(clk_data->clks); kfree(clk_data); } +EXPORT_SYMBOL_GPL(mtk_free_clk_data); =20 int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num, struct clk_onecell_data *clk_data) --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00796C433EF for ; Wed, 4 May 2022 12:32:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349613AbiEDMgY (ORCPT ); Wed, 4 May 2022 08:36:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349646AbiEDMgU (ORCPT ); Wed, 4 May 2022 08:36:20 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9926925E96; Wed, 4 May 2022 05:32:42 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id bv19so2587229ejb.6; Wed, 04 May 2022 05:32:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nBKA3UWWI9ka6cADxyOyqQzWUHiKDpIGUD+hMYCWwIE=; b=IyuGDa6VlGR8uuGgrygUdtZZA5TYqkZHkTBcLz+i70K9r+1qT8CbupcEsDQTytvDhw Y9K4JOoTspW2qMnjuniMQ3KmpsPvcIEEsMz7zT4woWw8Dcz1G9KaMHPew+nml4bFPyBH fchFcSRfPi+Mj2wS2r5oOsNSpLDNKPg3OZVAzL4MGx5me1tNRdFRMl5+zb1fir2fpSaH 3Ka/fgqO72ar+MmR81PLsewQqPsqzpEDqTJVO4ogn2nBIswn/PMZOgXzFC9k458Q8C1r Z5u/3nkYuxWTg0eERZQVbxU87/8s/HpT4ysl6+lMnYDX337XhVtm5+rMz8xoOdeyPre7 TZmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nBKA3UWWI9ka6cADxyOyqQzWUHiKDpIGUD+hMYCWwIE=; b=UoYWuWhyjDS4RXF9oVQpeG927wznsdY+wYtc+cSNoBCR6/6HlcX1p1dGJemObIgoWV GSuDWKppZmMNJbiqvLmWgp72R496kROZ1h5vNTOdConU4WFrurAhYc6uWRP6S7hIAulD 648Xv+xIAhxv60PwTNliFtGMc9LvEb3DLPurai5pEPG7ihkgyMUEsImduRJQNI4VXfB4 +fiX880pjEhcW4pAYSWDyVulvvSlGHpN/FGjDn/HkgtPEF0Fp760CutMh1d1paeTK+CT x60nBUsDozZk5TL6senBNtsHwUJc0pAhiEmQ7lhcPoIC4WmUzxiI6nXog1jRyShLcGLH 8IWw== X-Gm-Message-State: AOAM532MpTY7HKf/m17ZVL+OtPqjvMN2GegC3TpdmerMWI5akyUFQ05F ganvVOveTh9S1r3VZSz+l4M= X-Google-Smtp-Source: ABdhPJyh3RaGuyNMpjEnKgDQjawtnF9SoXDPNlstOvMG1X0fvWRNarG3SkkNIl/eZ8ahLkcMZBxLAA== X-Received: by 2002:a17:906:4985:b0:6ef:b344:2a56 with SMTP id p5-20020a170906498500b006efb3442a56mr20451501eju.625.1651667560889; Wed, 04 May 2022 05:32:40 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:40 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 06/13] clk: mediatek: Add driver for MT6735 apmixedsys Date: Wed, 4 May 2022 16:25:55 +0400 Message-Id: <20220504122601.335495-7-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add a driver for MT6735 apmixedsys PLLs. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 1 + drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-apmixed.c | 274 ++++++++++++++++++++++ 4 files changed, 283 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-apmixed.c diff --git a/MAINTAINERS b/MAINTAINERS index de15c3d50d2d..1077712edb4b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12442,6 +12442,7 @@ M: Yassine Oudjana L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: drivers/clk/mediatek/clk-mt6735-apmixed.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index d5936cfb3bee..ab364892f602 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -117,6 +117,13 @@ config COMMON_CLK_MT2712_VENCSYS help This driver supports MediaTek MT2712 vencsys clocks. =20 +config COMMON_CLK_MT6735_APMIXED + tristate "Clock driver for MediaTek MT6735 apmixedsys" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This driver supports MediaTek MT6735 apmixedsys clocks. + config COMMON_CLK_MT6765 bool "Clock driver for MediaTek MT6765" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index caf2ce93d666..7f45a22c6178 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mtk.o clk-pll.o clk-gate.o clk-= apmixed.o clk-cpumux.o reset.o clk-mux.o =20 +obj-$(CONFIG_COMMON_CLK_MT6735_APMIXED) +=3D clk-mt6735-apmixed.o obj-$(CONFIG_COMMON_CLK_MT6765) +=3D clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) +=3D clk-mt6765-audio.o obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) +=3D clk-mt6765-cam.o diff --git a/drivers/clk/mediatek/clk-mt6735-apmixed.c b/drivers/clk/mediat= ek/clk-mt6735-apmixed.c new file mode 100644 index 000000000000..6c4ec77d1d19 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-apmixed.c @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-mtk.h" +#include "clk-pll.h" + +#include + +#define AP_PLL_CON_5 0x014 +#define ARMPLL_CON0 0x200 +#define ARMPLL_CON1 0x204 +#define ARMPLL_PWR_CON0 0x20c +#define MAINPLL_CON0 0x210 +#define MAINPLL_CON1 0x214 +#define MAINPLL_PWR_CON0 0x21c +#define UNIVPLL_CON0 0x220 +#define UNIVPLL_CON1 0x224 +#define UNIVPLL_PWR_CON0 0x22c +#define MMPLL_CON0 0x230 +#define MMPLL_CON1 0x234 +#define MMPLL_PWR_CON0 0x23c +#define MSDCPLL_CON0 0x240 +#define MSDCPLL_CON1 0x244 +#define MSDCPLL_PWR_CON0 0x24c +#define VENCPLL_CON0 0x250 +#define VENCPLL_CON1 0x254 +#define VENCPLL_PWR_CON0 0x25c +#define TVDPLL_CON0 0x260 +#define TVDPLL_CON1 0x264 +#define TVDPLL_PWR_CON0 0x26c +#define APLL1_CON0 0x270 +#define APLL1_CON1 0x274 +#define APLL1_CON2 0x278 +#define APLL1_PWR_CON0 0x27c +#define APLL2_CON0 0x280 +#define APLL2_CON1 0x284 +#define APLL2_CON2 0x288 +#define APLL2_PWR_CON0 0x28c + +#define CON0_RST_BAR BIT(24) + +static const struct mtk_pll_data apmixed_plls[] =3D { + { + .id =3D ARMPLL, + .name =3D "armpll", + .parent_name =3D "clk26m", + + .reg =3D ARMPLL_CON0, + .pwr_reg =3D ARMPLL_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D ARMPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D ARMPLL_CON1, + .pcw_chg_reg =3D ARMPLL_CON1, + .pcwbits =3D 21, + + .flags =3D PLL_AO + }, + { + .id =3D MAINPLL, + .name =3D "mainpll", + .parent_name =3D "clk26m", + + .reg =3D MAINPLL_CON0, + .pwr_reg =3D MAINPLL_PWR_CON0, + .en_mask =3D 0xf0000101, + + .pd_reg =3D MAINPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D MAINPLL_CON1, + .pcw_chg_reg =3D MAINPLL_CON1, + .pcwbits =3D 21, + + .flags =3D HAVE_RST_BAR, + .rst_bar_mask =3D CON0_RST_BAR + }, + { + .id =3D UNIVPLL, + .name =3D "univpll", + .parent_name =3D "clk26m", + + .reg =3D UNIVPLL_CON0, + .pwr_reg =3D UNIVPLL_PWR_CON0, + .en_mask =3D 0xfc000001, + + .pd_reg =3D UNIVPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D UNIVPLL_CON1, + .pcw_chg_reg =3D UNIVPLL_CON1, + .pcwbits =3D 21, + + .flags =3D HAVE_RST_BAR, + .rst_bar_mask =3D CON0_RST_BAR + }, + { + .id =3D MMPLL, + .name =3D "mmpll", + .parent_name =3D "clk26m", + + .reg =3D MMPLL_CON0, + .pwr_reg =3D MMPLL_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D MMPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D MMPLL_CON1, + .pcw_chg_reg =3D MMPLL_CON1, + .pcwbits =3D 21 + }, + { + .id =3D MSDCPLL, + .name =3D "msdcpll", + .parent_name =3D "clk26m", + + .reg =3D MSDCPLL_CON0, + .pwr_reg =3D MSDCPLL_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D MSDCPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D MSDCPLL_CON1, + .pcw_chg_reg =3D MSDCPLL_CON1, + .pcwbits =3D 21, + }, + { + .id =3D VENCPLL, + .name =3D "vencpll", + .parent_name =3D "clk26m", + + .reg =3D VENCPLL_CON0, + .pwr_reg =3D VENCPLL_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D VENCPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D VENCPLL_CON1, + .pcw_chg_reg =3D VENCPLL_CON1, + .pcwbits =3D 21, + + .flags =3D HAVE_RST_BAR, + .rst_bar_mask =3D CON0_RST_BAR + }, + { + .id =3D TVDPLL, + .name =3D "tvdpll", + .parent_name =3D "clk26m", + + .reg =3D TVDPLL_CON0, + .pwr_reg =3D TVDPLL_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D TVDPLL_CON1, + .pd_shift =3D 24, + + .pcw_reg =3D TVDPLL_CON1, + .pcw_chg_reg =3D TVDPLL_CON1, + .pcwbits =3D 21 + }, + { + .id =3D APLL1, + .name =3D "apll1", + .parent_name =3D "clk26m", + + .reg =3D APLL1_CON0, + .pwr_reg =3D APLL1_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D APLL1_CON0, + .pd_shift =3D 4, + + .pcw_reg =3D APLL1_CON1, + .pcw_chg_reg =3D APLL1_CON1, + .pcwbits =3D 31, + + .tuner_reg =3D APLL1_CON2, + .tuner_en_reg =3D AP_PLL_CON_5, + .tuner_en_bit =3D 0 + }, + { + .id =3D APLL2, + .name =3D "apll2", + .parent_name =3D "clk26m", + + .reg =3D APLL2_CON0, + .pwr_reg =3D APLL2_PWR_CON0, + .en_mask =3D 0x00000001, + + .pd_reg =3D APLL2_CON0, + .pd_shift =3D 4, + + .pcw_reg =3D APLL2_CON1, + .pcw_chg_reg =3D APLL2_CON1, + .pcwbits =3D 31, + + .tuner_reg =3D APLL1_CON2, + .tuner_en_reg =3D AP_PLL_CON_5, + .tuner_en_bit =3D 1 + } +}; + +int clk_mt6735_apmixed_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct resource *res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct clk_onecell_data *clk_data; + int ret; + + base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls)); + if (!clk_data) + return -ENOMEM; + platform_set_drvdata(pdev, clk_data); + + ret =3D mtk_clk_register_plls(pdev->dev.of_node, apmixed_plls, + ARRAY_SIZE(apmixed_plls), clk_data); + if (ret) { + dev_err(&pdev->dev, "Failed to register PLLs: %pe\n", + ERR_PTR(ret)); + return ret; + } + + ret =3D of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + clk_data); + if (ret) + dev_err(&pdev->dev, "Failed to register clock provider: %pe\n", + ERR_PTR(ret)); + + return ret; +} + +int clk_mt6735_apmixed_remove(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + mtk_clk_unregister_plls(apmixed_plls, ARRAY_SIZE(apmixed_plls), clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static const struct of_device_id of_match_mt6735_apmixedsys[] =3D { + { .compatible =3D "mediatek,mt6735-apmixedsys" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_apmixed =3D { + .probe =3D clk_mt6735_apmixed_probe, + .remove =3D clk_mt6735_apmixed_remove, + .driver =3D { + .name =3D "clk-mt6735-apmixed", + .of_match_table =3D of_match_mt6735_apmixedsys, + }, +}; +module_platform_driver(clk_mt6735_apmixed); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 apmixedsys clock driver"); +MODULE_LICENSE("GPL"); --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F00E9C4332F for ; Wed, 4 May 2022 12:33:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349714AbiEDMgi (ORCPT ); Wed, 4 May 2022 08:36:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349649AbiEDMge (ORCPT ); Wed, 4 May 2022 08:36:34 -0400 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [IPv6:2a00:1450:4864:20::535]) by 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:46 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 07/13] clk: mediatek: Add driver for MT6735 topckgen Date: Wed, 4 May 2022 16:25:56 +0400 Message-Id: <20220504122601.335495-8-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add a driver for MT6735 topckgen clocks. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 1 + drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-topckgen.c | 1159 ++++++++++++++++++++ 4 files changed, 1168 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-topckgen.c diff --git a/MAINTAINERS b/MAINTAINERS index 1077712edb4b..d9d6449f910e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12443,6 +12443,7 @@ L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixed.c +F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h F: include/dt-bindings/clock/mediatek,mt6735-pericfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index ab364892f602..7c19e2d7bb02 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -124,6 +124,13 @@ config COMMON_CLK_MT6735_APMIXED help This driver supports MediaTek MT6735 apmixedsys clocks. =20 +config COMMON_CLK_MT6735_TOPCKGEN + tristate "Clock driver for MediaTek MT6735 topckgen" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This driver supports MediaTek MT6735 topckgen clocks. + config COMMON_CLK_MT6765 bool "Clock driver for MediaTek MT6765" depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 7f45a22c6178..e8e892c4145f 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mtk.o clk-pll.o clk-gate.o clk-= apmixed.o clk-cpumux.o reset.o clk-mux.o =20 obj-$(CONFIG_COMMON_CLK_MT6735_APMIXED) +=3D clk-mt6735-apmixed.o +obj-$(CONFIG_COMMON_CLK_MT6735_TOPCKGEN) +=3D clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6765) +=3D clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) +=3D clk-mt6765-audio.o obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) +=3D clk-mt6765-cam.o diff --git a/drivers/clk/mediatek/clk-mt6735-topckgen.c b/drivers/clk/media= tek/clk-mt6735-topckgen.c new file mode 100644 index 000000000000..444c87aed71e --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-topckgen.c @@ -0,0 +1,1159 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-mtk.h" +#include "clk-mux.h" + +#include + +#define CLK_CFG_0 0x40 +#define CLK_CFG_0_SET 0x44 +#define CLK_CFG_0_CLR 0x48 +#define CLK_CFG_1 0x50 +#define CLK_CFG_1_SET 0x54 +#define CLK_CFG_1_CLR 0x58 +#define CLK_CFG_2 0x60 +#define CLK_CFG_2_SET 0x64 +#define CLK_CFG_2_CLR 0x68 +#define CLK_CFG_3 0x70 +#define CLK_CFG_3_SET 0x74 +#define CLK_CFG_3_CLR 0x78 +#define CLK_CFG_4 0x80 +#define CLK_CFG_4_SET 0x84 +#define CLK_CFG_4_CLR 0x88 +#define CLK_CFG_5 0x90 +#define CLK_CFG_5_SET 0x94 +#define CLK_CFG_5_CLR 0x98 +#define CLK_CFG_6 0xa0 +#define CLK_CFG_6_SET 0xa4 +#define CLK_CFG_6_CLR 0xa8 +#define CLK_CFG_7 0xb0 +#define CLK_CFG_7_SET 0xb4 +#define CLK_CFG_7_CLR 0xb8 + +static DEFINE_SPINLOCK(mt6735_topckgen_lock); + +/* Some clocks with unknown details are modeled as fixed clocks */ +static const struct mtk_fixed_clk top_fixed_clks[] =3D { + { + /* + * This clock is available as a parent option for multiple + * muxes and seems like an alternative name for clk26m at first, + * but it appears alongside it in several muxes which should + * mean it is a separate clock. + */ + .id =3D AD_SYS_26M_CK, + .name =3D "ad_sys_26m_ck", + .parent =3D "clk26m", + .rate =3D 26 * MHZ, + }, + { + /* + * This clock is the parent of DMPLL divisors. It might be MEMPLL + * or its parent, as DMPLL appears to be an alternative name for + * MEMPLL. + */ + .id =3D CLKPH_MCK_O, + .name =3D "clkph_mck_o", + .parent =3D NULL + }, + { + /* + * DMPLL clock (dmpll_ck), controlled by DDRPHY. + */ + .id =3D DMPLL, + .name =3D "dmpll", + .parent =3D "clkph_mck_o" + }, + { + /* + * MIPI DPI clock. Parent option for dpi0_sel. Unknown parent. + */ + .id =3D DPI_CK, + .name =3D "dpi_ck", + .parent =3D NULL + }, + { + /* + * This clock is a child of WHPLL which is controlled by + * the modem. + */ + .id =3D WHPLL_AUDIO_CK, + .name =3D "whpll_audio_ck", + .parent =3D NULL + }, +}; + +static const struct mtk_fixed_factor top_divs[] =3D { + { + .id =3D SYSPLL_D2, + .name =3D "syspll_d2", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D SYSPLL_D3, + .name =3D "syspll_d3", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 3 + }, + { + .id =3D SYSPLL_D5, + .name =3D "syspll_d5", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 5 + }, + { + .id =3D SYSPLL1_D2, + .name =3D "syspll1_d2", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D SYSPLL1_D4, + .name =3D "syspll1_d4", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D SYSPLL1_D8, + .name =3D "syspll1_d8", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 8 + }, + { + .id =3D SYSPLL1_D16, + .name =3D "syspll1_d16", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 16 + }, + { + .id =3D SYSPLL2_D2, + .name =3D "syspll2_d2", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D SYSPLL2_D4, + .name =3D "syspll2_d4", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D SYSPLL3_D2, + .name =3D "syspll3_d2", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D SYSPLL3_D4, + .name =3D "syspll3_d4", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D SYSPLL4_D2, + .name =3D "syspll4_d2", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D SYSPLL4_D4, + .name =3D "syspll4_d4", + .parent_name =3D "mainpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D UNIVPLL_D2, + .name =3D "univpll_d2", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D UNIVPLL_D3, + .name =3D "univpll_d3", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 3 + }, + { + .id =3D UNIVPLL_D5, + .name =3D "univpll_d5", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 5 + }, + { + .id =3D UNIVPLL_D26, + .name =3D "univpll_d26", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 26 + }, + { + .id =3D UNIVPLL1_D2, + .name =3D "univpll1_d2", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D UNIVPLL1_D4, + .name =3D "univpll1_d4", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D UNIVPLL1_D8, + .name =3D "univpll1_d8", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 8 + }, + { + .id =3D UNIVPLL2_D2, + .name =3D "univpll2_d2", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D UNIVPLL2_D4, + .name =3D "univpll2_d4", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D UNIVPLL2_D8, + .name =3D "univpll2_d8", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 8 + }, + { + .id =3D UNIVPLL3_D2, + .name =3D "univpll3_d2", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D UNIVPLL3_D4, + .name =3D "univpll3_d4", + .parent_name =3D "univpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D MSDCPLL_D2, + .name =3D "msdcpll_d2", + .parent_name =3D "msdcpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D MSDCPLL_D4, + .name =3D "msdcpll_d4", + .parent_name =3D "msdcpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D MSDCPLL_D8, + .name =3D "msdcpll_d8", + .parent_name =3D "msdcpll", + .mult =3D 1, + .div =3D 8 + }, + { + .id =3D MSDCPLL_D16, + .name =3D "msdcpll_d16", + .parent_name =3D "msdcpll", + .mult =3D 1, + .div =3D 16 + }, + { + .id =3D VENCPLL_D3, + .name =3D "vencpll_d3", + .parent_name =3D "vencpll", + .mult =3D 1, + .div =3D 3 + }, + { + .id =3D TVDPLL_D2, + .name =3D "tvdpll_d2", + .parent_name =3D "tvdpll", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D TVDPLL_D4, + .name =3D "tvdpll_d4", + .parent_name =3D "tvdpll", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D DMPLL_D2, + .name =3D "dmpll_d2", + .parent_name =3D "clkph_mck_o", + .mult =3D 1, + .div =3D 2 + }, + { + .id =3D DMPLL_D4, + .name =3D "dmpll_d4", + .parent_name =3D "clkph_mck_o", + .mult =3D 1, + .div =3D 4 + }, + { + .id =3D DMPLL_D8, + .name =3D "dmpll_d8", + .parent_name =3D "clkph_mck_o", + .mult =3D 1, + .div =3D 8 + }, + { + .id =3D AD_SYS_26M_D2, + .name =3D "ad_sys_26m_d2", + .parent_name =3D "clk26m", + .mult =3D 1, + .div =3D 2 + }, +}; + +static const char * const axi_sel_parents[] =3D { + "clk26m", + "syspll1_d2", + "syspll_d5", + "syspll1_d4", + "univpll_d5", + "univpll2_d2", + "dmpll", + "dmpll_d2" +}; + +static const char * const mem_sel_parents[] =3D { + "clk26m", + "dmpll" +}; + +static const char * const ddrphycfg_parents[] =3D { + "clk26m", + "syspll1_d8" +}; + +static const char * const mm_sel_parents[] =3D { + "clk26m", + "vencpll", + "syspll1_d2", + "syspll_d5", + "syspll1_d4", + "univpll_d5", + "univpll2_d2", + "dmpll" +}; + +static const char * const pwm_sel_parents[] =3D { + "clk26m", + "univpll2_d4", + "univpll3_d2", + "univpll1_d4" +}; + +static const char * const vdec_sel_parents[] =3D { + "clk26m", + "syspll1_d2", + "syspll_d5", + "syspll1_d4", + "univpll_d5", + "syspll_d2", + "syspll2_d2", + "msdcpll_d2" +}; + +static const char * const mfg_sel_parents[] =3D { + "clk26m", + "mmpll", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "clk26m", + "syspll_d3", + "syspll1_d2", + "syspll_d5", + "univpll_d3", + "univpll1_d2" +}; + +static const char * const camtg_sel_parents[] =3D { + "clk26m", + "univpll_d26", + "univpll2_d2", + "syspll3_d2", + "syspll3_d4", + "msdcpll_d4" +}; + +static const char * const uart_sel_parents[] =3D { + "clk26m", + "univpll2_d8" +}; + +static const char * const spi_sel_parents[] =3D { + "clk26m", + "syspll3_d2", + "msdcpll_d8", + "syspll2_d4", + "syspll4_d2", + "univpll2_d4", + "univpll1_d8" +}; + +static const char * const usb20_sel_parents[] =3D { + "clk26m", + "univpll1_d8", + "univpll3_d4" +}; + +static const char * const msdc50_0_sel_parents[] =3D { + "clk26m", + "syspll1_d2", + "syspll2_d2", + "syspll4_d2", + "univpll_d5", + "univpll1_d4" +}; + +static const char * const msdc30_0_sel_parents[] =3D { + "clk26m", + "msdcpll", + "msdcpll_d2", + "msdcpll_d4", + "syspll2_d2", + "syspll1_d4", + "univpll1_d4", + "univpll_d3", + "univpll_d26", + "syspll2_d4", + "univpll_d2" +}; + +static const char * const msdc30_1_2_sel_parents[] =3D { + "clk26m", + "univpll2_d2", + "msdcpll_d4", + "syspll2_d2", + "syspll1_d4", + "univpll1_d4", + "univpll_d26", + "syspll2_d4" +}; + +static const char * const msdc30_3_sel_parents[] =3D { + "clk26m", + "univpll2_d2", + "msdcpll_d4", + "syspll2_d2", + "syspll1_d4", + "univpll1_d4", + "univpll_d26", + "msdcpll_d16", + "syspll2_d4" +}; + +static const char * const audio_sel_parents[] =3D { + "clk26m", + "syspll3_d4", + "syspll4_d4", + "syspll1_d16" +}; + +static const char * const aud_intbus_sel_parents[] =3D { + "clk26m", + "syspll1_d4", + "syspll4_d2", + "dmpll_d4" +}; + +static const char * const pmicspi_sel_parents[] =3D { + "clk26m", + "syspll1_d8", + "syspll3_d4", + "syspll1_d16", + "univpll3_d4", + "univpll_d26", + "dmpll_d4", + "dmpll_d8" +}; + +static const char * const scp_sel_parents[] =3D { + "clk26m", + "syspll1_d8", + "dmpll_d2", + "dmpll_d4" +}; + +static const char * const atb_sel_parents[] =3D { + "clk26m", + "syspll1_d2", + "syspll_d5", + "dmpll" +}; + +static const char * const dpi0_sel_parents[] =3D { + "clk26m", + "tvdpll", + "tvdpll_d2", + "tvdpll_d4", + "dpi_ck" +}; + +static const char * const scam_sel_parents[] =3D { + "clk26m", + "syspll3_d2", + "univpll2_d4", + "vencpll_d3" +}; + +static const char * const mfg13m_sel_parents[] =3D { + "clk26m", + "ad_sys_26m_d2" +}; + +static const char * const aud_1_2_sel_parents[] =3D { + "clk26m", + "apll1" +}; + +static const char * const irda_sel_parents[] =3D { + "clk26m", + "univpll2_d4" +}; + +static const char * const irtx_sel_parents[] =3D { + "clk26m", + "ad_sys_26m_ck" +}; + +static const char * const disppwm_sel_parents[] =3D { + "clk26m", + "univpll2_d4", + "syspll4_d2_d8", + "ad_sys_26m_ck" +}; + +static const struct mtk_mux top_muxes[] =3D { + { + .id =3D AXI_SEL, + .name =3D "axi_sel", + .parent_names =3D axi_sel_parents, + .num_parents =3D ARRAY_SIZE(axi_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_0, + .set_ofs =3D CLK_CFG_0_SET, + .clr_ofs =3D CLK_CFG_0_CLR, + + .mux_shift =3D 0, + .mux_width =3D 3, + + .ops =3D &mtk_mux_clr_set_upd_ops, + }, + { + .id =3D MEM_SEL, + .name =3D "mem_sel", + .parent_names =3D mem_sel_parents, + .num_parents =3D ARRAY_SIZE(mem_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_0, + .set_ofs =3D CLK_CFG_0_SET, + .clr_ofs =3D CLK_CFG_0_CLR, + + .mux_shift =3D 8, + .mux_width =3D 1, + + .ops =3D &mtk_mux_clr_set_upd_ops, + }, + { + .id =3D DDRPHY_SEL, + .name =3D "ddrphycfg_sel", + .parent_names =3D ddrphycfg_parents, + .num_parents =3D ARRAY_SIZE(ddrphycfg_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_0, + .set_ofs =3D CLK_CFG_0_SET, + .clr_ofs =3D CLK_CFG_0_CLR, + + .mux_shift =3D 16, + .mux_width =3D 1, + + .ops =3D &mtk_mux_clr_set_upd_ops, + }, + { + .id =3D MM_SEL, + .name =3D "mm_sel", + .parent_names =3D mm_sel_parents, + .num_parents =3D ARRAY_SIZE(mm_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_0, + .set_ofs =3D CLK_CFG_0_SET, + .clr_ofs =3D CLK_CFG_0_CLR, + + .mux_shift =3D 24, + .mux_width =3D 3, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D PWM_SEL, + .name =3D "pwm_sel", + .parent_names =3D pwm_sel_parents, + .num_parents =3D ARRAY_SIZE(pwm_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_1, + .set_ofs =3D CLK_CFG_1_SET, + .clr_ofs =3D CLK_CFG_1_CLR, + + .mux_shift =3D 0, + .mux_width =3D 2, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D VDEC_SEL, + .name =3D "vdec_sel", + .parent_names =3D vdec_sel_parents, + .num_parents =3D ARRAY_SIZE(vdec_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_1, + .set_ofs =3D CLK_CFG_1_SET, + .clr_ofs =3D CLK_CFG_1_CLR, + + .mux_shift =3D 8, + .mux_width =3D 3, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MFG_SEL, + .name =3D "mfg_sel", + .parent_names =3D mfg_sel_parents, + .num_parents =3D ARRAY_SIZE(mfg_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_1, + .set_ofs =3D CLK_CFG_1_SET, + .clr_ofs =3D CLK_CFG_1_CLR, + + .mux_shift =3D 16, + .mux_width =3D 4, + .gate_shift =3D 23, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D CAMTG_SEL, + .name =3D "camtg_sel", + .parent_names =3D camtg_sel_parents, + .num_parents =3D ARRAY_SIZE(camtg_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_1, + .set_ofs =3D CLK_CFG_1_SET, + .clr_ofs =3D CLK_CFG_1_CLR, + + .mux_shift =3D 24, + .mux_width =3D 3, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D UART_SEL, + .name =3D "uart_sel", + .parent_names =3D uart_sel_parents, + .num_parents =3D ARRAY_SIZE(uart_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_2, + .set_ofs =3D CLK_CFG_2_SET, + .clr_ofs =3D CLK_CFG_2_CLR, + + .mux_shift =3D 0, + .mux_width =3D 1, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D SPI_SEL, + .name =3D "spi_sel", + .parent_names =3D spi_sel_parents, + .num_parents =3D ARRAY_SIZE(spi_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_2, + .set_ofs =3D CLK_CFG_2_SET, + .clr_ofs =3D CLK_CFG_2_CLR, + + .mux_shift =3D 8, + .mux_width =3D 3, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D USB20_SEL, + .name =3D "usb20_sel", + .parent_names =3D usb20_sel_parents, + .num_parents =3D ARRAY_SIZE(usb20_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_2, + .set_ofs =3D CLK_CFG_2_SET, + .clr_ofs =3D CLK_CFG_2_CLR, + + .mux_shift =3D 16, + .mux_width =3D 2, + .gate_shift =3D 23, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MSDC50_0_SEL, + .name =3D "msdc50_0_sel", + .parent_names =3D msdc50_0_sel_parents, + .num_parents =3D ARRAY_SIZE(msdc50_0_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_2, + .set_ofs =3D CLK_CFG_2_SET, + .clr_ofs =3D CLK_CFG_2_CLR, + + .mux_shift =3D 24, + .mux_width =3D 3, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MSDC30_0_SEL, + .name =3D "msdc30_0_sel", + .parent_names =3D msdc30_0_sel_parents, + .num_parents =3D ARRAY_SIZE(msdc30_0_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_3, + .set_ofs =3D CLK_CFG_3_SET, + .clr_ofs =3D CLK_CFG_3_CLR, + + .mux_shift =3D 0, + .mux_width =3D 4, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MSDC30_1_SEL, + .name =3D "msdc30_1_sel", + .parent_names =3D msdc30_1_2_sel_parents, + .num_parents =3D ARRAY_SIZE(msdc30_1_2_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_3, + .set_ofs =3D CLK_CFG_3_SET, + .clr_ofs =3D CLK_CFG_3_CLR, + + .mux_shift =3D 8, + .mux_width =3D 3, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MSDC30_2_SEL, + .name =3D "msdc30_2_sel", + .parent_names =3D msdc30_1_2_sel_parents, + .num_parents =3D ARRAY_SIZE(msdc30_1_2_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_3, + .set_ofs =3D CLK_CFG_3_SET, + .clr_ofs =3D CLK_CFG_3_CLR, + + .mux_shift =3D 16, + .mux_width =3D 3, + .gate_shift =3D 23, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MSDC30_3_SEL, + .name =3D "msdc30_3_sel", + .parent_names =3D msdc30_3_sel_parents, + .num_parents =3D ARRAY_SIZE(msdc30_3_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_3, + .set_ofs =3D CLK_CFG_3_SET, + .clr_ofs =3D CLK_CFG_3_CLR, + + .mux_shift =3D 24, + .mux_width =3D 4, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D AUDIO_SEL, + .name =3D "audio_sel", + .parent_names =3D audio_sel_parents, + .num_parents =3D ARRAY_SIZE(audio_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_4, + .set_ofs =3D CLK_CFG_4_SET, + .clr_ofs =3D CLK_CFG_4_CLR, + + .mux_shift =3D 0, + .mux_width =3D 2, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D AUDINTBUS_SEL, + .name =3D "aud_intbus_sel", + .parent_names =3D aud_intbus_sel_parents, + .num_parents =3D ARRAY_SIZE(aud_intbus_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_4, + .set_ofs =3D CLK_CFG_4_SET, + .clr_ofs =3D CLK_CFG_4_CLR, + + .mux_shift =3D 8, + .mux_width =3D 2, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D PMICSPI_SEL, + .name =3D "pmicspi_sel", + .parent_names =3D pmicspi_sel_parents, + .num_parents =3D ARRAY_SIZE(pmicspi_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_4, + .set_ofs =3D CLK_CFG_4_SET, + .clr_ofs =3D CLK_CFG_4_CLR, + + .mux_shift =3D 16, + .mux_width =3D 3, + + .ops =3D &mtk_mux_clr_set_upd_ops, + }, + { + .id =3D SCP_SEL, + .name =3D "scp_sel", + .parent_names =3D scp_sel_parents, + .num_parents =3D ARRAY_SIZE(scp_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_4, + .set_ofs =3D CLK_CFG_4_SET, + .clr_ofs =3D CLK_CFG_4_CLR, + + .mux_shift =3D 24, + .mux_width =3D 2, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D ATB_SEL, + .name =3D "atb_sel", + .parent_names =3D atb_sel_parents, + .num_parents =3D ARRAY_SIZE(atb_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_5, + .set_ofs =3D CLK_CFG_5_SET, + .clr_ofs =3D CLK_CFG_5_CLR, + + .mux_shift =3D 0, + .mux_width =3D 2, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D DPI0_SEL, + .name =3D "dpi0_sel", + .parent_names =3D dpi0_sel_parents, + .num_parents =3D ARRAY_SIZE(dpi0_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_5, + .set_ofs =3D CLK_CFG_5_SET, + .clr_ofs =3D CLK_CFG_5_CLR, + + .mux_shift =3D 8, + .mux_width =3D 3, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D SCAM_SEL, + .name =3D "scam_sel", + .parent_names =3D scam_sel_parents, + .num_parents =3D ARRAY_SIZE(scam_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_5, + .set_ofs =3D CLK_CFG_5_SET, + .clr_ofs =3D CLK_CFG_5_CLR, + + .mux_shift =3D 16, + .mux_width =3D 2, + .gate_shift =3D 23, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D MFG13M_SEL, + .name =3D "mfg13m_sel", + .parent_names =3D mfg13m_sel_parents, + .num_parents =3D ARRAY_SIZE(mfg13m_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_5, + .set_ofs =3D CLK_CFG_5_SET, + .clr_ofs =3D CLK_CFG_5_CLR, + + .mux_shift =3D 24, + .mux_width =3D 1, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D AUD1_SEL, + .name =3D "aud_1_sel", + .parent_names =3D aud_1_2_sel_parents, + .num_parents =3D ARRAY_SIZE(aud_1_2_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_6, + .set_ofs =3D CLK_CFG_6_SET, + .clr_ofs =3D CLK_CFG_6_CLR, + + .mux_shift =3D 0, + .mux_width =3D 1, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D AUD2_SEL, + .name =3D "aud_2_sel", + .parent_names =3D aud_1_2_sel_parents, + .num_parents =3D ARRAY_SIZE(aud_1_2_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_6, + .set_ofs =3D CLK_CFG_6_SET, + .clr_ofs =3D CLK_CFG_6_CLR, + + .mux_shift =3D 8, + .mux_width =3D 1, + .gate_shift =3D 15, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D IRDA_SEL, + .name =3D "irda_sel", + .parent_names =3D irda_sel_parents, + .num_parents =3D ARRAY_SIZE(irda_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_6, + .set_ofs =3D CLK_CFG_6_SET, + .clr_ofs =3D CLK_CFG_6_CLR, + + .mux_shift =3D 16, + .mux_width =3D 1, + .gate_shift =3D 23, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D IRTX_SEL, + .name =3D "irtx_sel", + .parent_names =3D irtx_sel_parents, + .num_parents =3D ARRAY_SIZE(irtx_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_6, + .set_ofs =3D CLK_CFG_6_SET, + .clr_ofs =3D CLK_CFG_6_CLR, + + .mux_shift =3D 24, + .mux_width =3D 1, + .gate_shift =3D 31, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, + { + .id =3D DISPPWM_SEL, + .name =3D "disppwm_sel", + .parent_names =3D disppwm_sel_parents, + .num_parents =3D ARRAY_SIZE(disppwm_sel_parents), + .flags =3D CLK_SET_RATE_PARENT, + + .mux_ofs =3D CLK_CFG_7, + .set_ofs =3D CLK_CFG_7_SET, + .clr_ofs =3D CLK_CFG_7_CLR, + + .mux_shift =3D 0, + .mux_width =3D 2, + .gate_shift =3D 7, + + .ops =3D &mtk_mux_gate_clr_set_upd_ops, + }, +}; + +int clk_mt6735_topckgen_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct resource *res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct clk_onecell_data *clk_data; + int ret; + + base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(top_fixed_clks) + + ARRAY_SIZE(top_divs) + + ARRAY_SIZE(top_muxes)); + if (!clk_data) + return -ENOMEM; + platform_set_drvdata(pdev, clk_data); + + ret =3D mtk_clk_register_fixed_clks(top_fixed_clks, + ARRAY_SIZE(top_fixed_clks), clk_data); + if (ret) { + dev_err(&pdev->dev, "Failed to register fixed clocks: %pe\n", + ERR_PTR(ret)); + goto free_clk_data; + } + + ret =3D mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data= ); + if (ret) { + dev_err(&pdev->dev, "Failed to register dividers: %pe\n", + ERR_PTR(ret)); + goto unregister_fixed_clks; + } + + ret =3D mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), + pdev->dev.of_node, &mt6735_topckgen_lock, + clk_data); + if (ret) { + dev_err(&pdev->dev, "Failed to register muxes: %pe\n", + ERR_PTR(ret)); + goto unregister_factors; + } + + ret =3D of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + clk_data); + if (ret) { + dev_err(&pdev->dev, + "Failed to register clock provider: %pe\n", + ERR_PTR(ret)); + goto unregister_muxes; + } + + return 0; +unregister_muxes: + mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data); +unregister_factors: + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); +unregister_fixed_clks: + mtk_clk_unregister_fixed_clks(top_fixed_clks, + ARRAY_SIZE(top_fixed_clks), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + + return ret; +} + +int clk_mt6735_topckgen_remove(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data =3D platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + mtk_clk_unregister_muxes(top_muxes, ARRAY_SIZE(top_muxes), clk_data); + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), + clk_data); + mtk_free_clk_data(clk_data); + + return 0; +} + +static const struct of_device_id of_match_mt6735_topckgen[] =3D { + { .compatible =3D "mediatek,mt6735-topckgen" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_topckgen =3D { + .probe =3D clk_mt6735_topckgen_probe, + .remove =3D clk_mt6735_topckgen_remove, + .driver =3D { + .name =3D "clk-mt6735-topckgen", + .of_match_table =3D of_match_mt6735_topckgen, + }, +}; +module_platform_driver(clk_mt6735_topckgen); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 topckgen clock driver"); +MODULE_LICENSE("GPL"); --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:52 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 08/13] clk: mediatek: gate: Export mtk_clk_register_gates_with_dev Date: Wed, 4 May 2022 16:25:57 +0400 Message-Id: <20220504122601.335495-9-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana This allows it to be used in drivers built as modules. Signed-off-by: Yassine Oudjana --- drivers/clk/mediatek/clk-gate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gat= e.c index da52023f8455..8af907b82f8f 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -261,6 +261,7 @@ int mtk_clk_register_gates_with_dev(struct device_node = *node, =20 return PTR_ERR(clk); } +EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev); =20 int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks, int num, --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89404C433EF for ; Wed, 4 May 2022 12:33:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349739AbiEDMgw (ORCPT ); Wed, 4 May 2022 08:36:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349617AbiEDMgh (ORCPT ); Wed, 4 May 2022 08:36:37 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8BE9933A28; Wed, 4 May 2022 05:32:59 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id be20so1503288edb.12; Wed, 04 May 2022 05:32:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aPFSi/mWYMYdcINHgbvPpjSUWnzyR9p2rv5umtn3cjI=; b=UEFVed+rgiC1aLFETWO3cJXmKIhCocpF3HO/nI8utDBVg39ruLl5QFVsv4iuKvsveR 5qATWQ8FXfIGg/WmYfD4hppEDR+bjU9R2cpZK2b80cZj7hMm+DyQg4GkyCqvOrn9a6Hn Jf33IeqUyVSd18068d9DNkH5Ci1mOYNBziuQ4Kaaevxnfjp8ORdU3Y25YF4pBNcjVqPh K8jQg1FaR/BuZ27aXWahyAQCbLO6jopxmHRzaaxQPMilhwrwlBSIB0tsiMLKv1NQ4Njf ekXwbKBISFCg5eZx9ktY6Ge82DA4gMnJYoZ6k/x/ApvaQftQjfV5cP8tDj0Y4xVYp4Jy sDnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aPFSi/mWYMYdcINHgbvPpjSUWnzyR9p2rv5umtn3cjI=; b=RwFR3sACu6AVUrRD8IMeDnpXg7G1KwQ3SX1FkB/pPhrH/uMPSzS1+JygdaSrOMnnXa KlRweMn9xyHjvLMsnxJjLDDazRpjuYA2jMxjMyPdpvVl9pz6AgUg/eDykDWGjvPmBT/p oK9LodtlATLu2Dpa9/nWeqLrIuOxC82CcFXR8N9BCW4WuAnlGzUeh6itfg/03bN5/yLN /agJz1CsOoCQkvfAmzQQZ0KlboPo44fQ82oDnErNF47MyBzE5SE/Bd8IZpxJRg3hkIIE u/XDArccnWwzRj1tWlf8TocObtkoa0wsEHZOt4QrvKX+orkelTbInMr5f/yEJpr3OaG2 mcCA== X-Gm-Message-State: AOAM530Pe6hJQXLLmSGPbEcdh7xQ336Vl8kVd5fsJnSJY9rppgxY8xpW Mu4d148L4/UAy1wOdXacX9M= X-Google-Smtp-Source: ABdhPJw1ji77MznXPOLUih012rHNfyRY1v0DSI/u5kQreEXOVa6/qDVm+wA0fswuDakV4xVmX1s1FA== X-Received: by 2002:aa7:c318:0:b0:426:4aae:de6d with SMTP id l24-20020aa7c318000000b004264aaede6dmr22660856edq.208.1651667578090; Wed, 04 May 2022 05:32:58 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:32:57 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols Date: Wed, 4 May 2022 16:25:58 +0400 Message-Id: <20220504122601.335495-10-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Export mtk_register_reset_controller and mtk_register_reset_controller_set_clr to support building reset drivers as modules. Signed-off-by: Yassine Oudjana --- drivers/clk/mediatek/reset.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index bcec4b89f449..6c2effe6afef 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -129,6 +129,7 @@ void mtk_register_reset_controller(struct device_node *= np, mtk_register_reset_controller_common(np, num_regs, regofs, &mtk_reset_ops); } +EXPORT_SYMBOL_GPL(mtk_register_reset_controller); =20 void mtk_register_reset_controller_set_clr(struct device_node *np, unsigned int num_regs, int regofs) @@ -136,5 +137,6 @@ void mtk_register_reset_controller_set_clr(struct devic= e_node *np, mtk_register_reset_controller_common(np, num_regs, regofs, &mtk_reset_ops_set_clr); } +EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr); =20 MODULE_LICENSE("GPL"); --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15620C433F5 for ; Wed, 4 May 2022 12:33:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349737AbiEDMhB (ORCPT ); Wed, 4 May 2022 08:37:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349678AbiEDMgl (ORCPT ); Wed, 4 May 2022 08:36:41 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A38A326E2; Wed, 4 May 2022 05:33:05 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id l18so2584950ejc.7; Wed, 04 May 2022 05:33:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c4IPakMiBG8qMu0eZo70xqgp2PUHni7/ktt8LMUY1Go=; b=m2F3pyQcK4IPVHZeQQykxgWkJZ1MtrhVtyc+P5bf0ZH9Jgjrd9slbkr6T10zzXsT+O SKHQFHHdY5qa4+N6+extiji2ToJUpU1QA7nhtiokTSthTdyYP9uF5yhEBM0crd8gZ+dm rT/ivTV8NWMtSG8uX/h7nhs7t5a3n3Ocz+G+nyiJl350Oxj7dTJgCkCqKmvRnn3E2fR8 tzepYb9AVE4tY1GqMS9N3OXMIeHUJkUVJRwihnqxrpyP9eI4Vw2JoS6zCxZik3rzoOtG 8X7VyjxXcZxIDjOIiqt69uuL8B3dcep7tExY6hoe+MUvVqvC1Dniu2r8BN23G9TUleMQ 0mUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c4IPakMiBG8qMu0eZo70xqgp2PUHni7/ktt8LMUY1Go=; b=KEcLiFryISsinVwZpclHSXdQDz2utN1SpDpogTWpjUE4KFybeQudC4TMspEO2FvPFK ZdiYhFDu6cCnvtUBuRgvE7RSZHXXFkpEIZdBBp8jRZH7iZM/cW/9qa11DiTvJnIjuEGD xEB/dl95RLrq+OEVL7pHQQUMpdPpIqQT65czbKqVGYfmFauiuLnowyZ5eHuXzGZrYz7l 9Dhe280y/ykZlOdS8oJbaS9Ln5s10abvi+NLKDCCOGjMdImi4bUnNj7wzokrLTLPY10J LpiImKhZm++3H+0tHcNRytUMRMfjSENa+wnIuVgirdct2NRF+lB3tbU7UHHx1mqPXQT+ VbgQ== X-Gm-Message-State: AOAM531ErurJ/TbYGHcUZZhqF3YBxHuqJF+hCVIUGHxDl30V0SNhuud5 Hxh7V107OHUld7QA6OkAarR5e2uYEjc= X-Google-Smtp-Source: ABdhPJzjBn9KrdvJXPPoHERPbtQfki+JAaYMq/RQlJZ15Om95MsCxhMPcv/ncYAS2F1IyQC4vW+3dQ== X-Received: by 2002:a17:906:a2c2:b0:6e7:efc2:17f2 with SMTP id by2-20020a170906a2c200b006e7efc217f2mr19194685ejb.542.1651667583997; Wed, 04 May 2022 05:33:03 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:33:03 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 10/13] clk: mediatek: reset: Return mtk_reset pointer on register Date: Wed, 4 May 2022 16:25:59 +0400 Message-Id: <20220504122601.335495-11-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Return a struct mtk_reset* when registering a reset controller in preparation for adding an unregister helper that will take it as an argument. Signed-off-by: Yassine Oudjana --- drivers/clk/mediatek/clk-mtk.h | 6 +++--- drivers/clk/mediatek/reset.c | 22 ++++++++++++---------- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index bf6565aa7319..317905ec4a36 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -190,10 +190,10 @@ void mtk_free_clk_data(struct clk_onecell_data *clk_d= ata); struct clk *mtk_clk_register_ref2usb_tx(const char *name, const char *parent_name, void __iomem *reg); =20 -void mtk_register_reset_controller(struct device_node *np, - unsigned int num_regs, int regofs); +struct mtk_reset *mtk_register_reset_controller(struct device_node *np, + unsigned int num_regs, int regofs); =20 -void mtk_register_reset_controller_set_clr(struct device_node *np, +struct mtk_reset *mtk_register_reset_controller_set_clr(struct device_node= *np, unsigned int num_regs, int regofs); =20 struct mtk_clk_desc { diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index 6c2effe6afef..f853bc8a7092 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -90,9 +90,9 @@ static const struct reset_control_ops mtk_reset_ops_set_c= lr =3D { .reset =3D mtk_reset_set_clr, }; =20 -static void mtk_register_reset_controller_common(struct device_node *np, - unsigned int num_regs, int regofs, - const struct reset_control_ops *reset_ops) +static struct mtk_reset *mtk_register_reset_controller_common( + struct device_node *np, unsigned int num_regs, int regofs, + const struct reset_control_ops *reset_ops) { struct mtk_reset *data; int ret; @@ -101,12 +101,12 @@ static void mtk_register_reset_controller_common(stru= ct device_node *np, regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) { pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap); - return; + return (struct mtk_reset *)regmap; } =20 data =3D kzalloc(sizeof(*data), GFP_KERNEL); if (!data) - return; + return ERR_PTR(-ENOMEM); =20 data->regmap =3D regmap; data->regofs =3D regofs; @@ -119,22 +119,24 @@ static void mtk_register_reset_controller_common(stru= ct device_node *np, if (ret) { pr_err("could not register reset controller: %d\n", ret); kfree(data); - return; + return ERR_PTR(ret); } + + return data; } =20 -void mtk_register_reset_controller(struct device_node *np, +struct mtk_reset *mtk_register_reset_controller(struct device_node *np, unsigned int num_regs, int regofs) { - mtk_register_reset_controller_common(np, num_regs, regofs, + return mtk_register_reset_controller_common(np, num_regs, regofs, &mtk_reset_ops); } EXPORT_SYMBOL_GPL(mtk_register_reset_controller); =20 -void mtk_register_reset_controller_set_clr(struct device_node *np, +struct mtk_reset *mtk_register_reset_controller_set_clr(struct device_node= *np, unsigned int num_regs, int regofs) { - mtk_register_reset_controller_common(np, num_regs, regofs, + return mtk_register_reset_controller_common(np, num_regs, regofs, &mtk_reset_ops_set_clr); } EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr); --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7606DC433F5 for ; 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.33.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:33:09 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 11/13] clk: mediatek: reset: Implement mtk_unregister_reset_controller() API Date: Wed, 4 May 2022 16:26:00 +0400 Message-Id: <20220504122601.335495-12-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add a function to unregister a reset controller previously registered with mtk_register_reset_controller() or mtk_register_reset_controller_set_clr(), and do the necessary cleanup. Signed-off-by: Yassine Oudjana --- drivers/clk/mediatek/clk-mtk.h | 2 ++ drivers/clk/mediatek/reset.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 317905ec4a36..1a0462d9c20b 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -196,6 +196,8 @@ struct mtk_reset *mtk_register_reset_controller(struct = device_node *np, struct mtk_reset *mtk_register_reset_controller_set_clr(struct device_node= *np, unsigned int num_regs, int regofs); =20 +void mtk_unregister_reset_controller(struct mtk_reset *data); + struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c index f853bc8a7092..7201e1f5e07b 100644 --- a/drivers/clk/mediatek/reset.c +++ b/drivers/clk/mediatek/reset.c @@ -141,4 +141,11 @@ struct mtk_reset *mtk_register_reset_controller_set_cl= r(struct device_node *np, } EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr); =20 +void mtk_unregister_reset_controller(struct mtk_reset *data) +{ + reset_controller_unregister(&data->rcdev); + kfree(data); +} +EXPORT_SYMBOL_GPL(mtk_unregister_reset_controller); + MODULE_LICENSE("GPL"); --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84EB1C433F5 for ; Wed, 4 May 2022 12:34:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349831AbiEDMhS (ORCPT ); Wed, 4 May 2022 08:37:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349769AbiEDMg6 (ORCPT ); Wed, 4 May 2022 08:36:58 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43019377E4; Wed, 4 May 2022 05:33:16 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id n10so2591987ejk.5; Wed, 04 May 2022 05:33:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oBISr3CZQqGcdCjvRVbXiYWtS6ToMPWn6L1o4go4QLA=; b=qlFSPsKMg6Pg+xqGsaVWBtz6kLGClPntmdrQKCtiGYn2Km5rzLw4vdnHmpYJRQR0TA WS08ngbPf7TK4NjqvvQMTuhFV4nf0h4hA62VAPjCr/X6AOZvJUHm+3kqLupaMeWLjBaZ Msy0yQKk71fxUe4P4AqKq2dLNKcrdqwsdheslTTMlu4zO6I58fzeLN48WVDYebdFnPq6 KxgfsRpxilMj76St4qilt1ELN5kQkGuz2YaRHQSYEIKYckG4ZTSEDiHUWOclljJLRubS Etyg1Qw3GKloCRllmkflWQR7YGNoTl2QI1oaMvMS6/L6MYzvZQXMSr+B+KdBewwYdxRF f9Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oBISr3CZQqGcdCjvRVbXiYWtS6ToMPWn6L1o4go4QLA=; b=Te3QV5kEx3Ut/7hVol/1nC0Va813TVYRoXx/vR2YB80EXDB8X1g8S4EtKqNT/TFbja RyD3R8A1S7h6xGCvSic2Sl9XlYDcUCc/6nb8eyxHrWjhp5VNomJVaNPu3Gm874anzEJD 66LsidLuLNel3OXZw1eh7qNVNyX7mD/LRDPCpBkjEzVJYLRq2v/xQ7tS8lT/o/V3nAH8 Hygne3j+Xd0fr9iIv34WigM4ZrtEoQxJVaCBK/pcxaz6v1JR+R8I1ZUZCGVZVEO8vDgS VA0BRdZGiBg16uveNXmX585lGhyxMHlxZh54JWHeU7I0wsli3fDlESq088Ke//L6E4v/ +wpQ== X-Gm-Message-State: AOAM532a+DB1UEKnvHxwLve4i8+PNj+1UkdiMIpqJrcKdDpgguOFVOlG oJ2kxmHyi+7CSkOHn7krFYk= X-Google-Smtp-Source: ABdhPJzhH9mftAskdv28qpFFDeFdarqLbrsYcwEXevajGrJy6gxGdaY2Bd/IhcfZUhKdyHrgYAmLBA== X-Received: by 2002:a17:907:9958:b0:6e7:f67a:a1e7 with SMTP id kl24-20020a170907995800b006e7f67aa1e7mr19398668ejc.400.1651667595412; Wed, 04 May 2022 05:33:15 -0700 (PDT) Received: from localhost.localdomain (185-177-124-12.hosted-by-worldstream.net. [185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:33:15 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/13] clk: mediatek: Add driver for MT6735 infracfg Date: Wed, 4 May 2022 16:26:01 +0400 Message-Id: <20220504122601.335495-13-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add a driver for MT6735 infracfg clock gates and resets. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 1 + drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-infracfg.c | 265 +++++++++++++++++++++ 4 files changed, 274 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-infracfg.c diff --git a/MAINTAINERS b/MAINTAINERS index d9d6449f910e..8662f12f34a2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12443,6 +12443,7 @@ L: linux-clk@vger.kernel.org L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixed.c +F: drivers/clk/mediatek/clk-mt6735-infracfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 7c19e2d7bb02..62195e5d90a0 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -124,6 +124,13 @@ config COMMON_CLK_MT6735_APMIXED help This driver supports MediaTek MT6735 apmixedsys clocks. =20 +config COMMON_CLK_MT6735_INFRACFG + tristate "Clock driver for MediaTek MT6735 infracfg" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This driver supports MediaTek MT6735 infracfg clocks and resets. + config COMMON_CLK_MT6735_TOPCKGEN tristate "Clock driver for MediaTek MT6735 topckgen" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e8e892c4145f..e5c1da6e2711 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mtk.o clk-pll.o clk-gate.o clk-= apmixed.o clk-cpumux.o reset.o clk-mux.o =20 obj-$(CONFIG_COMMON_CLK_MT6735_APMIXED) +=3D clk-mt6735-apmixed.o +obj-$(CONFIG_COMMON_CLK_MT6735_INFRACFG) +=3D clk-mt6735-infracfg.o obj-$(CONFIG_COMMON_CLK_MT6735_TOPCKGEN) +=3D clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6765) +=3D clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) +=3D clk-mt6765-audio.o diff --git a/drivers/clk/mediatek/clk-mt6735-infracfg.c b/drivers/clk/media= tek/clk-mt6735-infracfg.c new file mode 100644 index 000000000000..ce1a5739b3b2 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-infracfg.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define INFRA_RST0 0x30 +#define INFRA_GLOBALCON_PDN0 0x40 +#define INFRA_PDN1 0x44 +#define INFRA_PDN_STA 0x48 + +struct mt6735_infracfg { + struct clk_onecell_data *clk_data; + struct mtk_reset *reset_data; +}; + +static struct mtk_gate_regs infra_cg_regs =3D { + .set_ofs =3D INFRA_GLOBALCON_PDN0, + .clr_ofs =3D INFRA_PDN1, + .sta_ofs =3D INFRA_PDN_STA, +}; + +static const struct mtk_gate infracfg_gates[] =3D { + { + .id =3D DBGCLK, + .name =3D "dbgclk", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 0, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D GCE, + .name =3D "gce", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 1, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D TRBG, + .name =3D "trbg", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 2, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CPUM, + .name =3D "cpum", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 3, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D DEVAPC, + .name =3D "devapc", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 4, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D AUDIO, + .name =3D "audio", + .parent_name =3D "aud_intbus_sel", + .regs =3D &infra_cg_regs, + .shift =3D 5, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D GCPU, + .name =3D "gcpu", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 6, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D L2C_SRAM, + .name =3D "l2csram", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 7, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D M4U, + .name =3D "m4u", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 8, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CLDMA, + .name =3D "cldma", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 12, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CONNMCU_BUS, + .name =3D "connmcu_bus", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 15, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D KP, + .name =3D "kp", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 16, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D APXGPT, + .name =3D "apxgpt", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 18, + .ops =3D &mtk_clk_gate_ops_setclr, + .flags =3D CLK_IS_CRITICAL + }, + { + .id =3D SEJ, + .name =3D "sej", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 19, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CCIF0_AP, + .name =3D "ccif0ap", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 20, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D CCIF1_AP, + .name =3D "ccif1ap", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 21, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PMIC_SPI, + .name =3D "pmicspi", + .parent_name =3D "pmicspi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 22, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PMIC_WRAP, + .name =3D "pmicwrap", + .parent_name =3D "axi_sel", + .regs =3D &infra_cg_regs, + .shift =3D 23, + .ops =3D &mtk_clk_gate_ops_setclr + }, +}; + +int clk_mt6735_infracfg_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct resource *res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct mt6735_infracfg *infracfg; + int ret; + + base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + infracfg =3D devm_kmalloc(&pdev->dev, sizeof(struct mt6735_infracfg), + GFP_KERNEL); + if (!infracfg) + return -ENOMEM; + + infracfg->clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(infracfg_gates)); + if (!infracfg->clk_data) + return -ENOMEM; + platform_set_drvdata(pdev, infracfg); + + ret =3D mtk_clk_register_gates_with_dev(pdev->dev.of_node, infracfg_gates, + ARRAY_SIZE(infracfg_gates), + infracfg->clk_data, &pdev->dev); + if (ret) { + dev_err(&pdev->dev, "Failed to register gates: %pe\n", + ERR_PTR(ret)); + goto free_clk_data; + } + + ret =3D of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + infracfg->clk_data); + if (ret) { + dev_err(&pdev->dev, "Failed to register clock provider: %pe\n", + ERR_PTR(ret)); + goto unregister_gates; + } + + infracfg->reset_data =3D mtk_register_reset_controller(pdev->dev.of_node, + 1, INFRA_RST0); + if (IS_ERR(infracfg->reset_data)) { + dev_err(&pdev->dev, "Failed to register reset controller: %pe\n", + infracfg->reset_data); + return PTR_ERR(infracfg->reset_data); + } + + return 0; + +unregister_gates: + mtk_clk_unregister_gates(infracfg_gates, ARRAY_SIZE(infracfg_gates), + infracfg->clk_data); +free_clk_data: + mtk_free_clk_data(infracfg->clk_data); + + return ret; +} + +int clk_mt6735_infracfg_remove(struct platform_device *pdev) +{ + struct mt6735_infracfg *infracfg =3D platform_get_drvdata(pdev); + + mtk_unregister_reset_controller(infracfg->reset_data); + of_clk_del_provider(pdev->dev.of_node); + mtk_clk_unregister_gates(infracfg_gates, ARRAY_SIZE(infracfg_gates), + infracfg->clk_data); + mtk_free_clk_data(infracfg->clk_data); + + return 0; +} + +static const struct of_device_id of_match_mt6735_infracfg[] =3D { + { .compatible =3D "mediatek,mt6735-infracfg" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_infracfg =3D { + .probe =3D clk_mt6735_infracfg_probe, + .remove =3D clk_mt6735_infracfg_remove, + .driver =3D { + .name =3D "clk-mt6735-infracfg", + .of_match_table =3D of_match_mt6735_infracfg, + }, +}; +module_platform_driver(clk_mt6735_infracfg); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 infracfg clock and reset driver"); +MODULE_LICENSE("GPL"); --=20 2.36.0 From nobody Sun Sep 22 01:59:48 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA84CC433EF for ; Wed, 4 May 2022 12:33:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349806AbiEDMh3 (ORCPT ); Wed, 4 May 2022 08:37:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349627AbiEDMhB (ORCPT ); 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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id ig1-20020a1709072e0100b006f3ef214e7asm5688693ejc.224.2022.05.04.05.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:33:23 -0700 (PDT) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski Cc: Yassine Oudjana , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 13/13] clk: mediatek: Add driver for MT6735 pericfg Date: Wed, 4 May 2022 16:26:02 +0400 Message-Id: <20220504122601.335495-14-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220504122601.335495-1-y.oudjana@protonmail.com> References: <20220504122601.335495-1-y.oudjana@protonmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yassine Oudjana Add a driver for MT6735 pericfg clock gates and resets. Signed-off-by: Yassine Oudjana --- MAINTAINERS | 1 + drivers/clk/mediatek/Kconfig | 7 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt6735-pericfg.c | 360 ++++++++++++++++++++++ 4 files changed, 369 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt6735-pericfg.c diff --git a/MAINTAINERS b/MAINTAINERS index 8662f12f34a2..5d90c2f2a587 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12444,6 +12444,7 @@ L: linux-mediatek@lists.infradead.org (moderated fo= r non-subscribers) S: Maintained F: drivers/clk/mediatek/clk-mt6735-apmixed.c F: drivers/clk/mediatek/clk-mt6735-infracfg.c +F: drivers/clk/mediatek/clk-mt6735-pericfg.c F: drivers/clk/mediatek/clk-mt6735-topckgen.c F: include/dt-bindings/clock/mediatek,mt6735-apmixedsys.h F: include/dt-bindings/clock/mediatek,mt6735-infracfg.h diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 62195e5d90a0..698ff2995460 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -131,6 +131,13 @@ config COMMON_CLK_MT6735_INFRACFG help This driver supports MediaTek MT6735 infracfg clocks and resets. =20 +config COMMON_CLK_MT6735_PERICFG + tristate "Clock driver for MediaTek MT6735 pericfg" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This driver supports MediaTek MT6735 pericfg clocks and resets. + config COMMON_CLK_MT6735_TOPCKGEN tristate "Clock driver for MediaTek MT6735 topckgen" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index e5c1da6e2711..b1a4d18e382d 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) +=3D clk-mtk.o clk-pll.o = clk-gate.o clk-apmixed. =20 obj-$(CONFIG_COMMON_CLK_MT6735_APMIXED) +=3D clk-mt6735-apmixed.o obj-$(CONFIG_COMMON_CLK_MT6735_INFRACFG) +=3D clk-mt6735-infracfg.o +obj-$(CONFIG_COMMON_CLK_MT6735_PERICFG) +=3D clk-mt6735-pericfg.o obj-$(CONFIG_COMMON_CLK_MT6735_TOPCKGEN) +=3D clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6765) +=3D clk-mt6765.o obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) +=3D clk-mt6765-audio.o diff --git a/drivers/clk/mediatek/clk-mt6735-pericfg.c b/drivers/clk/mediat= ek/clk-mt6735-pericfg.c new file mode 100644 index 000000000000..8a01aa63a81e --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6735-pericfg.c @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Yassine Oudjana + */ + +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include + +#define PERI_GLOBALCON_RST0 0x00 +#define PERI_GLOBALCON_PDN0_SET 0x08 +#define PERI_GLOBALCON_PDN0_CLR 0x10 +#define PERI_GLOBALCON_PDN0_STA 0x18 + +struct mt6735_pericfg { + struct clk_onecell_data *clk_data; + struct mtk_reset *reset_data; +}; + +static struct mtk_gate_regs peri_cg_regs =3D { + .set_ofs =3D PERI_GLOBALCON_PDN0_SET, + .clr_ofs =3D PERI_GLOBALCON_PDN0_CLR, + .sta_ofs =3D PERI_GLOBALCON_PDN0_STA, +}; + +static const struct mtk_gate pericfg_gates[] =3D { + { + .id =3D DISP_PWM, + .name =3D "disp_pwm", + .parent_name =3D "disppwm_sel", + .regs =3D &peri_cg_regs, + .shift =3D 0, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D THERM, + .name =3D "therm", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 1, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM1, + .name =3D "pwm1", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 2, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM2, + .name =3D "pwm2", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 3, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM3, + .name =3D "pwm3", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 4, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM4, + .name =3D "pwm4", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 5, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM5, + .name =3D "pwm5", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 6, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM6, + .name =3D "pwm6", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 7, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM7, + .name =3D "pwm7", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 8, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D PWM, + .name =3D "pwm", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 9, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D USB0, + .name =3D "usb0", + .parent_name =3D "usb20_sel", + .regs =3D &peri_cg_regs, + .shift =3D 10, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D IRDA, + .name =3D "irda", + .parent_name =3D "irda_sel", + .regs =3D &peri_cg_regs, + .shift =3D 11, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D APDMA, + .name =3D "apdma", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 12, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_0, + .name =3D "msdc30_0", + .parent_name =3D "msdc30_0_sel", + .regs =3D &peri_cg_regs, + .shift =3D 13, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_1, + .name =3D "msdc30_1", + .parent_name =3D "msdc30_1_sel", + .regs =3D &peri_cg_regs, + .shift =3D 14, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_2, + .name =3D "msdc30_2", + .parent_name =3D "msdc30_2_sel", + .regs =3D &peri_cg_regs, + .shift =3D 15, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D MSDC30_3, + .name =3D "msdc30_3", + .parent_name =3D "msdc30_3_sel", + .regs =3D &peri_cg_regs, + .shift =3D 16, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART0, + .name =3D "uart0", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 17, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART1, + .name =3D "uart1", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 18, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART2, + .name =3D "uart2", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 19, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART3, + .name =3D "uart3", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 20, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D UART4, + .name =3D "uart4", + .parent_name =3D "uart_sel", + .regs =3D &peri_cg_regs, + .shift =3D 21, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D BTIF, + .name =3D "btif", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 22, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C0, + .name =3D "i2c0", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 23, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C1, + .name =3D "i2c1", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 24, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C2, + .name =3D "i2c2", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 25, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D I2C3, + .name =3D "i2c3", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 26, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D AUXADC, + .name =3D "auxadc", + .parent_name =3D "axi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 27, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D SPI0, + .name =3D "spi0", + .parent_name =3D "spi_sel", + .regs =3D &peri_cg_regs, + .shift =3D 28, + .ops =3D &mtk_clk_gate_ops_setclr + }, + { + .id =3D IRTX, + .name =3D "IRTX", + .parent_name =3D "irtx_sel", + .regs =3D &peri_cg_regs, + .shift =3D 29, + .ops =3D &mtk_clk_gate_ops_setclr + }, +}; + +int clk_mt6735_pericfg_probe(struct platform_device *pdev) +{ + void __iomem *base; + struct resource *res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + struct mt6735_pericfg *pericfg; + int ret; + + base =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pericfg =3D devm_kmalloc(&pdev->dev, sizeof(struct mt6735_pericfg), + GFP_KERNEL); + if (!pericfg) + return -ENOMEM; + + pericfg->clk_data =3D mtk_alloc_clk_data(ARRAY_SIZE(pericfg_gates)); + if (!pericfg->clk_data) + return -ENOMEM; + platform_set_drvdata(pdev, pericfg); + + ret =3D mtk_clk_register_gates_with_dev(pdev->dev.of_node, pericfg_gates, + ARRAY_SIZE(pericfg_gates), + pericfg->clk_data, &pdev->dev); + if (ret) { + dev_err(&pdev->dev, "Failed to register gates: %pe\n", + ERR_PTR(ret)); + goto free_clk_data; + } + + ret =3D of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, + pericfg->clk_data); + if (ret) { + dev_err(&pdev->dev, + "Failed to register clock provider: %pe\n", + ERR_PTR(ret)); + goto unregister_gates; + } + + pericfg->reset_data =3D mtk_register_reset_controller(pdev->dev.of_node, = 2, + PERI_GLOBALCON_RST0); + if (IS_ERR(pericfg->reset_data)) { + dev_err(&pdev->dev, "Failed to register reset controller: %pe\n", + pericfg->reset_data); + return PTR_ERR(pericfg->reset_data); + } + + return 0; +unregister_gates: + mtk_clk_unregister_gates(pericfg_gates, ARRAY_SIZE(pericfg_gates), + pericfg->clk_data); +free_clk_data: + mtk_free_clk_data(pericfg->clk_data); + + return ret; +} + +int clk_mt6735_pericfg_remove(struct platform_device *pdev) +{ + struct mt6735_pericfg *pericfg =3D platform_get_drvdata(pdev); + + mtk_unregister_reset_controller(pericfg->reset_data); + of_clk_del_provider(pdev->dev.of_node); + mtk_clk_unregister_gates(pericfg_gates, ARRAY_SIZE(pericfg_gates), + pericfg->clk_data); + mtk_free_clk_data(pericfg->clk_data); + + return 0; +} + +static const struct of_device_id of_match_mt6735_pericfg[] =3D { + { .compatible =3D "mediatek,mt6735-pericfg" }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6735_pericfg =3D { + .probe =3D clk_mt6735_pericfg_probe, + .remove =3D clk_mt6735_pericfg_remove, + .driver =3D { + .name =3D "clk-mt6735-pericfg", + .of_match_table =3D of_match_mt6735_pericfg, + }, +}; +module_platform_driver(clk_mt6735_pericfg); + +MODULE_AUTHOR("Yassine Oudjana "); +MODULE_DESCRIPTION("Mediatek MT6735 pericfg clock driver"); +MODULE_LICENSE("GPL"); --=20 2.36.0