From nobody Sun May 10 12:49:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A21DFC433F5 for ; Tue, 3 May 2022 19:46:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242152AbiECTtq (ORCPT ); Tue, 3 May 2022 15:49:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242094AbiECTte (ORCPT ); Tue, 3 May 2022 15:49:34 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 975942229E; Tue, 3 May 2022 12:46:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651607161; x=1683143161; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CP0I8+L3LjHbkmf03eJINEHNiUWKyiWgZVLpi7cVFIs=; b=mUvJ6UGE0BDV8588hjtqeZ1saHiQxXBk81ou+sXGRzoK7OTAnKOz8Jao iTCR+rgBL2/BqM3jcSl5FRZS5nzaE0g/LIElmRXvAoOTZMkgaJabIWoYV aMU8GQtNxFTWxEyyl5L2XBQLzu7+7KXhQPFYCbUmOZ4+MWety3PgOENf6 0s/CATbprz6ywz9sPgd5MrUUeohU70cD1HfWgxXfMkmvL8670it5yIV06 0AT7AhavlQKLBIc2JkmKyqARemz+ZbRZt2x+PZ+fqDlIvUbINAJX/O/Ir XriGj2JIcjFN942m4EY2OX6PRrmtes/KaQlFh2TVF4LZHTwVA+DcEEh9Z w==; X-IronPort-AV: E=McAfee;i="6400,9594,10336"; a="248114159" X-IronPort-AV: E=Sophos;i="5.91,196,1647327600"; d="scan'208";a="248114159" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 12:46:00 -0700 X-IronPort-AV: E=Sophos;i="5.91,196,1647327600"; d="scan'208";a="584345938" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 12:45:59 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach Subject: [PATCH v2 1/3] dt-bindings: misc: add bindings for Intel HPS Copy Engine Date: Tue, 3 May 2022 12:45:44 -0700 Message-Id: <20220503194546.1287679-2-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220503194546.1287679-1-matthew.gerlach@linux.intel.com> References: <20220503194546.1287679-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matthew Gerlach Add device tree bindings documentation for the Intel Hard Processor System (HPS) Copy Engine. Signed-off-by: Matthew Gerlach --- .../bindings/misc/intel,hps-copy-engine.yaml | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/intel,hps-copy-e= ngine.yaml diff --git a/Documentation/devicetree/bindings/misc/intel,hps-copy-engine.y= aml b/Documentation/devicetree/bindings/misc/intel,hps-copy-engine.yaml new file mode 100644 index 000000000000..74e7da9002f4 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/intel,hps-copy-engine.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2022, Intel Corporation +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/misc/intel,hps-copy-engine.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel HPS Copy Engine + +maintainers: + - Matthew Gerlach + +description: | + The Intel Hard Processor System (HPS) Copy Engine is an IP block used to= copy + a bootable image from host memory to HPS DDR. Additionally, there is a + register the HPS can use to indicate the state of booting the copied ima= ge as + well as a keep-a-live indication to the host. + +properties: + compatible: + items: + - const: intel,hps-copy-engine + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + agilex_hps_bridges: bus@80000000 { + compatible =3D "simple-bus"; + reg =3D <0x80000000 0x60000000>, + <0xf9000000 0x00100000>; + reg-names =3D "axi_h2f", "axi_h2f_lw"; + #address-cells =3D <0x2>; + #size-cells =3D <0x1>; + ranges =3D <0x00000000 0x00000000 0xf9000000 0x00001000>; + + hps_cp_eng@0 { + compatible =3D "intel,hps-copy-engine"; + reg =3D <0x00000000 0x00000000 0x00001000>; + }; + }; --=20 2.25.1 From nobody Sun May 10 12:49:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11629C433F5 for ; Tue, 3 May 2022 19:46:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239444AbiECTtm (ORCPT ); Tue, 3 May 2022 15:49:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242086AbiECTte (ORCPT ); Tue, 3 May 2022 15:49:34 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AED262E6BB; Tue, 3 May 2022 12:46:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651607161; x=1683143161; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GNXzg6lz5FwL3/2NW3SeM/C8p33Q44jpG3a64BmETtg=; b=QZChQDjyj6MjmEQVn1EIvvjoojizTxmxtZjbVMWF6CfQ725LKp46q/rr bPPeJgcaB13/w50qWyLGdIgN13TrqUICiWOL3gUiOmk4Khy+vilEHGUwG iUPWMuGEc9fb93OdSgIOSdDkFUlyDjYWYHw8jw7aJXQurwd6sLcKiSAw2 9G5X1Lmvl/Eze7awQFicv7pYvk4DnY5zSuZ6CWTgwGbY8ajyGyGNO78GC P9EQnb0b6/1AXgib2qRkcjq7WUJdZOw8tadK8r0lfMGFagwDvG0ZouGKD cZAEpRWjfphjIoO2K1ptIt8pamRW+1S/llqG69Cn8BfXtviF7HjuY3qwq Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10336"; a="248114161" X-IronPort-AV: E=Sophos;i="5.91,196,1647327600"; d="scan'208";a="248114161" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 12:46:00 -0700 X-IronPort-AV: E=Sophos;i="5.91,196,1647327600"; d="scan'208";a="584345939" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 12:45:59 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach Subject: [PATCH v2 2/3] dt-bindings: intel: add binding for Intel n6000 Date: Tue, 3 May 2022 12:45:45 -0700 Message-Id: <20220503194546.1287679-3-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220503194546.1287679-1-matthew.gerlach@linux.intel.com> References: <20220503194546.1287679-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matthew Gerlach Add the binding string for the Agilex based Intel n6000 board. Signed-off-by: Matthew Gerlach Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Doc= umentation/devicetree/bindings/arm/intel,socfpga.yaml index 6e043459fcd5..61a454a40e87 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - intel,n5x-socdk + - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk - const: intel,socfpga-agilex =20 --=20 2.25.1 From nobody Sun May 10 12:49:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 247FEC433F5 for ; Tue, 3 May 2022 19:46:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242157AbiECTtw (ORCPT ); Tue, 3 May 2022 15:49:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242106AbiECTtf (ORCPT ); Tue, 3 May 2022 15:49:35 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EEF41EC69; Tue, 3 May 2022 12:46:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1651607162; x=1683143162; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=15VPEkkpNfoHEDQrDJC9rIeebWmswoBg5hQZL9hNclE=; b=CLv7Df7eErjcC4fll0pkV6Dh89yb565cCCltpnCxmRQjjeCcn3uf1Stk xgtMHKc+7S3E3dLJh5fJM0IuxBIzOBcKoM2RAzkEy4dKdGkScI2DxBH/O dsGy8CeFabI10L7PAJihpevqsgwW61e9d3OFmF2gXKg4/0VDACPrJ1Fxb LurIUh2K8vhL08NK5YOhGvEXcUAtvDuHPR1Fi3/aMNpHCB9JNOin3Nzr5 UEl5TVVbUmZ+uUXTKqdHHto57WK1/4wxLtGJQtErzRTTHzzSvQhHX+9WA OFy3WTxp5AzbhpAYuRFmewHXLQK1h5RoMgwZXLEkTw9y164KuAR++UWvn Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10336"; a="248114162" X-IronPort-AV: E=Sophos;i="5.91,196,1647327600"; d="scan'208";a="248114162" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 12:46:00 -0700 X-IronPort-AV: E=Sophos;i="5.91,196,1647327600"; d="scan'208";a="584345940" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 May 2022 12:45:59 -0700 From: matthew.gerlach@linux.intel.com To: dinguyen@kernel.org, robh+dt@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: Matthew Gerlach Subject: [PATCH v2 3/3] arm64: dts: intel: add device tree for n6000 Date: Tue, 3 May 2022 12:45:46 -0700 Message-Id: <20220503194546.1287679-4-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220503194546.1287679-1-matthew.gerlach@linux.intel.com> References: <20220503194546.1287679-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matthew Gerlach Add a device tree for the n6000 instantiation of Agilex Hard Processor System (HPS). Signed-off-by: Matthew Gerlach --- v2: - fix copy engine node name - fix compatible field for copy engine - remove redundant status field - add compatibility field for the board - fix SPDX - fix how osc1 clock frequency is set --- arch/arm64/boot/dts/intel/Makefile | 3 +- .../boot/dts/intel/socfpga_agilex_n6000.dts | 76 +++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel= /Makefile index 0b5477442263..c2a723838344 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D socfpga_agilex_socdk.dtb \ +dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D socfpga_agilex_n6000.dtb \ + socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) +=3D keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm6= 4/boot/dts/intel/socfpga_agilex_n6000.dts new file mode 100644 index 000000000000..6f8b7bf7a53f --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021-2022, Intel Corporation + */ +#include "socfpga_agilex.dtsi" + +/ { + model =3D "SoCFPGA Agilex n6000"; + compatible =3D "intel,socfpga-agilex-n6000", "intel,socfpga-agilex"; + + aliases { + serial0 =3D &uart1; + serial1 =3D &uart0; + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + ethernet2 =3D &gmac2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory { + device_type =3D "memory"; + /* We expect the bootloader to fill in the reg */ + reg =3D <0 0 0 0>; + }; + + soc { + agilex_hps_bridges: bus@80000000 { + compatible =3D "simple-bus"; + reg =3D <0x80000000 0x60000000>, + <0xf9000000 0x00100000>; + reg-names =3D "axi_h2f", "axi_h2f_lw"; + #address-cells =3D <0x2>; + #size-cells =3D <0x1>; + ranges =3D <0x00000000 0x00000000 0xf9000000 0x00001000>; + + hps_cp_eng@0 { + compatible =3D "intel,hps-copy-engine"; + reg =3D <0x00000000 0x00000000 0x00001000>; + }; + }; + }; +}; + +&osc1 { + clock-frequency =3D <25000000>; +}; + +&uart0 { + status =3D "okay"; +}; + +&uart1 { + status =3D "okay"; +}; + +&spi0 { + status =3D "okay"; + + spidev: spidev@0 { + status =3D "okay"; + compatible =3D "linux,spidev"; + spi-max-frequency =3D <25000000>; + reg =3D <0>; + }; +}; + +&watchdog0 { + status =3D "okay"; +}; + +&fpga_mgr { + status =3D "disabled"; +}; --=20 2.25.1